lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// A disasembler class for Mips.
  34 class MipsDisassemblerBase : public MCDisassembler {
  35 public:
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  37                        bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsN64(STI.getFeatureBits() & Mips::FeatureN64),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   virtual ~MipsDisassemblerBase() {}
  43
  44   bool isN64() const { return IsN64; }
  45
  46 private:
  47   bool IsN64;
  48 protected:
  49   bool IsBigEndian;
  50 };
  51
  52 /// A disasembler class for Mips32.
  53 class MipsDisassembler : public MipsDisassemblerBase {
  54   bool IsMicroMips;
  55 public:
  56   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  57       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  58     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  59   }
  60
  61   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  62   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  63   bool hasMips32r6() const {
  64     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  65   }
  66
  67   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  68
  69   bool hasCOP3() const {
  70     // Only present in MIPS-I and MIPS-II
  71     return !hasMips32() && !hasMips3();
  72   }
  73
  74   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  75                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  76                               raw_ostream &VStream,
  77                               raw_ostream &CStream) const override;
  78 };
  79
  80 /// A disasembler class for Mips64.
  81 class Mips64Disassembler : public MipsDisassemblerBase {
  82 public:
  83   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  84                      bool bigEndian) :
  85     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  86
  87   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  88                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  89                               raw_ostream &VStream,
  90                               raw_ostream &CStream) const override;
  91 };
  92
  93 } // end anonymous namespace
  94
  95 // Forward declare these because the autogenerated code will reference them.
  96 // Definitions are further down.
  97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  98                                              unsigned RegNo,
  99                                              uint64_t Address,
 100                                              const void *Decoder);
 101
 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 103                                                  unsigned RegNo,
 104                                                  uint64_t Address,
 105                                                  const void *Decoder);
 106
 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 108                                                unsigned RegNo,
 109                                                uint64_t Address,
 110                                                const void *Decoder);
 111
 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 113                                                    unsigned RegNo,
 114                                                    uint64_t Address,
 115                                                    const void *Decoder);
 116
 117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 118                                              unsigned RegNo,
 119                                              uint64_t Address,
 120                                              const void *Decoder);
 121
 122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 123                                            unsigned Insn,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 128                                             unsigned RegNo,
 129                                             uint64_t Address,
 130                                             const void *Decoder);
 131
 132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 133                                              unsigned RegNo,
 134                                              uint64_t Address,
 135                                              const void *Decoder);
 136
 137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 138                                              unsigned RegNo,
 139                                              uint64_t Address,
 140                                              const void *Decoder);
 141
 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 143                                            unsigned RegNo,
 144                                            uint64_t Address,
 145                                            const void *Decoder);
 146
 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 148                                            unsigned RegNo,
 149                                            uint64_t Address,
 150                                            const void *Decoder);
 151
 152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 153                                              uint64_t Address,
 154                                              const void *Decoder);
 155
 156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 157                                               unsigned Insn,
 158                                               uint64_t Address,
 159                                               const void *Decoder);
 160
 161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 162                                               unsigned RegNo,
 163                                               uint64_t Address,
 164                                               const void *Decoder);
 165
 166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 167                                                 unsigned RegNo,
 168                                                 uint64_t Address,
 169                                                 const void *Decoder);
 170
 171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 182                                                unsigned RegNo,
 183                                                uint64_t Address,
 184                                                const void *Decoder);
 185
 186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 187                                                unsigned RegNo,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 192                                                unsigned RegNo,
 193                                                uint64_t Address,
 194                                                const void *Decoder);
 195
 196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 197                                                unsigned RegNo,
 198                                                uint64_t Address,
 199                                                const void *Decoder);
 200
 201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 202                                                unsigned RegNo,
 203                                                uint64_t Address,
 204                                                const void *Decoder);
 205
 206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 207                                             unsigned RegNo,
 208                                             uint64_t Address,
 209                                             const void *Decoder);
 210
 211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 212                                        unsigned Offset,
 213                                        uint64_t Address,
 214                                        const void *Decoder);
 215
 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 217                                      unsigned Insn,
 218                                      uint64_t Address,
 219                                      const void *Decoder);
 220
 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 222                                          unsigned Offset,
 223                                          uint64_t Address,
 224                                          const void *Decoder);
 225
 226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 227                                          unsigned Offset,
 228                                          uint64_t Address,
 229                                          const void *Decoder);
 230
 231 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 232 // shifted left by 1 bit.
 233 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 234                                          unsigned Offset,
 235                                          uint64_t Address,
 236                                          const void *Decoder);
 237
 238 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 239 // shifted left by 1 bit.
 240 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 241                                        unsigned Insn,
 242                                        uint64_t Address,
 243                                        const void *Decoder);
 244
 245 static DecodeStatus DecodeMem(MCInst &Inst,
 246                               unsigned Insn,
 247                               uint64_t Address,
 248                               const void *Decoder);
 249
 250 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 251                               unsigned Insn,
 252                               uint64_t Address,
 253                               const void *Decoder);
 254
 255 static DecodeStatus DecodeSyncI(MCInst &Inst,
 256                                 unsigned Insn,
 257                                 uint64_t Address,
 258                                 const void *Decoder);
 259
 260 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 261                                     uint64_t Address, const void *Decoder);
 262
 263 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 264                                     unsigned Insn,
 265                                     uint64_t Address,
 266                                     const void *Decoder);
 267
 268 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 269                                      unsigned Insn,
 270                                      uint64_t Address,
 271                                      const void *Decoder);
 272
 273 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 274                                      unsigned Insn,
 275                                      uint64_t Address,
 276                                      const void *Decoder);
 277
 278 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 279                                uint64_t Address,
 280                                const void *Decoder);
 281
 282 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 283                                uint64_t Address,
 284                                const void *Decoder);
 285
 286 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 287                                uint64_t Address,
 288                                const void *Decoder);
 289
 290 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 291                                        unsigned Insn,
 292                                        uint64_t Address,
 293                                        const void *Decoder);
 294
 295 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 296                                        unsigned Value,
 297                                        uint64_t Address,
 298                                        const void *Decoder);
 299
 300 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 301                                     unsigned Value,
 302                                     uint64_t Address,
 303                                     const void *Decoder);
 304
 305 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 306                                   unsigned Value,
 307                                   uint64_t Address,
 308                                   const void *Decoder);
 309
 310 static DecodeStatus DecodeSimm4(MCInst &Inst,
 311                                 unsigned Value,
 312                                 uint64_t Address,
 313                                 const void *Decoder);
 314
 315 static DecodeStatus DecodeSimm16(MCInst &Inst,
 316                                  unsigned Insn,
 317                                  uint64_t Address,
 318                                  const void *Decoder);
 319
 320 // Decode the immediate field of an LSA instruction which
 321 // is off by one.
 322 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 323                                  unsigned Insn,
 324                                  uint64_t Address,
 325                                  const void *Decoder);
 326
 327 static DecodeStatus DecodeInsSize(MCInst &Inst,
 328                                   unsigned Insn,
 329                                   uint64_t Address,
 330                                   const void *Decoder);
 331
 332 static DecodeStatus DecodeExtSize(MCInst &Inst,
 333                                   unsigned Insn,
 334                                   uint64_t Address,
 335                                   const void *Decoder);
 336
 337 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 338                                      uint64_t Address, const void *Decoder);
 339
 340 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 341                                      uint64_t Address, const void *Decoder);
 342
 343 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 344 /// handle.
 345 template <typename InsnType>
 346 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 347                                    const void *Decoder);
 348
 349 template <typename InsnType>
 350 static DecodeStatus
 351 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 352                       const void *Decoder);
 353
 354 template <typename InsnType>
 355 static DecodeStatus
 356 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 357                        const void *Decoder);
 358
 359 template <typename InsnType>
 360 static DecodeStatus
 361 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 362                        const void *Decoder);
 363
 364 template <typename InsnType>
 365 static DecodeStatus
 366 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 367                        const void *Decoder);
 368
 369 template <typename InsnType>
 370 static DecodeStatus
 371 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 372                       const void *Decoder);
 373
 374 template <typename InsnType>
 375 static DecodeStatus
 376 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 377                        const void *Decoder);
 378
 379 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 380                                          uint64_t Address,
 381                                          const void *Decoder);
 382
 383 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 384                                            uint64_t Address,
 385                                            const void *Decoder);
 386
 387 namespace llvm {
 388 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 389               TheMips64elTarget;
 390 }
 391
 392 static MCDisassembler *createMipsDisassembler(
 393                        const Target &T,
 394                        const MCSubtargetInfo &STI,
 395                        MCContext &Ctx) {
 396   return new MipsDisassembler(STI, Ctx, true);
 397 }
 398
 399 static MCDisassembler *createMipselDisassembler(
 400                        const Target &T,
 401                        const MCSubtargetInfo &STI,
 402                        MCContext &Ctx) {
 403   return new MipsDisassembler(STI, Ctx, false);
 404 }
 405
 406 static MCDisassembler *createMips64Disassembler(
 407                        const Target &T,
 408                        const MCSubtargetInfo &STI,
 409                        MCContext &Ctx) {
 410   return new Mips64Disassembler(STI, Ctx, true);
 411 }
 412
 413 static MCDisassembler *createMips64elDisassembler(
 414                        const Target &T,
 415                        const MCSubtargetInfo &STI,
 416                        MCContext &Ctx) {
 417   return new Mips64Disassembler(STI, Ctx, false);
 418 }
 419
 420 extern "C" void LLVMInitializeMipsDisassembler() {
 421   // Register the disassembler.
 422   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 423                                          createMipsDisassembler);
 424   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 425                                          createMipselDisassembler);
 426   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 427                                          createMips64Disassembler);
 428   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 429                                          createMips64elDisassembler);
 430 }
 431
 432 #include "MipsGenDisassemblerTables.inc"
 433
 434 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 435   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 436   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 437   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 438 }
 439
 440 template <typename InsnType>
 441 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 442                                    const void *Decoder) {
 443   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 444   // The size of the n field depends on the element size
 445   // The register class also depends on this.
 446   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 447   unsigned NSize = 0;
 448   DecodeFN RegDecoder = nullptr;
 449   if ((tmp & 0x18) == 0x00) { // INSVE_B
 450     NSize = 4;
 451     RegDecoder = DecodeMSA128BRegisterClass;
 452   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 453     NSize = 3;
 454     RegDecoder = DecodeMSA128HRegisterClass;
 455   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 456     NSize = 2;
 457     RegDecoder = DecodeMSA128WRegisterClass;
 458   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 459     NSize = 1;
 460     RegDecoder = DecodeMSA128DRegisterClass;
 461   } else
 462     llvm_unreachable("Invalid encoding");
 463
 464   assert(NSize != 0 && RegDecoder != nullptr);
 465
 466   // $wd
 467   tmp = fieldFromInstruction(insn, 6, 5);
 468   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 469     return MCDisassembler::Fail;
 470   // $wd_in
 471   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 472     return MCDisassembler::Fail;
 473   // $n
 474   tmp = fieldFromInstruction(insn, 16, NSize);
 475   MI.addOperand(MCOperand::CreateImm(tmp));
 476   // $ws
 477   tmp = fieldFromInstruction(insn, 11, 5);
 478   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 479     return MCDisassembler::Fail;
 480   // $n2
 481   MI.addOperand(MCOperand::CreateImm(0));
 482
 483   return MCDisassembler::Success;
 484 }
 485
 486 template <typename InsnType>
 487 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 488                                           uint64_t Address,
 489                                           const void *Decoder) {
 490   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 491   // (otherwise we would have matched the ADDI instruction from the earlier
 492   // ISA's instead).
 493   //
 494   // We have:
 495   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 496   //      BOVC if rs >= rt
 497   //      BEQZALC if rs == 0 && rt != 0
 498   //      BEQC if rs < rt && rs != 0
 499
 500   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 501   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 502   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 503   bool HasRs = false;
 504
 505   if (Rs >= Rt) {
 506     MI.setOpcode(Mips::BOVC);
 507     HasRs = true;
 508   } else if (Rs != 0 && Rs < Rt) {
 509     MI.setOpcode(Mips::BEQC);
 510     HasRs = true;
 511   } else
 512     MI.setOpcode(Mips::BEQZALC);
 513
 514   if (HasRs)
 515     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 516                                        Rs)));
 517
 518   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 519                                      Rt)));
 520   MI.addOperand(MCOperand::CreateImm(Imm));
 521
 522   return MCDisassembler::Success;
 523 }
 524
 525 template <typename InsnType>
 526 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 527                                            uint64_t Address,
 528                                            const void *Decoder) {
 529   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 530   // (otherwise we would have matched the ADDI instruction from the earlier
 531   // ISA's instead).
 532   //
 533   // We have:
 534   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 535   //      BNVC if rs >= rt
 536   //      BNEZALC if rs == 0 && rt != 0
 537   //      BNEC if rs < rt && rs != 0
 538
 539   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 540   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 541   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 542   bool HasRs = false;
 543
 544   if (Rs >= Rt) {
 545     MI.setOpcode(Mips::BNVC);
 546     HasRs = true;
 547   } else if (Rs != 0 && Rs < Rt) {
 548     MI.setOpcode(Mips::BNEC);
 549     HasRs = true;
 550   } else
 551     MI.setOpcode(Mips::BNEZALC);
 552
 553   if (HasRs)
 554     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 555                                        Rs)));
 556
 557   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 558                                      Rt)));
 559   MI.addOperand(MCOperand::CreateImm(Imm));
 560
 561   return MCDisassembler::Success;
 562 }
 563
 564 template <typename InsnType>
 565 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 566                                            uint64_t Address,
 567                                            const void *Decoder) {
 568   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 569   // (otherwise we would have matched the BLEZL instruction from the earlier
 570   // ISA's instead).
 571   //
 572   // We have:
 573   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 574   //      Invalid if rs == 0
 575   //      BLEZC   if rs == 0  && rt != 0
 576   //      BGEZC   if rs == rt && rt != 0
 577   //      BGEC    if rs != rt && rs != 0  && rt != 0
 578
 579   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 580   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 581   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 582   bool HasRs = false;
 583
 584   if (Rt == 0)
 585     return MCDisassembler::Fail;
 586   else if (Rs == 0)
 587     MI.setOpcode(Mips::BLEZC);
 588   else if (Rs == Rt)
 589     MI.setOpcode(Mips::BGEZC);
 590   else {
 591     HasRs = true;
 592     MI.setOpcode(Mips::BGEC);
 593   }
 594
 595   if (HasRs)
 596     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 597                                        Rs)));
 598
 599   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 600                                      Rt)));
 601
 602   MI.addOperand(MCOperand::CreateImm(Imm));
 603
 604   return MCDisassembler::Success;
 605 }
 606
 607 template <typename InsnType>
 608 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 609                                            uint64_t Address,
 610                                            const void *Decoder) {
 611   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 612   // (otherwise we would have matched the BGTZL instruction from the earlier
 613   // ISA's instead).
 614   //
 615   // We have:
 616   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 617   //      Invalid if rs == 0
 618   //      BGTZC   if rs == 0  && rt != 0
 619   //      BLTZC   if rs == rt && rt != 0
 620   //      BLTC    if rs != rt && rs != 0  && rt != 0
 621
 622   bool HasRs = false;
 623
 624   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 625   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 626   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 627
 628   if (Rt == 0)
 629     return MCDisassembler::Fail;
 630   else if (Rs == 0)
 631     MI.setOpcode(Mips::BGTZC);
 632   else if (Rs == Rt)
 633     MI.setOpcode(Mips::BLTZC);
 634   else {
 635     MI.setOpcode(Mips::BLTC);
 636     HasRs = true;
 637   }
 638
 639   if (HasRs)
 640     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 641                                               Rs)));
 642
 643   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 644                                      Rt)));
 645
 646   MI.addOperand(MCOperand::CreateImm(Imm));
 647
 648   return MCDisassembler::Success;
 649 }
 650
 651 template <typename InsnType>
 652 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 653                                           uint64_t Address,
 654                                           const void *Decoder) {
 655   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 656   // (otherwise we would have matched the BGTZ instruction from the earlier
 657   // ISA's instead).
 658   //
 659   // We have:
 660   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 661   //      BGTZ    if rt == 0
 662   //      BGTZALC if rs == 0 && rt != 0
 663   //      BLTZALC if rs != 0 && rs == rt
 664   //      BLTUC   if rs != 0 && rs != rt
 665
 666   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 667   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 668   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 669   bool HasRs = false;
 670   bool HasRt = false;
 671
 672   if (Rt == 0) {
 673     MI.setOpcode(Mips::BGTZ);
 674     HasRs = true;
 675   } else if (Rs == 0) {
 676     MI.setOpcode(Mips::BGTZALC);
 677     HasRt = true;
 678   } else if (Rs == Rt) {
 679     MI.setOpcode(Mips::BLTZALC);
 680     HasRs = true;
 681   } else {
 682     MI.setOpcode(Mips::BLTUC);
 683     HasRs = true;
 684     HasRt = true;
 685   }
 686
 687   if (HasRs)
 688     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 689                                        Rs)));
 690
 691   if (HasRt)
 692     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 693                                        Rt)));
 694
 695   MI.addOperand(MCOperand::CreateImm(Imm));
 696
 697   return MCDisassembler::Success;
 698 }
 699
 700 template <typename InsnType>
 701 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 702                                            uint64_t Address,
 703                                            const void *Decoder) {
 704   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 705   // (otherwise we would have matched the BLEZL instruction from the earlier
 706   // ISA's instead).
 707   //
 708   // We have:
 709   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 710   //      Invalid   if rs == 0
 711   //      BLEZALC   if rs == 0  && rt != 0
 712   //      BGEZALC   if rs == rt && rt != 0
 713   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 714
 715   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 716   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 717   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 718   bool HasRs = false;
 719
 720   if (Rt == 0)
 721     return MCDisassembler::Fail;
 722   else if (Rs == 0)
 723     MI.setOpcode(Mips::BLEZALC);
 724   else if (Rs == Rt)
 725     MI.setOpcode(Mips::BGEZALC);
 726   else {
 727     HasRs = true;
 728     MI.setOpcode(Mips::BGEUC);
 729   }
 730
 731   if (HasRs)
 732     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 733                                        Rs)));
 734   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 735                                      Rt)));
 736
 737   MI.addOperand(MCOperand::CreateImm(Imm));
 738
 739   return MCDisassembler::Success;
 740 }
 741
 742 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 743 /// according to the given endianess.
 744 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 745                                       uint64_t &Size, uint32_t &Insn,
 746                                       bool IsBigEndian) {
 747   // We want to read exactly 2 Bytes of data.
 748   if (Bytes.size() < 2) {
 749     Size = 0;
 750     return MCDisassembler::Fail;
 751   }
 752
 753   if (IsBigEndian) {
 754     Insn = (Bytes[0] << 8) | Bytes[1];
 755   } else {
 756     Insn = (Bytes[1] << 8) | Bytes[0];
 757   }
 758
 759   return MCDisassembler::Success;
 760 }
 761
 762 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 763 /// according to the given endianess
 764 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 765                                       uint64_t &Size, uint32_t &Insn,
 766                                       bool IsBigEndian, bool IsMicroMips) {
 767   // We want to read exactly 4 Bytes of data.
 768   if (Bytes.size() < 4) {
 769     Size = 0;
 770     return MCDisassembler::Fail;
 771   }
 772
 773   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 774   // always precede the low 16 bits in the instruction stream (that is, they
 775   // are placed at lower addresses in the instruction stream).
 776   //
 777   // microMIPS byte ordering:
 778   //   Big-endian:    0 | 1 | 2 | 3
 779   //   Little-endian: 1 | 0 | 3 | 2
 780
 781   if (IsBigEndian) {
 782     // Encoded as a big-endian 32-bit word in the stream.
 783     Insn =
 784         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 785   } else {
 786     if (IsMicroMips) {
 787       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 788              (Bytes[1] << 24);
 789     } else {
 790       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 791              (Bytes[3] << 24);
 792     }
 793   }
 794
 795   return MCDisassembler::Success;
 796 }
 797
 798 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 799                                               ArrayRef<uint8_t> Bytes,
 800                                               uint64_t Address,
 801                                               raw_ostream &VStream,
 802                                               raw_ostream &CStream) const {
 803   uint32_t Insn;
 804   DecodeStatus Result;
 805
 806   if (IsMicroMips) {
 807     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 808
 809     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 810     // Calling the auto-generated decoder function.
 811     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 812                                this, STI);
 813     if (Result != MCDisassembler::Fail) {
 814       Size = 2;
 815       return Result;
 816     }
 817
 818     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 819     if (Result == MCDisassembler::Fail)
 820       return MCDisassembler::Fail;
 821
 822     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 823     // Calling the auto-generated decoder function.
 824     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 825                                this, STI);
 826     if (Result != MCDisassembler::Fail) {
 827       Size = 4;
 828       return Result;
 829     }
 830     return MCDisassembler::Fail;
 831   }
 832
 833   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 834   if (Result == MCDisassembler::Fail)
 835     return MCDisassembler::Fail;
 836
 837   if (hasCOP3()) {
 838     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 839     Result =
 840         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 841     if (Result != MCDisassembler::Fail) {
 842       Size = 4;
 843       return Result;
 844     }
 845   }
 846
 847   if (hasMips32r6() && isGP64()) {
 848     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 849     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 850                                Address, this, STI);
 851     if (Result != MCDisassembler::Fail) {
 852       Size = 4;
 853       return Result;
 854     }
 855   }
 856
 857   if (hasMips32r6()) {
 858     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 859     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 860                                Address, this, STI);
 861     if (Result != MCDisassembler::Fail) {
 862       Size = 4;
 863       return Result;
 864     }
 865   }
 866
 867   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 868   // Calling the auto-generated decoder function.
 869   Result =
 870       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 871   if (Result != MCDisassembler::Fail) {
 872     Size = 4;
 873     return Result;
 874   }
 875
 876   return MCDisassembler::Fail;
 877 }
 878
 879 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 880                                                 ArrayRef<uint8_t> Bytes,
 881                                                 uint64_t Address,
 882                                                 raw_ostream &VStream,
 883                                                 raw_ostream &CStream) const {
 884   uint32_t Insn;
 885
 886   DecodeStatus Result =
 887       readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 888   if (Result == MCDisassembler::Fail)
 889     return MCDisassembler::Fail;
 890
 891   // Calling the auto-generated decoder function.
 892   Result =
 893       decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
 894   if (Result != MCDisassembler::Fail) {
 895     Size = 4;
 896     return Result;
 897   }
 898   // If we fail to decode in Mips64 decoder space we can try in Mips32
 899   Result =
 900       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 901   if (Result != MCDisassembler::Fail) {
 902     Size = 4;
 903     return Result;
 904   }
 905
 906   return MCDisassembler::Fail;
 907 }
 908
 909 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 910                                                  unsigned RegNo,
 911                                                  uint64_t Address,
 912                                                  const void *Decoder) {
 913
 914   return MCDisassembler::Fail;
 915
 916 }
 917
 918 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 919                                              unsigned RegNo,
 920                                              uint64_t Address,
 921                                              const void *Decoder) {
 922
 923   if (RegNo > 31)
 924     return MCDisassembler::Fail;
 925
 926   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 927   Inst.addOperand(MCOperand::CreateReg(Reg));
 928   return MCDisassembler::Success;
 929 }
 930
 931 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 932                                                unsigned RegNo,
 933                                                uint64_t Address,
 934                                                const void *Decoder) {
 935   if (RegNo > 7)
 936     return MCDisassembler::Fail;
 937   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 938   Inst.addOperand(MCOperand::CreateReg(Reg));
 939   return MCDisassembler::Success;
 940 }
 941
 942 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 943                                                    unsigned RegNo,
 944                                                    uint64_t Address,
 945                                                    const void *Decoder) {
 946   if (RegNo > 7)
 947     return MCDisassembler::Fail;
 948   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
 949   Inst.addOperand(MCOperand::CreateReg(Reg));
 950   return MCDisassembler::Success;
 951 }
 952
 953 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 954                                              unsigned RegNo,
 955                                              uint64_t Address,
 956                                              const void *Decoder) {
 957   if (RegNo > 31)
 958     return MCDisassembler::Fail;
 959   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 960   Inst.addOperand(MCOperand::CreateReg(Reg));
 961   return MCDisassembler::Success;
 962 }
 963
 964 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 965                                            unsigned RegNo,
 966                                            uint64_t Address,
 967                                            const void *Decoder) {
 968   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 969     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 970
 971   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 972 }
 973
 974 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 975                                             unsigned RegNo,
 976                                             uint64_t Address,
 977                                             const void *Decoder) {
 978   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 979 }
 980
 981 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 982                                              unsigned RegNo,
 983                                              uint64_t Address,
 984                                              const void *Decoder) {
 985   if (RegNo > 31)
 986     return MCDisassembler::Fail;
 987
 988   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 989   Inst.addOperand(MCOperand::CreateReg(Reg));
 990   return MCDisassembler::Success;
 991 }
 992
 993 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 994                                              unsigned RegNo,
 995                                              uint64_t Address,
 996                                              const void *Decoder) {
 997   if (RegNo > 31)
 998     return MCDisassembler::Fail;
 999
1000   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1001   Inst.addOperand(MCOperand::CreateReg(Reg));
1002   return MCDisassembler::Success;
1003 }
1004
1005 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1006                                            unsigned RegNo,
1007                                            uint64_t Address,
1008                                            const void *Decoder) {
1009   if (RegNo > 31)
1010     return MCDisassembler::Fail;
1011   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1012   Inst.addOperand(MCOperand::CreateReg(Reg));
1013   return MCDisassembler::Success;
1014 }
1015
1016 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1017                                            unsigned RegNo,
1018                                            uint64_t Address,
1019                                            const void *Decoder) {
1020   if (RegNo > 7)
1021     return MCDisassembler::Fail;
1022   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1023   Inst.addOperand(MCOperand::CreateReg(Reg));
1024   return MCDisassembler::Success;
1025 }
1026
1027 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1028                                              uint64_t Address,
1029                                              const void *Decoder) {
1030   if (RegNo > 31)
1031     return MCDisassembler::Fail;
1032
1033   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1034   Inst.addOperand(MCOperand::CreateReg(Reg));
1035   return MCDisassembler::Success;
1036 }
1037
1038 static DecodeStatus DecodeMem(MCInst &Inst,
1039                               unsigned Insn,
1040                               uint64_t Address,
1041                               const void *Decoder) {
1042   int Offset = SignExtend32<16>(Insn & 0xffff);
1043   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1044   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1045
1046   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1047   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1048
1049   if(Inst.getOpcode() == Mips::SC){
1050     Inst.addOperand(MCOperand::CreateReg(Reg));
1051   }
1052
1053   Inst.addOperand(MCOperand::CreateReg(Reg));
1054   Inst.addOperand(MCOperand::CreateReg(Base));
1055   Inst.addOperand(MCOperand::CreateImm(Offset));
1056
1057   return MCDisassembler::Success;
1058 }
1059
1060 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1061                               unsigned Insn,
1062                               uint64_t Address,
1063                               const void *Decoder) {
1064   int Offset = SignExtend32<16>(Insn & 0xffff);
1065   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1066   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1067
1068   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1069
1070   Inst.addOperand(MCOperand::CreateReg(Base));
1071   Inst.addOperand(MCOperand::CreateImm(Offset));
1072   Inst.addOperand(MCOperand::CreateImm(Hint));
1073
1074   return MCDisassembler::Success;
1075 }
1076
1077 static DecodeStatus DecodeSyncI(MCInst &Inst,
1078                               unsigned Insn,
1079                               uint64_t Address,
1080                               const void *Decoder) {
1081   int Offset = SignExtend32<16>(Insn & 0xffff);
1082   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1083
1084   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1085
1086   Inst.addOperand(MCOperand::CreateReg(Base));
1087   Inst.addOperand(MCOperand::CreateImm(Offset));
1088
1089   return MCDisassembler::Success;
1090 }
1091
1092 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1093                                     uint64_t Address, const void *Decoder) {
1094   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1095   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1096   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1097
1098   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1099   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1100
1101   Inst.addOperand(MCOperand::CreateReg(Reg));
1102   Inst.addOperand(MCOperand::CreateReg(Base));
1103
1104   // The immediate field of an LD/ST instruction is scaled which means it must
1105   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1106   // data format.
1107   // .b - 1 byte
1108   // .h - 2 bytes
1109   // .w - 4 bytes
1110   // .d - 8 bytes
1111   switch(Inst.getOpcode())
1112   {
1113   default:
1114     assert (0 && "Unexpected instruction");
1115     return MCDisassembler::Fail;
1116     break;
1117   case Mips::LD_B:
1118   case Mips::ST_B:
1119     Inst.addOperand(MCOperand::CreateImm(Offset));
1120     break;
1121   case Mips::LD_H:
1122   case Mips::ST_H:
1123     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1124     break;
1125   case Mips::LD_W:
1126   case Mips::ST_W:
1127     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1128     break;
1129   case Mips::LD_D:
1130   case Mips::ST_D:
1131     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1132     break;
1133   }
1134
1135   return MCDisassembler::Success;
1136 }
1137
1138 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1139                                     unsigned Insn,
1140                                     uint64_t Address,
1141                                     const void *Decoder) {
1142   unsigned Offset = Insn & 0xf;
1143   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1144   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1145
1146   switch (Inst.getOpcode()) {
1147     case Mips::LBU16_MM:
1148     case Mips::LHU16_MM:
1149     case Mips::LW16_MM:
1150       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1151             == MCDisassembler::Fail)
1152         return MCDisassembler::Fail;
1153       break;
1154     case Mips::SB16_MM:
1155     case Mips::SH16_MM:
1156     case Mips::SW16_MM:
1157       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1158             == MCDisassembler::Fail)
1159         return MCDisassembler::Fail;
1160       break;
1161   }
1162
1163   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1164         == MCDisassembler::Fail)
1165     return MCDisassembler::Fail;
1166
1167   switch (Inst.getOpcode()) {
1168     case Mips::LBU16_MM:
1169       if (Offset == 0xf)
1170         Inst.addOperand(MCOperand::CreateImm(-1));
1171       else
1172         Inst.addOperand(MCOperand::CreateImm(Offset));
1173       break;
1174     case Mips::SB16_MM:
1175       Inst.addOperand(MCOperand::CreateImm(Offset));
1176       break;
1177     case Mips::LHU16_MM:
1178     case Mips::SH16_MM:
1179       Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1180       break;
1181     case Mips::LW16_MM:
1182     case Mips::SW16_MM:
1183       Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1184       break;
1185   }
1186
1187   return MCDisassembler::Success;
1188 }
1189
1190 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1191                                      unsigned Insn,
1192                                      uint64_t Address,
1193                                      const void *Decoder) {
1194   int Offset = SignExtend32<12>(Insn & 0x0fff);
1195   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1196   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1197
1198   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1199   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1200
1201   switch (Inst.getOpcode()) {
1202   case Mips::SWM32_MM:
1203   case Mips::LWM32_MM:
1204     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1205         == MCDisassembler::Fail)
1206       return MCDisassembler::Fail;
1207     Inst.addOperand(MCOperand::CreateReg(Base));
1208     Inst.addOperand(MCOperand::CreateImm(Offset));
1209     break;
1210   case Mips::SC_MM:
1211     Inst.addOperand(MCOperand::CreateReg(Reg));
1212     // fallthrough
1213   default:
1214     Inst.addOperand(MCOperand::CreateReg(Reg));
1215     Inst.addOperand(MCOperand::CreateReg(Base));
1216     Inst.addOperand(MCOperand::CreateImm(Offset));
1217   }
1218
1219   return MCDisassembler::Success;
1220 }
1221
1222 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1223                                      unsigned Insn,
1224                                      uint64_t Address,
1225                                      const void *Decoder) {
1226   int Offset = SignExtend32<16>(Insn & 0xffff);
1227   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1228   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1229
1230   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1231   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1232
1233   Inst.addOperand(MCOperand::CreateReg(Reg));
1234   Inst.addOperand(MCOperand::CreateReg(Base));
1235   Inst.addOperand(MCOperand::CreateImm(Offset));
1236
1237   return MCDisassembler::Success;
1238 }
1239
1240 static DecodeStatus DecodeFMem(MCInst &Inst,
1241                                unsigned Insn,
1242                                uint64_t Address,
1243                                const void *Decoder) {
1244   int Offset = SignExtend32<16>(Insn & 0xffff);
1245   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1246   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1247
1248   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1249   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1250
1251   Inst.addOperand(MCOperand::CreateReg(Reg));
1252   Inst.addOperand(MCOperand::CreateReg(Base));
1253   Inst.addOperand(MCOperand::CreateImm(Offset));
1254
1255   return MCDisassembler::Success;
1256 }
1257
1258 static DecodeStatus DecodeFMem2(MCInst &Inst,
1259                                unsigned Insn,
1260                                uint64_t Address,
1261                                const void *Decoder) {
1262   int Offset = SignExtend32<16>(Insn & 0xffff);
1263   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1264   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1265
1266   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1267   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1268
1269   Inst.addOperand(MCOperand::CreateReg(Reg));
1270   Inst.addOperand(MCOperand::CreateReg(Base));
1271   Inst.addOperand(MCOperand::CreateImm(Offset));
1272
1273   return MCDisassembler::Success;
1274 }
1275
1276 static DecodeStatus DecodeFMem3(MCInst &Inst,
1277                                unsigned Insn,
1278                                uint64_t Address,
1279                                const void *Decoder) {
1280   int Offset = SignExtend32<16>(Insn & 0xffff);
1281   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1282   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1283
1284   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1285   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1286
1287   Inst.addOperand(MCOperand::CreateReg(Reg));
1288   Inst.addOperand(MCOperand::CreateReg(Base));
1289   Inst.addOperand(MCOperand::CreateImm(Offset));
1290
1291   return MCDisassembler::Success;
1292 }
1293
1294 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1295                                        unsigned Insn,
1296                                        uint64_t Address,
1297                                        const void *Decoder) {
1298   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1299   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1300   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1301
1302   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1303   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1304
1305   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1306     Inst.addOperand(MCOperand::CreateReg(Rt));
1307   }
1308
1309   Inst.addOperand(MCOperand::CreateReg(Rt));
1310   Inst.addOperand(MCOperand::CreateReg(Base));
1311   Inst.addOperand(MCOperand::CreateImm(Offset));
1312
1313   return MCDisassembler::Success;
1314 }
1315
1316 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1317                                               unsigned RegNo,
1318                                               uint64_t Address,
1319                                               const void *Decoder) {
1320   // Currently only hardware register 29 is supported.
1321   if (RegNo != 29)
1322     return  MCDisassembler::Fail;
1323   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1324   return MCDisassembler::Success;
1325 }
1326
1327 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1328                                               unsigned RegNo,
1329                                               uint64_t Address,
1330                                               const void *Decoder) {
1331   if (RegNo > 30 || RegNo %2)
1332     return MCDisassembler::Fail;
1333
1334   ;
1335   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1336   Inst.addOperand(MCOperand::CreateReg(Reg));
1337   return MCDisassembler::Success;
1338 }
1339
1340 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1341                                                 unsigned RegNo,
1342                                                 uint64_t Address,
1343                                                 const void *Decoder) {
1344   if (RegNo >= 4)
1345     return MCDisassembler::Fail;
1346
1347   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1348   Inst.addOperand(MCOperand::CreateReg(Reg));
1349   return MCDisassembler::Success;
1350 }
1351
1352 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1353                                                unsigned RegNo,
1354                                                uint64_t Address,
1355                                                const void *Decoder) {
1356   if (RegNo >= 4)
1357     return MCDisassembler::Fail;
1358
1359   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1360   Inst.addOperand(MCOperand::CreateReg(Reg));
1361   return MCDisassembler::Success;
1362 }
1363
1364 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1365                                                unsigned RegNo,
1366                                                uint64_t Address,
1367                                                const void *Decoder) {
1368   if (RegNo >= 4)
1369     return MCDisassembler::Fail;
1370
1371   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1372   Inst.addOperand(MCOperand::CreateReg(Reg));
1373   return MCDisassembler::Success;
1374 }
1375
1376 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1377                                                unsigned RegNo,
1378                                                uint64_t Address,
1379                                                const void *Decoder) {
1380   if (RegNo > 31)
1381     return MCDisassembler::Fail;
1382
1383   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1384   Inst.addOperand(MCOperand::CreateReg(Reg));
1385   return MCDisassembler::Success;
1386 }
1387
1388 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1389                                                unsigned RegNo,
1390                                                uint64_t Address,
1391                                                const void *Decoder) {
1392   if (RegNo > 31)
1393     return MCDisassembler::Fail;
1394
1395   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1396   Inst.addOperand(MCOperand::CreateReg(Reg));
1397   return MCDisassembler::Success;
1398 }
1399
1400 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1401                                                unsigned RegNo,
1402                                                uint64_t Address,
1403                                                const void *Decoder) {
1404   if (RegNo > 31)
1405     return MCDisassembler::Fail;
1406
1407   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1408   Inst.addOperand(MCOperand::CreateReg(Reg));
1409   return MCDisassembler::Success;
1410 }
1411
1412 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1413                                                unsigned RegNo,
1414                                                uint64_t Address,
1415                                                const void *Decoder) {
1416   if (RegNo > 31)
1417     return MCDisassembler::Fail;
1418
1419   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1420   Inst.addOperand(MCOperand::CreateReg(Reg));
1421   return MCDisassembler::Success;
1422 }
1423
1424 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1425                                                unsigned RegNo,
1426                                                uint64_t Address,
1427                                                const void *Decoder) {
1428   if (RegNo > 7)
1429     return MCDisassembler::Fail;
1430
1431   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1432   Inst.addOperand(MCOperand::CreateReg(Reg));
1433   return MCDisassembler::Success;
1434 }
1435
1436 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1437                                             unsigned RegNo,
1438                                             uint64_t Address,
1439                                             const void *Decoder) {
1440   if (RegNo > 31)
1441     return MCDisassembler::Fail;
1442
1443   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1444   Inst.addOperand(MCOperand::CreateReg(Reg));
1445   return MCDisassembler::Success;
1446 }
1447
1448 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1449                                        unsigned Offset,
1450                                        uint64_t Address,
1451                                        const void *Decoder) {
1452   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1453   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1454   return MCDisassembler::Success;
1455 }
1456
1457 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1458                                      unsigned Insn,
1459                                      uint64_t Address,
1460                                      const void *Decoder) {
1461
1462   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1463   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1464   return MCDisassembler::Success;
1465 }
1466
1467 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1468                                          unsigned Offset,
1469                                          uint64_t Address,
1470                                          const void *Decoder) {
1471   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1472
1473   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1474   return MCDisassembler::Success;
1475 }
1476
1477 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1478                                          unsigned Offset,
1479                                          uint64_t Address,
1480                                          const void *Decoder) {
1481   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1482
1483   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1484   return MCDisassembler::Success;
1485 }
1486
1487 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1488                                          unsigned Offset,
1489                                          uint64_t Address,
1490                                          const void *Decoder) {
1491   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1492   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1493   return MCDisassembler::Success;
1494 }
1495
1496 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1497                                        unsigned Insn,
1498                                        uint64_t Address,
1499                                        const void *Decoder) {
1500   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1501   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1502   return MCDisassembler::Success;
1503 }
1504
1505 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1506                                        unsigned Value,
1507                                        uint64_t Address,
1508                                        const void *Decoder) {
1509   if (Value == 0)
1510     Inst.addOperand(MCOperand::CreateImm(1));
1511   else if (Value == 0x7)
1512     Inst.addOperand(MCOperand::CreateImm(-1));
1513   else
1514     Inst.addOperand(MCOperand::CreateImm(Value << 2));
1515   return MCDisassembler::Success;
1516 }
1517
1518 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1519                                     unsigned Value,
1520                                     uint64_t Address,
1521                                     const void *Decoder) {
1522   Inst.addOperand(MCOperand::CreateImm(Value << 2));
1523   return MCDisassembler::Success;
1524 }
1525
1526 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1527                                   unsigned Value,
1528                                   uint64_t Address,
1529                                   const void *Decoder) {
1530   if (Value == 0x7F)
1531     Inst.addOperand(MCOperand::CreateImm(-1));
1532   else
1533     Inst.addOperand(MCOperand::CreateImm(Value));
1534   return MCDisassembler::Success;
1535 }
1536
1537 static DecodeStatus DecodeSimm4(MCInst &Inst,
1538                                 unsigned Value,
1539                                 uint64_t Address,
1540                                 const void *Decoder) {
1541   Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1542   return MCDisassembler::Success;
1543 }
1544
1545 static DecodeStatus DecodeSimm16(MCInst &Inst,
1546                                  unsigned Insn,
1547                                  uint64_t Address,
1548                                  const void *Decoder) {
1549   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1550   return MCDisassembler::Success;
1551 }
1552
1553 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1554                                  unsigned Insn,
1555                                  uint64_t Address,
1556                                  const void *Decoder) {
1557   // We add one to the immediate field as it was encoded as 'imm - 1'.
1558   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1559   return MCDisassembler::Success;
1560 }
1561
1562 static DecodeStatus DecodeInsSize(MCInst &Inst,
1563                                   unsigned Insn,
1564                                   uint64_t Address,
1565                                   const void *Decoder) {
1566   // First we need to grab the pos(lsb) from MCInst.
1567   int Pos = Inst.getOperand(2).getImm();
1568   int Size = (int) Insn - Pos + 1;
1569   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1570   return MCDisassembler::Success;
1571 }
1572
1573 static DecodeStatus DecodeExtSize(MCInst &Inst,
1574                                   unsigned Insn,
1575                                   uint64_t Address,
1576                                   const void *Decoder) {
1577   int Size = (int) Insn  + 1;
1578   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1579   return MCDisassembler::Success;
1580 }
1581
1582 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1583                                      uint64_t Address, const void *Decoder) {
1584   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1585   return MCDisassembler::Success;
1586 }
1587
1588 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1589                                      uint64_t Address, const void *Decoder) {
1590   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1591   return MCDisassembler::Success;
1592 }
1593
1594 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1595                                          unsigned Insn,
1596                                          uint64_t Address,
1597                                          const void *Decoder) {
1598   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1599                      Mips::S6, Mips::FP};
1600   unsigned RegNum;
1601
1602   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1603   // Empty register lists are not allowed.
1604   if (RegLst == 0)
1605     return MCDisassembler::Fail;
1606
1607   RegNum = RegLst & 0xf;
1608   for (unsigned i = 0; i < RegNum; i++)
1609     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1610
1611   if (RegLst & 0x10)
1612     Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1613
1614   return MCDisassembler::Success;
1615 }
1616
1617 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1618                                            uint64_t Address,
1619                                            const void *Decoder) {
1620   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1621   unsigned RegNum;
1622
1623   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1624   // Empty register lists are not allowed.
1625   if (RegLst == 0)
1626     return MCDisassembler::Fail;
1627
1628   RegNum = RegLst & 0x3;
1629   for (unsigned i = 0; i < RegNum - 1; i++)
1630     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1631
1632   Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1633
1634   return MCDisassembler::Success;
1635 }