1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define DEBUG_TYPE "mips-disassembler"
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 /// A disasembler class for Mips.
34 class MipsDisassemblerBase : public MCDisassembler {
36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
38 : MCDisassembler(STI, Ctx),
39 IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
40 IsBigEndian(IsBigEndian) {}
42 virtual ~MipsDisassemblerBase() {}
44 bool isGP64Bit() const { return IsGP64Bit; }
52 /// A disasembler class for Mips32.
53 class MipsDisassembler : public MipsDisassemblerBase {
56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
57 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
63 bool hasMips32r6() const {
64 return STI.getFeatureBits() & Mips::FeatureMips32r6;
67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
77 raw_ostream &CStream) const override;
80 /// A disasembler class for Mips64.
81 class Mips64Disassembler : public MipsDisassemblerBase {
83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
85 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
88 ArrayRef<uint8_t> Bytes, uint64_t Address,
90 raw_ostream &CStream) const override;
93 } // end anonymous namespace
95 // Forward declare these because the autogenerated code will reference them.
96 // Definitions are further down.
97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
100 const void *Decoder);
102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
105 const void *Decoder);
107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
110 const void *Decoder);
112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
115 const void *Decoder);
117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
120 const void *Decoder);
122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
125 const void *Decoder);
127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
130 const void *Decoder);
132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
135 const void *Decoder);
137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
140 const void *Decoder);
142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
145 const void *Decoder);
147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
150 const void *Decoder);
152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
154 const void *Decoder);
156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
159 const void *Decoder);
161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
164 const void *Decoder);
166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
169 const void *Decoder);
171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
174 const void *Decoder);
176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
179 const void *Decoder);
181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
184 const void *Decoder);
186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
189 const void *Decoder);
191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
194 const void *Decoder);
196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
199 const void *Decoder);
201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
204 const void *Decoder);
206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
209 const void *Decoder);
211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
214 const void *Decoder);
216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
219 const void *Decoder);
221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
224 const void *Decoder);
226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
229 const void *Decoder);
231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
232 // shifted left by 1 bit.
233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
236 const void *Decoder);
238 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
239 // shifted left by 1 bit.
240 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
243 const void *Decoder);
245 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
246 // shifted left by 1 bit.
247 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
250 const void *Decoder);
252 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
253 // shifted left by 1 bit.
254 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
257 const void *Decoder);
259 static DecodeStatus DecodeMem(MCInst &Inst,
262 const void *Decoder);
264 static DecodeStatus DecodeCacheOp(MCInst &Inst,
267 const void *Decoder);
269 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
272 const void *Decoder);
274 static DecodeStatus DecodeSyncI(MCInst &Inst,
277 const void *Decoder);
279 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
285 const void *Decoder);
287 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
290 const void *Decoder);
292 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
295 const void *Decoder);
297 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
300 const void *Decoder);
302 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
304 const void *Decoder);
306 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
308 const void *Decoder);
310 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
312 const void *Decoder);
314 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
317 const void *Decoder);
319 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
322 const void *Decoder);
324 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
327 const void *Decoder);
329 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
332 const void *Decoder);
334 static DecodeStatus DecodeSimm4(MCInst &Inst,
337 const void *Decoder);
339 static DecodeStatus DecodeSimm16(MCInst &Inst,
342 const void *Decoder);
344 // Decode the immediate field of an LSA instruction which
346 static DecodeStatus DecodeLSAImm(MCInst &Inst,
349 const void *Decoder);
351 static DecodeStatus DecodeInsSize(MCInst &Inst,
354 const void *Decoder);
356 static DecodeStatus DecodeExtSize(MCInst &Inst,
359 const void *Decoder);
361 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
362 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
365 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
368 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
374 uint64_t Address, const void *Decoder);
376 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
378 template <typename InsnType>
379 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
380 const void *Decoder);
382 template <typename InsnType>
384 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
385 const void *Decoder);
387 template <typename InsnType>
389 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
390 const void *Decoder);
392 template <typename InsnType>
394 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
395 const void *Decoder);
397 template <typename InsnType>
399 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
400 const void *Decoder);
402 template <typename InsnType>
404 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
405 const void *Decoder);
407 template <typename InsnType>
409 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
410 const void *Decoder);
412 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
414 const void *Decoder);
416 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
418 const void *Decoder);
421 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
425 static MCDisassembler *createMipsDisassembler(
427 const MCSubtargetInfo &STI,
429 return new MipsDisassembler(STI, Ctx, true);
432 static MCDisassembler *createMipselDisassembler(
434 const MCSubtargetInfo &STI,
436 return new MipsDisassembler(STI, Ctx, false);
439 static MCDisassembler *createMips64Disassembler(
441 const MCSubtargetInfo &STI,
443 return new Mips64Disassembler(STI, Ctx, true);
446 static MCDisassembler *createMips64elDisassembler(
448 const MCSubtargetInfo &STI,
450 return new Mips64Disassembler(STI, Ctx, false);
453 extern "C" void LLVMInitializeMipsDisassembler() {
454 // Register the disassembler.
455 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
456 createMipsDisassembler);
457 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
458 createMipselDisassembler);
459 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
460 createMips64Disassembler);
461 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
462 createMips64elDisassembler);
465 #include "MipsGenDisassemblerTables.inc"
467 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
468 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
469 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
470 return *(RegInfo->getRegClass(RC).begin() + RegNo);
473 template <typename InsnType>
474 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
475 const void *Decoder) {
476 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
477 // The size of the n field depends on the element size
478 // The register class also depends on this.
479 InsnType tmp = fieldFromInstruction(insn, 17, 5);
481 DecodeFN RegDecoder = nullptr;
482 if ((tmp & 0x18) == 0x00) { // INSVE_B
484 RegDecoder = DecodeMSA128BRegisterClass;
485 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
487 RegDecoder = DecodeMSA128HRegisterClass;
488 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
490 RegDecoder = DecodeMSA128WRegisterClass;
491 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
493 RegDecoder = DecodeMSA128DRegisterClass;
495 llvm_unreachable("Invalid encoding");
497 assert(NSize != 0 && RegDecoder != nullptr);
500 tmp = fieldFromInstruction(insn, 6, 5);
501 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
502 return MCDisassembler::Fail;
504 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
505 return MCDisassembler::Fail;
507 tmp = fieldFromInstruction(insn, 16, NSize);
508 MI.addOperand(MCOperand::CreateImm(tmp));
510 tmp = fieldFromInstruction(insn, 11, 5);
511 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
512 return MCDisassembler::Fail;
514 MI.addOperand(MCOperand::CreateImm(0));
516 return MCDisassembler::Success;
519 template <typename InsnType>
520 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
522 const void *Decoder) {
523 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
524 // (otherwise we would have matched the ADDI instruction from the earlier
528 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
530 // BEQZALC if rs == 0 && rt != 0
531 // BEQC if rs < rt && rs != 0
533 InsnType Rs = fieldFromInstruction(insn, 21, 5);
534 InsnType Rt = fieldFromInstruction(insn, 16, 5);
535 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
539 MI.setOpcode(Mips::BOVC);
541 } else if (Rs != 0 && Rs < Rt) {
542 MI.setOpcode(Mips::BEQC);
545 MI.setOpcode(Mips::BEQZALC);
548 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
551 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
553 MI.addOperand(MCOperand::CreateImm(Imm));
555 return MCDisassembler::Success;
558 template <typename InsnType>
559 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
561 const void *Decoder) {
562 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
563 // (otherwise we would have matched the ADDI instruction from the earlier
567 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
569 // BNEZALC if rs == 0 && rt != 0
570 // BNEC if rs < rt && rs != 0
572 InsnType Rs = fieldFromInstruction(insn, 21, 5);
573 InsnType Rt = fieldFromInstruction(insn, 16, 5);
574 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
578 MI.setOpcode(Mips::BNVC);
580 } else if (Rs != 0 && Rs < Rt) {
581 MI.setOpcode(Mips::BNEC);
584 MI.setOpcode(Mips::BNEZALC);
587 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
590 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
592 MI.addOperand(MCOperand::CreateImm(Imm));
594 return MCDisassembler::Success;
597 template <typename InsnType>
598 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
600 const void *Decoder) {
601 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
602 // (otherwise we would have matched the BLEZL instruction from the earlier
606 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
607 // Invalid if rs == 0
608 // BLEZC if rs == 0 && rt != 0
609 // BGEZC if rs == rt && rt != 0
610 // BGEC if rs != rt && rs != 0 && rt != 0
612 InsnType Rs = fieldFromInstruction(insn, 21, 5);
613 InsnType Rt = fieldFromInstruction(insn, 16, 5);
614 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
618 return MCDisassembler::Fail;
620 MI.setOpcode(Mips::BLEZC);
622 MI.setOpcode(Mips::BGEZC);
625 MI.setOpcode(Mips::BGEC);
629 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
632 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
635 MI.addOperand(MCOperand::CreateImm(Imm));
637 return MCDisassembler::Success;
640 template <typename InsnType>
641 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
643 const void *Decoder) {
644 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
645 // (otherwise we would have matched the BGTZL instruction from the earlier
649 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
650 // Invalid if rs == 0
651 // BGTZC if rs == 0 && rt != 0
652 // BLTZC if rs == rt && rt != 0
653 // BLTC if rs != rt && rs != 0 && rt != 0
657 InsnType Rs = fieldFromInstruction(insn, 21, 5);
658 InsnType Rt = fieldFromInstruction(insn, 16, 5);
659 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
662 return MCDisassembler::Fail;
664 MI.setOpcode(Mips::BGTZC);
666 MI.setOpcode(Mips::BLTZC);
668 MI.setOpcode(Mips::BLTC);
673 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
676 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
679 MI.addOperand(MCOperand::CreateImm(Imm));
681 return MCDisassembler::Success;
684 template <typename InsnType>
685 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
687 const void *Decoder) {
688 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
689 // (otherwise we would have matched the BGTZ instruction from the earlier
693 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
695 // BGTZALC if rs == 0 && rt != 0
696 // BLTZALC if rs != 0 && rs == rt
697 // BLTUC if rs != 0 && rs != rt
699 InsnType Rs = fieldFromInstruction(insn, 21, 5);
700 InsnType Rt = fieldFromInstruction(insn, 16, 5);
701 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
706 MI.setOpcode(Mips::BGTZ);
708 } else if (Rs == 0) {
709 MI.setOpcode(Mips::BGTZALC);
711 } else if (Rs == Rt) {
712 MI.setOpcode(Mips::BLTZALC);
715 MI.setOpcode(Mips::BLTUC);
721 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
725 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
728 MI.addOperand(MCOperand::CreateImm(Imm));
730 return MCDisassembler::Success;
733 template <typename InsnType>
734 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
736 const void *Decoder) {
737 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
738 // (otherwise we would have matched the BLEZL instruction from the earlier
742 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
743 // Invalid if rs == 0
744 // BLEZALC if rs == 0 && rt != 0
745 // BGEZALC if rs == rt && rt != 0
746 // BGEUC if rs != rt && rs != 0 && rt != 0
748 InsnType Rs = fieldFromInstruction(insn, 21, 5);
749 InsnType Rt = fieldFromInstruction(insn, 16, 5);
750 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
754 return MCDisassembler::Fail;
756 MI.setOpcode(Mips::BLEZALC);
758 MI.setOpcode(Mips::BGEZALC);
761 MI.setOpcode(Mips::BGEUC);
765 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
767 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
770 MI.addOperand(MCOperand::CreateImm(Imm));
772 return MCDisassembler::Success;
775 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
776 /// according to the given endianess.
777 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
778 uint64_t &Size, uint32_t &Insn,
780 // We want to read exactly 2 Bytes of data.
781 if (Bytes.size() < 2) {
783 return MCDisassembler::Fail;
787 Insn = (Bytes[0] << 8) | Bytes[1];
789 Insn = (Bytes[1] << 8) | Bytes[0];
792 return MCDisassembler::Success;
795 /// Read four bytes from the ArrayRef and return 32 bit word sorted
796 /// according to the given endianess
797 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
798 uint64_t &Size, uint32_t &Insn,
799 bool IsBigEndian, bool IsMicroMips) {
800 // We want to read exactly 4 Bytes of data.
801 if (Bytes.size() < 4) {
803 return MCDisassembler::Fail;
806 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
807 // always precede the low 16 bits in the instruction stream (that is, they
808 // are placed at lower addresses in the instruction stream).
810 // microMIPS byte ordering:
811 // Big-endian: 0 | 1 | 2 | 3
812 // Little-endian: 1 | 0 | 3 | 2
815 // Encoded as a big-endian 32-bit word in the stream.
817 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
820 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
823 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
828 return MCDisassembler::Success;
831 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
832 ArrayRef<uint8_t> Bytes,
834 raw_ostream &VStream,
835 raw_ostream &CStream) const {
840 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
842 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
843 // Calling the auto-generated decoder function.
844 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
846 if (Result != MCDisassembler::Fail) {
851 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
852 if (Result == MCDisassembler::Fail)
853 return MCDisassembler::Fail;
855 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
856 // Calling the auto-generated decoder function.
857 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
859 if (Result != MCDisassembler::Fail) {
863 return MCDisassembler::Fail;
866 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
867 if (Result == MCDisassembler::Fail)
868 return MCDisassembler::Fail;
871 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
873 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
874 if (Result != MCDisassembler::Fail) {
880 if (hasMips32r6() && isGP64()) {
881 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
882 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
884 if (Result != MCDisassembler::Fail) {
891 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
892 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
894 if (Result != MCDisassembler::Fail) {
900 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
901 // Calling the auto-generated decoder function.
903 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
904 if (Result != MCDisassembler::Fail) {
909 return MCDisassembler::Fail;
912 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
913 ArrayRef<uint8_t> Bytes,
915 raw_ostream &VStream,
916 raw_ostream &CStream) const {
919 DecodeStatus Result =
920 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
921 if (Result == MCDisassembler::Fail)
922 return MCDisassembler::Fail;
924 // Calling the auto-generated decoder function.
926 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
927 if (Result != MCDisassembler::Fail) {
931 // If we fail to decode in Mips64 decoder space we can try in Mips32
933 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
934 if (Result != MCDisassembler::Fail) {
939 return MCDisassembler::Fail;
942 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
945 const void *Decoder) {
947 return MCDisassembler::Fail;
951 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
954 const void *Decoder) {
957 return MCDisassembler::Fail;
959 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
960 Inst.addOperand(MCOperand::CreateReg(Reg));
961 return MCDisassembler::Success;
964 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
967 const void *Decoder) {
969 return MCDisassembler::Fail;
970 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
971 Inst.addOperand(MCOperand::CreateReg(Reg));
972 return MCDisassembler::Success;
975 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
978 const void *Decoder) {
980 return MCDisassembler::Fail;
981 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
982 Inst.addOperand(MCOperand::CreateReg(Reg));
983 return MCDisassembler::Success;
986 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
989 const void *Decoder) {
991 return MCDisassembler::Fail;
992 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
993 Inst.addOperand(MCOperand::CreateReg(Reg));
994 return MCDisassembler::Success;
997 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1000 const void *Decoder) {
1001 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
1002 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1004 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1007 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1010 const void *Decoder) {
1011 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1014 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1017 const void *Decoder) {
1019 return MCDisassembler::Fail;
1021 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1022 Inst.addOperand(MCOperand::CreateReg(Reg));
1023 return MCDisassembler::Success;
1026 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1029 const void *Decoder) {
1031 return MCDisassembler::Fail;
1033 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1034 Inst.addOperand(MCOperand::CreateReg(Reg));
1035 return MCDisassembler::Success;
1038 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1041 const void *Decoder) {
1043 return MCDisassembler::Fail;
1044 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1045 Inst.addOperand(MCOperand::CreateReg(Reg));
1046 return MCDisassembler::Success;
1049 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1052 const void *Decoder) {
1054 return MCDisassembler::Fail;
1055 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1056 Inst.addOperand(MCOperand::CreateReg(Reg));
1057 return MCDisassembler::Success;
1060 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1062 const void *Decoder) {
1064 return MCDisassembler::Fail;
1066 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1067 Inst.addOperand(MCOperand::CreateReg(Reg));
1068 return MCDisassembler::Success;
1071 static DecodeStatus DecodeMem(MCInst &Inst,
1074 const void *Decoder) {
1075 int Offset = SignExtend32<16>(Insn & 0xffff);
1076 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1077 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1079 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1080 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1082 if(Inst.getOpcode() == Mips::SC ||
1083 Inst.getOpcode() == Mips::SCD){
1084 Inst.addOperand(MCOperand::CreateReg(Reg));
1087 Inst.addOperand(MCOperand::CreateReg(Reg));
1088 Inst.addOperand(MCOperand::CreateReg(Base));
1089 Inst.addOperand(MCOperand::CreateImm(Offset));
1091 return MCDisassembler::Success;
1094 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1097 const void *Decoder) {
1098 int Offset = SignExtend32<16>(Insn & 0xffff);
1099 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1100 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1102 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1104 Inst.addOperand(MCOperand::CreateReg(Base));
1105 Inst.addOperand(MCOperand::CreateImm(Offset));
1106 Inst.addOperand(MCOperand::CreateImm(Hint));
1108 return MCDisassembler::Success;
1111 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1114 const void *Decoder) {
1115 int Offset = SignExtend32<12>(Insn & 0xfff);
1116 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1117 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1119 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1121 Inst.addOperand(MCOperand::CreateReg(Base));
1122 Inst.addOperand(MCOperand::CreateImm(Offset));
1123 Inst.addOperand(MCOperand::CreateImm(Hint));
1125 return MCDisassembler::Success;
1128 static DecodeStatus DecodeSyncI(MCInst &Inst,
1131 const void *Decoder) {
1132 int Offset = SignExtend32<16>(Insn & 0xffff);
1133 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1135 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1137 Inst.addOperand(MCOperand::CreateReg(Base));
1138 Inst.addOperand(MCOperand::CreateImm(Offset));
1140 return MCDisassembler::Success;
1143 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1144 uint64_t Address, const void *Decoder) {
1145 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1146 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1147 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1149 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1150 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1152 Inst.addOperand(MCOperand::CreateReg(Reg));
1153 Inst.addOperand(MCOperand::CreateReg(Base));
1155 // The immediate field of an LD/ST instruction is scaled which means it must
1156 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1162 switch(Inst.getOpcode())
1165 assert (0 && "Unexpected instruction");
1166 return MCDisassembler::Fail;
1170 Inst.addOperand(MCOperand::CreateImm(Offset));
1174 Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1178 Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1182 Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1186 return MCDisassembler::Success;
1189 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1192 const void *Decoder) {
1193 unsigned Offset = Insn & 0xf;
1194 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1195 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1197 switch (Inst.getOpcode()) {
1198 case Mips::LBU16_MM:
1199 case Mips::LHU16_MM:
1201 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1202 == MCDisassembler::Fail)
1203 return MCDisassembler::Fail;
1208 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1209 == MCDisassembler::Fail)
1210 return MCDisassembler::Fail;
1214 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1215 == MCDisassembler::Fail)
1216 return MCDisassembler::Fail;
1218 switch (Inst.getOpcode()) {
1219 case Mips::LBU16_MM:
1221 Inst.addOperand(MCOperand::CreateImm(-1));
1223 Inst.addOperand(MCOperand::CreateImm(Offset));
1226 Inst.addOperand(MCOperand::CreateImm(Offset));
1228 case Mips::LHU16_MM:
1230 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1234 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1238 return MCDisassembler::Success;
1241 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1244 const void *Decoder) {
1245 unsigned Offset = Insn & 0x1F;
1246 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1248 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1250 Inst.addOperand(MCOperand::CreateReg(Reg));
1251 Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1252 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1254 return MCDisassembler::Success;
1257 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1260 const void *Decoder) {
1261 int Offset = SignExtend32<12>(Insn & 0x0fff);
1262 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1263 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1265 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1266 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1268 switch (Inst.getOpcode()) {
1269 case Mips::SWM32_MM:
1270 case Mips::LWM32_MM:
1271 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1272 == MCDisassembler::Fail)
1273 return MCDisassembler::Fail;
1274 Inst.addOperand(MCOperand::CreateReg(Base));
1275 Inst.addOperand(MCOperand::CreateImm(Offset));
1278 Inst.addOperand(MCOperand::CreateReg(Reg));
1281 Inst.addOperand(MCOperand::CreateReg(Reg));
1282 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1283 Inst.addOperand(MCOperand::CreateReg(Reg+1));
1285 Inst.addOperand(MCOperand::CreateReg(Base));
1286 Inst.addOperand(MCOperand::CreateImm(Offset));
1289 return MCDisassembler::Success;
1292 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1295 const void *Decoder) {
1296 int Offset = SignExtend32<16>(Insn & 0xffff);
1297 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1298 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1300 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1301 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1303 Inst.addOperand(MCOperand::CreateReg(Reg));
1304 Inst.addOperand(MCOperand::CreateReg(Base));
1305 Inst.addOperand(MCOperand::CreateImm(Offset));
1307 return MCDisassembler::Success;
1310 static DecodeStatus DecodeFMem(MCInst &Inst,
1313 const void *Decoder) {
1314 int Offset = SignExtend32<16>(Insn & 0xffff);
1315 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1316 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1318 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1319 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1321 Inst.addOperand(MCOperand::CreateReg(Reg));
1322 Inst.addOperand(MCOperand::CreateReg(Base));
1323 Inst.addOperand(MCOperand::CreateImm(Offset));
1325 return MCDisassembler::Success;
1328 static DecodeStatus DecodeFMem2(MCInst &Inst,
1331 const void *Decoder) {
1332 int Offset = SignExtend32<16>(Insn & 0xffff);
1333 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1334 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1336 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1337 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1339 Inst.addOperand(MCOperand::CreateReg(Reg));
1340 Inst.addOperand(MCOperand::CreateReg(Base));
1341 Inst.addOperand(MCOperand::CreateImm(Offset));
1343 return MCDisassembler::Success;
1346 static DecodeStatus DecodeFMem3(MCInst &Inst,
1349 const void *Decoder) {
1350 int Offset = SignExtend32<16>(Insn & 0xffff);
1351 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1352 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1354 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1355 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1357 Inst.addOperand(MCOperand::CreateReg(Reg));
1358 Inst.addOperand(MCOperand::CreateReg(Base));
1359 Inst.addOperand(MCOperand::CreateImm(Offset));
1361 return MCDisassembler::Success;
1364 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1367 const void *Decoder) {
1368 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1369 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1370 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1372 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1373 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1375 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1376 Inst.addOperand(MCOperand::CreateReg(Rt));
1379 Inst.addOperand(MCOperand::CreateReg(Rt));
1380 Inst.addOperand(MCOperand::CreateReg(Base));
1381 Inst.addOperand(MCOperand::CreateImm(Offset));
1383 return MCDisassembler::Success;
1386 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1389 const void *Decoder) {
1390 // Currently only hardware register 29 is supported.
1392 return MCDisassembler::Fail;
1393 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1394 return MCDisassembler::Success;
1397 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1400 const void *Decoder) {
1401 if (RegNo > 30 || RegNo %2)
1402 return MCDisassembler::Fail;
1405 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1406 Inst.addOperand(MCOperand::CreateReg(Reg));
1407 return MCDisassembler::Success;
1410 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1413 const void *Decoder) {
1415 return MCDisassembler::Fail;
1417 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1418 Inst.addOperand(MCOperand::CreateReg(Reg));
1419 return MCDisassembler::Success;
1422 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1425 const void *Decoder) {
1427 return MCDisassembler::Fail;
1429 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1430 Inst.addOperand(MCOperand::CreateReg(Reg));
1431 return MCDisassembler::Success;
1434 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1437 const void *Decoder) {
1439 return MCDisassembler::Fail;
1441 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1442 Inst.addOperand(MCOperand::CreateReg(Reg));
1443 return MCDisassembler::Success;
1446 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1449 const void *Decoder) {
1451 return MCDisassembler::Fail;
1453 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1454 Inst.addOperand(MCOperand::CreateReg(Reg));
1455 return MCDisassembler::Success;
1458 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1461 const void *Decoder) {
1463 return MCDisassembler::Fail;
1465 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1466 Inst.addOperand(MCOperand::CreateReg(Reg));
1467 return MCDisassembler::Success;
1470 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1473 const void *Decoder) {
1475 return MCDisassembler::Fail;
1477 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1478 Inst.addOperand(MCOperand::CreateReg(Reg));
1479 return MCDisassembler::Success;
1482 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1485 const void *Decoder) {
1487 return MCDisassembler::Fail;
1489 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1490 Inst.addOperand(MCOperand::CreateReg(Reg));
1491 return MCDisassembler::Success;
1494 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1497 const void *Decoder) {
1499 return MCDisassembler::Fail;
1501 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1502 Inst.addOperand(MCOperand::CreateReg(Reg));
1503 return MCDisassembler::Success;
1506 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1509 const void *Decoder) {
1511 return MCDisassembler::Fail;
1513 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1514 Inst.addOperand(MCOperand::CreateReg(Reg));
1515 return MCDisassembler::Success;
1518 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1521 const void *Decoder) {
1522 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1523 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1524 return MCDisassembler::Success;
1527 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1530 const void *Decoder) {
1532 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1533 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1534 return MCDisassembler::Success;
1537 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1540 const void *Decoder) {
1541 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1543 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1544 return MCDisassembler::Success;
1547 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1550 const void *Decoder) {
1551 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1553 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1554 return MCDisassembler::Success;
1557 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1560 const void *Decoder) {
1561 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1562 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1563 return MCDisassembler::Success;
1566 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1569 const void *Decoder) {
1570 int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1571 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1572 return MCDisassembler::Success;
1575 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1578 const void *Decoder) {
1579 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1580 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1581 return MCDisassembler::Success;
1584 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1587 const void *Decoder) {
1588 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1589 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1590 return MCDisassembler::Success;
1593 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1596 const void *Decoder) {
1598 Inst.addOperand(MCOperand::CreateImm(1));
1599 else if (Value == 0x7)
1600 Inst.addOperand(MCOperand::CreateImm(-1));
1602 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1603 return MCDisassembler::Success;
1606 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1609 const void *Decoder) {
1610 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1611 return MCDisassembler::Success;
1614 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1617 const void *Decoder) {
1619 Inst.addOperand(MCOperand::CreateImm(-1));
1621 Inst.addOperand(MCOperand::CreateImm(Value));
1622 return MCDisassembler::Success;
1625 static DecodeStatus DecodeSimm4(MCInst &Inst,
1628 const void *Decoder) {
1629 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1630 return MCDisassembler::Success;
1633 static DecodeStatus DecodeSimm16(MCInst &Inst,
1636 const void *Decoder) {
1637 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1638 return MCDisassembler::Success;
1641 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1644 const void *Decoder) {
1645 // We add one to the immediate field as it was encoded as 'imm - 1'.
1646 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1647 return MCDisassembler::Success;
1650 static DecodeStatus DecodeInsSize(MCInst &Inst,
1653 const void *Decoder) {
1654 // First we need to grab the pos(lsb) from MCInst.
1655 int Pos = Inst.getOperand(2).getImm();
1656 int Size = (int) Insn - Pos + 1;
1657 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1658 return MCDisassembler::Success;
1661 static DecodeStatus DecodeExtSize(MCInst &Inst,
1664 const void *Decoder) {
1665 int Size = (int) Insn + 1;
1666 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1667 return MCDisassembler::Success;
1670 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1671 uint64_t Address, const void *Decoder) {
1672 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1673 return MCDisassembler::Success;
1676 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1677 uint64_t Address, const void *Decoder) {
1678 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1679 return MCDisassembler::Success;
1682 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1683 uint64_t Address, const void *Decoder) {
1684 int32_t DecodedValue;
1686 case 0: DecodedValue = 256; break;
1687 case 1: DecodedValue = 257; break;
1688 case 510: DecodedValue = -258; break;
1689 case 511: DecodedValue = -257; break;
1690 default: DecodedValue = SignExtend32<9>(Insn); break;
1692 Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1693 return MCDisassembler::Success;
1696 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1697 uint64_t Address, const void *Decoder) {
1698 // Insn must be >= 0, since it is unsigned that condition is always true.
1700 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1702 Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1703 return MCDisassembler::Success;
1706 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1707 uint64_t Address, const void *Decoder) {
1708 Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1709 return MCDisassembler::Success;
1712 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1715 const void *Decoder) {
1716 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1717 Mips::S6, Mips::FP};
1720 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1721 // Empty register lists are not allowed.
1723 return MCDisassembler::Fail;
1725 RegNum = RegLst & 0xf;
1726 for (unsigned i = 0; i < RegNum; i++)
1727 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1730 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1732 return MCDisassembler::Success;
1735 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1737 const void *Decoder) {
1738 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1741 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1742 // Empty register lists are not allowed.
1744 return MCDisassembler::Fail;
1746 RegNum = RegLst & 0x3;
1747 for (unsigned i = 0; i < RegNum - 1; i++)
1748 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1750 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1752 return MCDisassembler::Success;