lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MathExtras.h"
  22 #include "llvm/Support/MemoryObject.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 typedef MCDisassembler::DecodeStatus DecodeStatus;
  28
  29 namespace {
  30
  31 /// MipsDisassemblerBase - a disasembler class for Mips.
  32 class MipsDisassemblerBase : public MCDisassembler {
  33 public:
  34   /// Constructor     - Initializes the disassembler.
  35   ///
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  37                        bool bigEndian) :
  38     MCDisassembler(STI), RegInfo(Info),
  39     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  40
  41   virtual ~MipsDisassemblerBase() {}
  42
  43   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  44
  45   bool isN64() const { return IsN64; }
  46
  47 private:
  48   OwningPtr<const MCRegisterInfo> RegInfo;
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  61                    bool bigEndian) :
  62     MipsDisassemblerBase(STI, Info, bigEndian) {
  63       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  64     }
  65
  66   /// getInstruction - See MCDisassembler.
  67   virtual DecodeStatus getInstruction(MCInst &instr,
  68                                       uint64_t &size,
  69                                       const MemoryObject &region,
  70                                       uint64_t address,
  71                                       raw_ostream &vStream,
  72                                       raw_ostream &cStream) const;
  73 };
  74
  75
  76 /// Mips64Disassembler - a disasembler class for Mips64.
  77 class Mips64Disassembler : public MipsDisassemblerBase {
  78 public:
  79   /// Constructor     - Initializes the disassembler.
  80   ///
  81   Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  82                      bool bigEndian) :
  83     MipsDisassemblerBase(STI, Info, bigEndian) {}
  84
  85   /// getInstruction - See MCDisassembler.
  86   virtual DecodeStatus getInstruction(MCInst &instr,
  87                                       uint64_t &size,
  88                                       const MemoryObject &region,
  89                                       uint64_t address,
  90                                       raw_ostream &vStream,
  91                                       raw_ostream &cStream) const;
  92 };
  93
  94 } // end anonymous namespace
  95
  96 // Forward declare these because the autogenerated code will reference them.
  97 // Definitions are further down.
  98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  99                                              unsigned RegNo,
 100                                              uint64_t Address,
 101                                              const void *Decoder);
 102
 103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 104                                                  unsigned RegNo,
 105                                                  uint64_t Address,
 106                                                  const void *Decoder);
 107
 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 109                                              unsigned RegNo,
 110                                              uint64_t Address,
 111                                              const void *Decoder);
 112
 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 114                                            unsigned Insn,
 115                                            uint64_t Address,
 116                                            const void *Decoder);
 117
 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 119                                             unsigned RegNo,
 120                                             uint64_t Address,
 121                                             const void *Decoder);
 122
 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 124                                              unsigned RegNo,
 125                                              uint64_t Address,
 126                                              const void *Decoder);
 127
 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 129                                              unsigned RegNo,
 130                                              uint64_t Address,
 131                                              const void *Decoder);
 132
 133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 134                                               unsigned RegNo,
 135                                               uint64_t Address,
 136                                               const void *Decoder);
 137
 138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 139                                            unsigned RegNo,
 140                                            uint64_t Address,
 141                                            const void *Decoder);
 142
 143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 144                                            unsigned RegNo,
 145                                            uint64_t Address,
 146                                            const void *Decoder);
 147
 148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 149                                               unsigned Insn,
 150                                               uint64_t Address,
 151                                               const void *Decoder);
 152
 153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 154                                               unsigned RegNo,
 155                                               uint64_t Address,
 156                                               const void *Decoder);
 157
 158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 159                                                 unsigned RegNo,
 160                                                 uint64_t Address,
 161                                                 const void *Decoder);
 162
 163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 164                                                unsigned RegNo,
 165                                                uint64_t Address,
 166                                                const void *Decoder);
 167
 168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 169                                                unsigned RegNo,
 170                                                uint64_t Address,
 171                                                const void *Decoder);
 172
 173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 174                                                unsigned RegNo,
 175                                                uint64_t Address,
 176                                                const void *Decoder);
 177
 178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 179                                                unsigned RegNo,
 180                                                uint64_t Address,
 181                                                const void *Decoder);
 182
 183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 184                                                unsigned RegNo,
 185                                                uint64_t Address,
 186                                                const void *Decoder);
 187
 188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 189                                                unsigned RegNo,
 190                                                uint64_t Address,
 191                                                const void *Decoder);
 192
 193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 194                                                unsigned RegNo,
 195                                                uint64_t Address,
 196                                                const void *Decoder);
 197
 198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 199                                        unsigned Offset,
 200                                        uint64_t Address,
 201                                        const void *Decoder);
 202
 203 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 204                                      unsigned Insn,
 205                                      uint64_t Address,
 206                                      const void *Decoder);
 207
 208 static DecodeStatus DecodeMem(MCInst &Inst,
 209                               unsigned Insn,
 210                               uint64_t Address,
 211                               const void *Decoder);
 212
 213 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 214                                     uint64_t Address, const void *Decoder);
 215
 216 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 217                                      unsigned Insn,
 218                                      uint64_t Address,
 219                                      const void *Decoder);
 220
 221 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 222                                      unsigned Insn,
 223                                      uint64_t Address,
 224                                      const void *Decoder);
 225
 226 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 227                                uint64_t Address,
 228                                const void *Decoder);
 229
 230 static DecodeStatus DecodeSimm16(MCInst &Inst,
 231                                  unsigned Insn,
 232                                  uint64_t Address,
 233                                  const void *Decoder);
 234
 235 static DecodeStatus DecodeInsSize(MCInst &Inst,
 236                                   unsigned Insn,
 237                                   uint64_t Address,
 238                                   const void *Decoder);
 239
 240 static DecodeStatus DecodeExtSize(MCInst &Inst,
 241                                   unsigned Insn,
 242                                   uint64_t Address,
 243                                   const void *Decoder);
 244
 245 namespace llvm {
 246 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 247               TheMips64elTarget;
 248 }
 249
 250 static MCDisassembler *createMipsDisassembler(
 251                        const Target &T,
 252                        const MCSubtargetInfo &STI) {
 253   return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
 254 }
 255
 256 static MCDisassembler *createMipselDisassembler(
 257                        const Target &T,
 258                        const MCSubtargetInfo &STI) {
 259   return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
 260 }
 261
 262 static MCDisassembler *createMips64Disassembler(
 263                        const Target &T,
 264                        const MCSubtargetInfo &STI) {
 265   return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
 266 }
 267
 268 static MCDisassembler *createMips64elDisassembler(
 269                        const Target &T,
 270                        const MCSubtargetInfo &STI) {
 271   return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
 272 }
 273
 274 extern "C" void LLVMInitializeMipsDisassembler() {
 275   // Register the disassembler.
 276   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 277                                          createMipsDisassembler);
 278   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 279                                          createMipselDisassembler);
 280   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 281                                          createMips64Disassembler);
 282   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 283                                          createMips64elDisassembler);
 284 }
 285
 286
 287 #include "MipsGenDisassemblerTables.inc"
 288
 289   /// readInstruction - read four bytes from the MemoryObject
 290   /// and return 32 bit word sorted according to the given endianess
 291 static DecodeStatus readInstruction32(const MemoryObject &region,
 292                                       uint64_t address,
 293                                       uint64_t &size,
 294                                       uint32_t &insn,
 295                                       bool isBigEndian,
 296                                       bool IsMicroMips) {
 297   uint8_t Bytes[4];
 298
 299   // We want to read exactly 4 Bytes of data.
 300   if (region.readBytes(address, 4, Bytes) == -1) {
 301     size = 0;
 302     return MCDisassembler::Fail;
 303   }
 304
 305   if (isBigEndian) {
 306     // Encoded as a big-endian 32-bit word in the stream.
 307     insn = (Bytes[3] <<  0) |
 308            (Bytes[2] <<  8) |
 309            (Bytes[1] << 16) |
 310            (Bytes[0] << 24);
 311   }
 312   else {
 313     // Encoded as a small-endian 32-bit word in the stream.
 314     // Little-endian byte ordering:
 315     //   mips32r2:   4 | 3 | 2 | 1
 316     //   microMIPS:  2 | 1 | 4 | 3
 317     if (IsMicroMips) {
 318       insn = (Bytes[2] <<  0) |
 319              (Bytes[3] <<  8) |
 320              (Bytes[0] << 16) |
 321              (Bytes[1] << 24);
 322     } else {
 323       insn = (Bytes[0] <<  0) |
 324              (Bytes[1] <<  8) |
 325              (Bytes[2] << 16) |
 326              (Bytes[3] << 24);
 327     }
 328   }
 329
 330   return MCDisassembler::Success;
 331 }
 332
 333 DecodeStatus
 334 MipsDisassembler::getInstruction(MCInst &instr,
 335                                  uint64_t &Size,
 336                                  const MemoryObject &Region,
 337                                  uint64_t Address,
 338                                  raw_ostream &vStream,
 339                                  raw_ostream &cStream) const {
 340   uint32_t Insn;
 341
 342   DecodeStatus Result = readInstruction32(Region, Address, Size,
 343                                           Insn, isBigEndian, IsMicroMips);
 344   if (Result == MCDisassembler::Fail)
 345     return MCDisassembler::Fail;
 346
 347   if (IsMicroMips) {
 348     // Calling the auto-generated decoder function.
 349     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 350                                this, STI);
 351     if (Result != MCDisassembler::Fail) {
 352       Size = 4;
 353       return Result;
 354     }
 355     return MCDisassembler::Fail;
 356   }
 357
 358   // Calling the auto-generated decoder function.
 359   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 360                              this, STI);
 361   if (Result != MCDisassembler::Fail) {
 362     Size = 4;
 363     return Result;
 364   }
 365
 366   return MCDisassembler::Fail;
 367 }
 368
 369 DecodeStatus
 370 Mips64Disassembler::getInstruction(MCInst &instr,
 371                                    uint64_t &Size,
 372                                    const MemoryObject &Region,
 373                                    uint64_t Address,
 374                                    raw_ostream &vStream,
 375                                    raw_ostream &cStream) const {
 376   uint32_t Insn;
 377
 378   DecodeStatus Result = readInstruction32(Region, Address, Size,
 379                                           Insn, isBigEndian, false);
 380   if (Result == MCDisassembler::Fail)
 381     return MCDisassembler::Fail;
 382
 383   // Calling the auto-generated decoder function.
 384   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 385                              this, STI);
 386   if (Result != MCDisassembler::Fail) {
 387     Size = 4;
 388     return Result;
 389   }
 390   // If we fail to decode in Mips64 decoder space we can try in Mips32
 391   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 392                              this, STI);
 393   if (Result != MCDisassembler::Fail) {
 394     Size = 4;
 395     return Result;
 396   }
 397
 398   return MCDisassembler::Fail;
 399 }
 400
 401 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 402   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 403   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
 404 }
 405
 406 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 407                                                  unsigned RegNo,
 408                                                  uint64_t Address,
 409                                                  const void *Decoder) {
 410
 411   return MCDisassembler::Fail;
 412
 413 }
 414
 415 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 416                                              unsigned RegNo,
 417                                              uint64_t Address,
 418                                              const void *Decoder) {
 419
 420   if (RegNo > 31)
 421     return MCDisassembler::Fail;
 422
 423   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 424   Inst.addOperand(MCOperand::CreateReg(Reg));
 425   return MCDisassembler::Success;
 426 }
 427
 428 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 429                                              unsigned RegNo,
 430                                              uint64_t Address,
 431                                              const void *Decoder) {
 432   if (RegNo > 31)
 433     return MCDisassembler::Fail;
 434   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 435   Inst.addOperand(MCOperand::CreateReg(Reg));
 436   return MCDisassembler::Success;
 437 }
 438
 439 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 440                                            unsigned RegNo,
 441                                            uint64_t Address,
 442                                            const void *Decoder) {
 443   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 444     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 445
 446   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 447 }
 448
 449 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 450                                             unsigned RegNo,
 451                                             uint64_t Address,
 452                                             const void *Decoder) {
 453   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 454 }
 455
 456 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 457                                              unsigned RegNo,
 458                                              uint64_t Address,
 459                                              const void *Decoder) {
 460   if (RegNo > 31)
 461     return MCDisassembler::Fail;
 462
 463   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 464   Inst.addOperand(MCOperand::CreateReg(Reg));
 465   return MCDisassembler::Success;
 466 }
 467
 468 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 469                                              unsigned RegNo,
 470                                              uint64_t Address,
 471                                              const void *Decoder) {
 472   if (RegNo > 31)
 473     return MCDisassembler::Fail;
 474
 475   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 476   Inst.addOperand(MCOperand::CreateReg(Reg));
 477   return MCDisassembler::Success;
 478 }
 479
 480 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 481                                               unsigned RegNo,
 482                                               uint64_t Address,
 483                                               const void *Decoder) {
 484   if (RegNo > 31)
 485     return MCDisassembler::Fail;
 486
 487   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 488   Inst.addOperand(MCOperand::CreateReg(Reg));
 489   return MCDisassembler::Success;
 490 }
 491
 492 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 493                                            unsigned RegNo,
 494                                            uint64_t Address,
 495                                            const void *Decoder) {
 496   if (RegNo > 31)
 497     return MCDisassembler::Fail;
 498   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 499   Inst.addOperand(MCOperand::CreateReg(Reg));
 500   return MCDisassembler::Success;
 501 }
 502
 503 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 504                                            unsigned RegNo,
 505                                            uint64_t Address,
 506                                            const void *Decoder) {
 507   if (RegNo > 7)
 508     return MCDisassembler::Fail;
 509   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 510   Inst.addOperand(MCOperand::CreateReg(Reg));
 511   return MCDisassembler::Success;
 512 }
 513
 514 static DecodeStatus DecodeMem(MCInst &Inst,
 515                               unsigned Insn,
 516                               uint64_t Address,
 517                               const void *Decoder) {
 518   int Offset = SignExtend32<16>(Insn & 0xffff);
 519   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 520   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 521
 522   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 523   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 524
 525   if(Inst.getOpcode() == Mips::SC){
 526     Inst.addOperand(MCOperand::CreateReg(Reg));
 527   }
 528
 529   Inst.addOperand(MCOperand::CreateReg(Reg));
 530   Inst.addOperand(MCOperand::CreateReg(Base));
 531   Inst.addOperand(MCOperand::CreateImm(Offset));
 532
 533   return MCDisassembler::Success;
 534 }
 535
 536 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 537                                     uint64_t Address, const void *Decoder) {
 538   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 539   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 540   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 541
 542   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 543   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 544
 545   Inst.addOperand(MCOperand::CreateReg(Reg));
 546   Inst.addOperand(MCOperand::CreateReg(Base));
 547   Inst.addOperand(MCOperand::CreateImm(Offset));
 548
 549   return MCDisassembler::Success;
 550 }
 551
 552 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 553                                      unsigned Insn,
 554                                      uint64_t Address,
 555                                      const void *Decoder) {
 556   int Offset = SignExtend32<12>(Insn & 0x0fff);
 557   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 558   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 559
 560   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 561   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 562
 563   Inst.addOperand(MCOperand::CreateReg(Reg));
 564   Inst.addOperand(MCOperand::CreateReg(Base));
 565   Inst.addOperand(MCOperand::CreateImm(Offset));
 566
 567   return MCDisassembler::Success;
 568 }
 569
 570 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 571                                      unsigned Insn,
 572                                      uint64_t Address,
 573                                      const void *Decoder) {
 574   int Offset = SignExtend32<16>(Insn & 0xffff);
 575   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 576   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 577
 578   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 579   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 580
 581   Inst.addOperand(MCOperand::CreateReg(Reg));
 582   Inst.addOperand(MCOperand::CreateReg(Base));
 583   Inst.addOperand(MCOperand::CreateImm(Offset));
 584
 585   return MCDisassembler::Success;
 586 }
 587
 588 static DecodeStatus DecodeFMem(MCInst &Inst,
 589                                unsigned Insn,
 590                                uint64_t Address,
 591                                const void *Decoder) {
 592   int Offset = SignExtend32<16>(Insn & 0xffff);
 593   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 594   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 595
 596   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
 597   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 598
 599   Inst.addOperand(MCOperand::CreateReg(Reg));
 600   Inst.addOperand(MCOperand::CreateReg(Base));
 601   Inst.addOperand(MCOperand::CreateImm(Offset));
 602
 603   return MCDisassembler::Success;
 604 }
 605
 606
 607 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 608                                               unsigned RegNo,
 609                                               uint64_t Address,
 610                                               const void *Decoder) {
 611   // Currently only hardware register 29 is supported.
 612   if (RegNo != 29)
 613     return  MCDisassembler::Fail;
 614   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
 615   return MCDisassembler::Success;
 616 }
 617
 618 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 619                                               unsigned RegNo,
 620                                               uint64_t Address,
 621                                               const void *Decoder) {
 622   if (RegNo > 30 || RegNo %2)
 623     return MCDisassembler::Fail;
 624
 625   ;
 626   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
 627   Inst.addOperand(MCOperand::CreateReg(Reg));
 628   return MCDisassembler::Success;
 629 }
 630
 631 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 632                                                 unsigned RegNo,
 633                                                 uint64_t Address,
 634                                                 const void *Decoder) {
 635   if (RegNo >= 4)
 636     return MCDisassembler::Fail;
 637
 638   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
 639   Inst.addOperand(MCOperand::CreateReg(Reg));
 640   return MCDisassembler::Success;
 641 }
 642
 643 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 644                                                unsigned RegNo,
 645                                                uint64_t Address,
 646                                                const void *Decoder) {
 647   if (RegNo >= 4)
 648     return MCDisassembler::Fail;
 649
 650   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
 651   Inst.addOperand(MCOperand::CreateReg(Reg));
 652   return MCDisassembler::Success;
 653 }
 654
 655 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 656                                                unsigned RegNo,
 657                                                uint64_t Address,
 658                                                const void *Decoder) {
 659   if (RegNo >= 4)
 660     return MCDisassembler::Fail;
 661
 662   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
 663   Inst.addOperand(MCOperand::CreateReg(Reg));
 664   return MCDisassembler::Success;
 665 }
 666
 667 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 668                                                unsigned RegNo,
 669                                                uint64_t Address,
 670                                                const void *Decoder) {
 671   if (RegNo > 31)
 672     return MCDisassembler::Fail;
 673
 674   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
 675   Inst.addOperand(MCOperand::CreateReg(Reg));
 676   return MCDisassembler::Success;
 677 }
 678
 679 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 680                                                unsigned RegNo,
 681                                                uint64_t Address,
 682                                                const void *Decoder) {
 683   if (RegNo > 31)
 684     return MCDisassembler::Fail;
 685
 686   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
 687   Inst.addOperand(MCOperand::CreateReg(Reg));
 688   return MCDisassembler::Success;
 689 }
 690
 691 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 692                                                unsigned RegNo,
 693                                                uint64_t Address,
 694                                                const void *Decoder) {
 695   if (RegNo > 31)
 696     return MCDisassembler::Fail;
 697
 698   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
 699   Inst.addOperand(MCOperand::CreateReg(Reg));
 700   return MCDisassembler::Success;
 701 }
 702
 703 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 704                                                unsigned RegNo,
 705                                                uint64_t Address,
 706                                                const void *Decoder) {
 707   if (RegNo > 31)
 708     return MCDisassembler::Fail;
 709
 710   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
 711   Inst.addOperand(MCOperand::CreateReg(Reg));
 712   return MCDisassembler::Success;
 713 }
 714
 715 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 716                                                unsigned RegNo,
 717                                                uint64_t Address,
 718                                                const void *Decoder) {
 719   if (RegNo > 7)
 720     return MCDisassembler::Fail;
 721
 722   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
 723   Inst.addOperand(MCOperand::CreateReg(Reg));
 724   return MCDisassembler::Success;
 725 }
 726
 727 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 728                                        unsigned Offset,
 729                                        uint64_t Address,
 730                                        const void *Decoder) {
 731   unsigned BranchOffset = Offset & 0xffff;
 732   BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
 733   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 734   return MCDisassembler::Success;
 735 }
 736
 737 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 738                                      unsigned Insn,
 739                                      uint64_t Address,
 740                                      const void *Decoder) {
 741
 742   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
 743   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 744   return MCDisassembler::Success;
 745 }
 746
 747
 748 static DecodeStatus DecodeSimm16(MCInst &Inst,
 749                                  unsigned Insn,
 750                                  uint64_t Address,
 751                                  const void *Decoder) {
 752   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
 753   return MCDisassembler::Success;
 754 }
 755
 756 static DecodeStatus DecodeInsSize(MCInst &Inst,
 757                                   unsigned Insn,
 758                                   uint64_t Address,
 759                                   const void *Decoder) {
 760   // First we need to grab the pos(lsb) from MCInst.
 761   int Pos = Inst.getOperand(2).getImm();
 762   int Size = (int) Insn - Pos + 1;
 763   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 764   return MCDisassembler::Success;
 765 }
 766
 767 static DecodeStatus DecodeExtSize(MCInst &Inst,
 768                                   unsigned Insn,
 769                                   uint64_t Address,
 770                                   const void *Decoder) {
 771   int Size = (int) Insn  + 1;
 772   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 773   return MCDisassembler::Success;
 774 }