lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MathExtras.h"
  22 #include "llvm/Support/MemoryObject.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 typedef MCDisassembler::DecodeStatus DecodeStatus;
  28
  29 namespace {
  30
  31 /// MipsDisassemblerBase - a disasembler class for Mips.
  32 class MipsDisassemblerBase : public MCDisassembler {
  33 public:
  34   /// Constructor     - Initializes the disassembler.
  35   ///
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  37                        bool bigEndian) :
  38     MCDisassembler(STI), RegInfo(Info),
  39     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  40
  41   virtual ~MipsDisassemblerBase() {}
  42
  43   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  44
  45   bool isN64() const { return IsN64; }
  46
  47 private:
  48   OwningPtr<const MCRegisterInfo> RegInfo;
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  61                    bool bigEndian) :
  62     MipsDisassemblerBase(STI, Info, bigEndian) {
  63       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  64     }
  65
  66   /// getInstruction - See MCDisassembler.
  67   virtual DecodeStatus getInstruction(MCInst &instr,
  68                                       uint64_t &size,
  69                                       const MemoryObject &region,
  70                                       uint64_t address,
  71                                       raw_ostream &vStream,
  72                                       raw_ostream &cStream) const;
  73 };
  74
  75
  76 /// Mips64Disassembler - a disasembler class for Mips64.
  77 class Mips64Disassembler : public MipsDisassemblerBase {
  78 public:
  79   /// Constructor     - Initializes the disassembler.
  80   ///
  81   Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  82                      bool bigEndian) :
  83     MipsDisassemblerBase(STI, Info, bigEndian) {}
  84
  85   /// getInstruction - See MCDisassembler.
  86   virtual DecodeStatus getInstruction(MCInst &instr,
  87                                       uint64_t &size,
  88                                       const MemoryObject &region,
  89                                       uint64_t address,
  90                                       raw_ostream &vStream,
  91                                       raw_ostream &cStream) const;
  92 };
  93
  94 } // end anonymous namespace
  95
  96 // Forward declare these because the autogenerated code will reference them.
  97 // Definitions are further down.
  98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  99                                              unsigned RegNo,
 100                                              uint64_t Address,
 101                                              const void *Decoder);
 102
 103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 104                                                  unsigned RegNo,
 105                                                  uint64_t Address,
 106                                                  const void *Decoder);
 107
 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 109                                              unsigned RegNo,
 110                                              uint64_t Address,
 111                                              const void *Decoder);
 112
 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 114                                            unsigned Insn,
 115                                            uint64_t Address,
 116                                            const void *Decoder);
 117
 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 119                                             unsigned RegNo,
 120                                             uint64_t Address,
 121                                             const void *Decoder);
 122
 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 124                                              unsigned RegNo,
 125                                              uint64_t Address,
 126                                              const void *Decoder);
 127
 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 129                                              unsigned RegNo,
 130                                              uint64_t Address,
 131                                              const void *Decoder);
 132
 133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 134                                               unsigned RegNo,
 135                                               uint64_t Address,
 136                                               const void *Decoder);
 137
 138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 139                                            unsigned RegNo,
 140                                            uint64_t Address,
 141                                            const void *Decoder);
 142
 143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 144                                            unsigned RegNo,
 145                                            uint64_t Address,
 146                                            const void *Decoder);
 147
 148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 149                                               unsigned Insn,
 150                                               uint64_t Address,
 151                                               const void *Decoder);
 152
 153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 154                                               unsigned RegNo,
 155                                               uint64_t Address,
 156                                               const void *Decoder);
 157
 158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 159                                                 unsigned RegNo,
 160                                                 uint64_t Address,
 161                                                 const void *Decoder);
 162
 163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 164                                                unsigned RegNo,
 165                                                uint64_t Address,
 166                                                const void *Decoder);
 167
 168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 169                                                unsigned RegNo,
 170                                                uint64_t Address,
 171                                                const void *Decoder);
 172
 173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 174                                                unsigned RegNo,
 175                                                uint64_t Address,
 176                                                const void *Decoder);
 177
 178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 179                                                unsigned RegNo,
 180                                                uint64_t Address,
 181                                                const void *Decoder);
 182
 183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 184                                                unsigned RegNo,
 185                                                uint64_t Address,
 186                                                const void *Decoder);
 187
 188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 189                                                unsigned RegNo,
 190                                                uint64_t Address,
 191                                                const void *Decoder);
 192
 193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 194                                                unsigned RegNo,
 195                                                uint64_t Address,
 196                                                const void *Decoder);
 197
 198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 199                                        unsigned Offset,
 200                                        uint64_t Address,
 201                                        const void *Decoder);
 202
 203 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 204                                      unsigned Insn,
 205                                      uint64_t Address,
 206                                      const void *Decoder);
 207
 208 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 209 // shifted left by 1 bit.
 210 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 211                                        unsigned Insn,
 212                                        uint64_t Address,
 213                                        const void *Decoder);
 214
 215 static DecodeStatus DecodeMem(MCInst &Inst,
 216                               unsigned Insn,
 217                               uint64_t Address,
 218                               const void *Decoder);
 219
 220 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 221                                     uint64_t Address, const void *Decoder);
 222
 223 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 224                                      unsigned Insn,
 225                                      uint64_t Address,
 226                                      const void *Decoder);
 227
 228 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 229                                      unsigned Insn,
 230                                      uint64_t Address,
 231                                      const void *Decoder);
 232
 233 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 234                                uint64_t Address,
 235                                const void *Decoder);
 236
 237 static DecodeStatus DecodeSimm16(MCInst &Inst,
 238                                  unsigned Insn,
 239                                  uint64_t Address,
 240                                  const void *Decoder);
 241
 242 static DecodeStatus DecodeInsSize(MCInst &Inst,
 243                                   unsigned Insn,
 244                                   uint64_t Address,
 245                                   const void *Decoder);
 246
 247 static DecodeStatus DecodeExtSize(MCInst &Inst,
 248                                   unsigned Insn,
 249                                   uint64_t Address,
 250                                   const void *Decoder);
 251
 252 namespace llvm {
 253 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 254               TheMips64elTarget;
 255 }
 256
 257 static MCDisassembler *createMipsDisassembler(
 258                        const Target &T,
 259                        const MCSubtargetInfo &STI) {
 260   return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
 261 }
 262
 263 static MCDisassembler *createMipselDisassembler(
 264                        const Target &T,
 265                        const MCSubtargetInfo &STI) {
 266   return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
 267 }
 268
 269 static MCDisassembler *createMips64Disassembler(
 270                        const Target &T,
 271                        const MCSubtargetInfo &STI) {
 272   return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
 273 }
 274
 275 static MCDisassembler *createMips64elDisassembler(
 276                        const Target &T,
 277                        const MCSubtargetInfo &STI) {
 278   return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
 279 }
 280
 281 extern "C" void LLVMInitializeMipsDisassembler() {
 282   // Register the disassembler.
 283   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 284                                          createMipsDisassembler);
 285   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 286                                          createMipselDisassembler);
 287   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 288                                          createMips64Disassembler);
 289   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 290                                          createMips64elDisassembler);
 291 }
 292
 293
 294 #include "MipsGenDisassemblerTables.inc"
 295
 296   /// readInstruction - read four bytes from the MemoryObject
 297   /// and return 32 bit word sorted according to the given endianess
 298 static DecodeStatus readInstruction32(const MemoryObject &region,
 299                                       uint64_t address,
 300                                       uint64_t &size,
 301                                       uint32_t &insn,
 302                                       bool isBigEndian,
 303                                       bool IsMicroMips) {
 304   uint8_t Bytes[4];
 305
 306   // We want to read exactly 4 Bytes of data.
 307   if (region.readBytes(address, 4, Bytes) == -1) {
 308     size = 0;
 309     return MCDisassembler::Fail;
 310   }
 311
 312   if (isBigEndian) {
 313     // Encoded as a big-endian 32-bit word in the stream.
 314     insn = (Bytes[3] <<  0) |
 315            (Bytes[2] <<  8) |
 316            (Bytes[1] << 16) |
 317            (Bytes[0] << 24);
 318   }
 319   else {
 320     // Encoded as a small-endian 32-bit word in the stream.
 321     // Little-endian byte ordering:
 322     //   mips32r2:   4 | 3 | 2 | 1
 323     //   microMIPS:  2 | 1 | 4 | 3
 324     if (IsMicroMips) {
 325       insn = (Bytes[2] <<  0) |
 326              (Bytes[3] <<  8) |
 327              (Bytes[0] << 16) |
 328              (Bytes[1] << 24);
 329     } else {
 330       insn = (Bytes[0] <<  0) |
 331              (Bytes[1] <<  8) |
 332              (Bytes[2] << 16) |
 333              (Bytes[3] << 24);
 334     }
 335   }
 336
 337   return MCDisassembler::Success;
 338 }
 339
 340 DecodeStatus
 341 MipsDisassembler::getInstruction(MCInst &instr,
 342                                  uint64_t &Size,
 343                                  const MemoryObject &Region,
 344                                  uint64_t Address,
 345                                  raw_ostream &vStream,
 346                                  raw_ostream &cStream) const {
 347   uint32_t Insn;
 348
 349   DecodeStatus Result = readInstruction32(Region, Address, Size,
 350                                           Insn, isBigEndian, IsMicroMips);
 351   if (Result == MCDisassembler::Fail)
 352     return MCDisassembler::Fail;
 353
 354   if (IsMicroMips) {
 355     // Calling the auto-generated decoder function.
 356     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 357                                this, STI);
 358     if (Result != MCDisassembler::Fail) {
 359       Size = 4;
 360       return Result;
 361     }
 362     return MCDisassembler::Fail;
 363   }
 364
 365   // Calling the auto-generated decoder function.
 366   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 367                              this, STI);
 368   if (Result != MCDisassembler::Fail) {
 369     Size = 4;
 370     return Result;
 371   }
 372
 373   return MCDisassembler::Fail;
 374 }
 375
 376 DecodeStatus
 377 Mips64Disassembler::getInstruction(MCInst &instr,
 378                                    uint64_t &Size,
 379                                    const MemoryObject &Region,
 380                                    uint64_t Address,
 381                                    raw_ostream &vStream,
 382                                    raw_ostream &cStream) const {
 383   uint32_t Insn;
 384
 385   DecodeStatus Result = readInstruction32(Region, Address, Size,
 386                                           Insn, isBigEndian, false);
 387   if (Result == MCDisassembler::Fail)
 388     return MCDisassembler::Fail;
 389
 390   // Calling the auto-generated decoder function.
 391   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 392                              this, STI);
 393   if (Result != MCDisassembler::Fail) {
 394     Size = 4;
 395     return Result;
 396   }
 397   // If we fail to decode in Mips64 decoder space we can try in Mips32
 398   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 399                              this, STI);
 400   if (Result != MCDisassembler::Fail) {
 401     Size = 4;
 402     return Result;
 403   }
 404
 405   return MCDisassembler::Fail;
 406 }
 407
 408 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 409   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 410   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
 411 }
 412
 413 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 414                                                  unsigned RegNo,
 415                                                  uint64_t Address,
 416                                                  const void *Decoder) {
 417
 418   return MCDisassembler::Fail;
 419
 420 }
 421
 422 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 423                                              unsigned RegNo,
 424                                              uint64_t Address,
 425                                              const void *Decoder) {
 426
 427   if (RegNo > 31)
 428     return MCDisassembler::Fail;
 429
 430   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 431   Inst.addOperand(MCOperand::CreateReg(Reg));
 432   return MCDisassembler::Success;
 433 }
 434
 435 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 436                                              unsigned RegNo,
 437                                              uint64_t Address,
 438                                              const void *Decoder) {
 439   if (RegNo > 31)
 440     return MCDisassembler::Fail;
 441   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 442   Inst.addOperand(MCOperand::CreateReg(Reg));
 443   return MCDisassembler::Success;
 444 }
 445
 446 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 447                                            unsigned RegNo,
 448                                            uint64_t Address,
 449                                            const void *Decoder) {
 450   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 451     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 452
 453   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 454 }
 455
 456 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 457                                             unsigned RegNo,
 458                                             uint64_t Address,
 459                                             const void *Decoder) {
 460   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 461 }
 462
 463 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 464                                              unsigned RegNo,
 465                                              uint64_t Address,
 466                                              const void *Decoder) {
 467   if (RegNo > 31)
 468     return MCDisassembler::Fail;
 469
 470   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 471   Inst.addOperand(MCOperand::CreateReg(Reg));
 472   return MCDisassembler::Success;
 473 }
 474
 475 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 476                                              unsigned RegNo,
 477                                              uint64_t Address,
 478                                              const void *Decoder) {
 479   if (RegNo > 31)
 480     return MCDisassembler::Fail;
 481
 482   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 483   Inst.addOperand(MCOperand::CreateReg(Reg));
 484   return MCDisassembler::Success;
 485 }
 486
 487 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 488                                               unsigned RegNo,
 489                                               uint64_t Address,
 490                                               const void *Decoder) {
 491   if (RegNo > 31)
 492     return MCDisassembler::Fail;
 493
 494   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 495   Inst.addOperand(MCOperand::CreateReg(Reg));
 496   return MCDisassembler::Success;
 497 }
 498
 499 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 500                                            unsigned RegNo,
 501                                            uint64_t Address,
 502                                            const void *Decoder) {
 503   if (RegNo > 31)
 504     return MCDisassembler::Fail;
 505   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 506   Inst.addOperand(MCOperand::CreateReg(Reg));
 507   return MCDisassembler::Success;
 508 }
 509
 510 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 511                                            unsigned RegNo,
 512                                            uint64_t Address,
 513                                            const void *Decoder) {
 514   if (RegNo > 7)
 515     return MCDisassembler::Fail;
 516   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 517   Inst.addOperand(MCOperand::CreateReg(Reg));
 518   return MCDisassembler::Success;
 519 }
 520
 521 static DecodeStatus DecodeMem(MCInst &Inst,
 522                               unsigned Insn,
 523                               uint64_t Address,
 524                               const void *Decoder) {
 525   int Offset = SignExtend32<16>(Insn & 0xffff);
 526   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 527   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 528
 529   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 530   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 531
 532   if(Inst.getOpcode() == Mips::SC){
 533     Inst.addOperand(MCOperand::CreateReg(Reg));
 534   }
 535
 536   Inst.addOperand(MCOperand::CreateReg(Reg));
 537   Inst.addOperand(MCOperand::CreateReg(Base));
 538   Inst.addOperand(MCOperand::CreateImm(Offset));
 539
 540   return MCDisassembler::Success;
 541 }
 542
 543 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 544                                     uint64_t Address, const void *Decoder) {
 545   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 546   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 547   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 548
 549   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 550   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 551
 552   Inst.addOperand(MCOperand::CreateReg(Reg));
 553   Inst.addOperand(MCOperand::CreateReg(Base));
 554   Inst.addOperand(MCOperand::CreateImm(Offset));
 555
 556   return MCDisassembler::Success;
 557 }
 558
 559 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 560                                      unsigned Insn,
 561                                      uint64_t Address,
 562                                      const void *Decoder) {
 563   int Offset = SignExtend32<12>(Insn & 0x0fff);
 564   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 565   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 566
 567   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 568   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 569
 570   Inst.addOperand(MCOperand::CreateReg(Reg));
 571   Inst.addOperand(MCOperand::CreateReg(Base));
 572   Inst.addOperand(MCOperand::CreateImm(Offset));
 573
 574   return MCDisassembler::Success;
 575 }
 576
 577 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 578                                      unsigned Insn,
 579                                      uint64_t Address,
 580                                      const void *Decoder) {
 581   int Offset = SignExtend32<16>(Insn & 0xffff);
 582   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 583   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 584
 585   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 586   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 587
 588   Inst.addOperand(MCOperand::CreateReg(Reg));
 589   Inst.addOperand(MCOperand::CreateReg(Base));
 590   Inst.addOperand(MCOperand::CreateImm(Offset));
 591
 592   return MCDisassembler::Success;
 593 }
 594
 595 static DecodeStatus DecodeFMem(MCInst &Inst,
 596                                unsigned Insn,
 597                                uint64_t Address,
 598                                const void *Decoder) {
 599   int Offset = SignExtend32<16>(Insn & 0xffff);
 600   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 601   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 602
 603   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
 604   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 605
 606   Inst.addOperand(MCOperand::CreateReg(Reg));
 607   Inst.addOperand(MCOperand::CreateReg(Base));
 608   Inst.addOperand(MCOperand::CreateImm(Offset));
 609
 610   return MCDisassembler::Success;
 611 }
 612
 613
 614 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 615                                               unsigned RegNo,
 616                                               uint64_t Address,
 617                                               const void *Decoder) {
 618   // Currently only hardware register 29 is supported.
 619   if (RegNo != 29)
 620     return  MCDisassembler::Fail;
 621   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
 622   return MCDisassembler::Success;
 623 }
 624
 625 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 626                                               unsigned RegNo,
 627                                               uint64_t Address,
 628                                               const void *Decoder) {
 629   if (RegNo > 30 || RegNo %2)
 630     return MCDisassembler::Fail;
 631
 632   ;
 633   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
 634   Inst.addOperand(MCOperand::CreateReg(Reg));
 635   return MCDisassembler::Success;
 636 }
 637
 638 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 639                                                 unsigned RegNo,
 640                                                 uint64_t Address,
 641                                                 const void *Decoder) {
 642   if (RegNo >= 4)
 643     return MCDisassembler::Fail;
 644
 645   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
 646   Inst.addOperand(MCOperand::CreateReg(Reg));
 647   return MCDisassembler::Success;
 648 }
 649
 650 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 651                                                unsigned RegNo,
 652                                                uint64_t Address,
 653                                                const void *Decoder) {
 654   if (RegNo >= 4)
 655     return MCDisassembler::Fail;
 656
 657   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
 658   Inst.addOperand(MCOperand::CreateReg(Reg));
 659   return MCDisassembler::Success;
 660 }
 661
 662 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 663                                                unsigned RegNo,
 664                                                uint64_t Address,
 665                                                const void *Decoder) {
 666   if (RegNo >= 4)
 667     return MCDisassembler::Fail;
 668
 669   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
 670   Inst.addOperand(MCOperand::CreateReg(Reg));
 671   return MCDisassembler::Success;
 672 }
 673
 674 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 675                                                unsigned RegNo,
 676                                                uint64_t Address,
 677                                                const void *Decoder) {
 678   if (RegNo > 31)
 679     return MCDisassembler::Fail;
 680
 681   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
 682   Inst.addOperand(MCOperand::CreateReg(Reg));
 683   return MCDisassembler::Success;
 684 }
 685
 686 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 687                                                unsigned RegNo,
 688                                                uint64_t Address,
 689                                                const void *Decoder) {
 690   if (RegNo > 31)
 691     return MCDisassembler::Fail;
 692
 693   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
 694   Inst.addOperand(MCOperand::CreateReg(Reg));
 695   return MCDisassembler::Success;
 696 }
 697
 698 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 699                                                unsigned RegNo,
 700                                                uint64_t Address,
 701                                                const void *Decoder) {
 702   if (RegNo > 31)
 703     return MCDisassembler::Fail;
 704
 705   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
 706   Inst.addOperand(MCOperand::CreateReg(Reg));
 707   return MCDisassembler::Success;
 708 }
 709
 710 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 711                                                unsigned RegNo,
 712                                                uint64_t Address,
 713                                                const void *Decoder) {
 714   if (RegNo > 31)
 715     return MCDisassembler::Fail;
 716
 717   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
 718   Inst.addOperand(MCOperand::CreateReg(Reg));
 719   return MCDisassembler::Success;
 720 }
 721
 722 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 723                                                unsigned RegNo,
 724                                                uint64_t Address,
 725                                                const void *Decoder) {
 726   if (RegNo > 7)
 727     return MCDisassembler::Fail;
 728
 729   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
 730   Inst.addOperand(MCOperand::CreateReg(Reg));
 731   return MCDisassembler::Success;
 732 }
 733
 734 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 735                                        unsigned Offset,
 736                                        uint64_t Address,
 737                                        const void *Decoder) {
 738   unsigned BranchOffset = Offset & 0xffff;
 739   BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
 740   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 741   return MCDisassembler::Success;
 742 }
 743
 744 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 745                                      unsigned Insn,
 746                                      uint64_t Address,
 747                                      const void *Decoder) {
 748
 749   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
 750   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 751   return MCDisassembler::Success;
 752 }
 753
 754 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 755                                        unsigned Insn,
 756                                        uint64_t Address,
 757                                        const void *Decoder) {
 758   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
 759   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 760   return MCDisassembler::Success;
 761 }
 762
 763 static DecodeStatus DecodeSimm16(MCInst &Inst,
 764                                  unsigned Insn,
 765                                  uint64_t Address,
 766                                  const void *Decoder) {
 767   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
 768   return MCDisassembler::Success;
 769 }
 770
 771 static DecodeStatus DecodeInsSize(MCInst &Inst,
 772                                   unsigned Insn,
 773                                   uint64_t Address,
 774                                   const void *Decoder) {
 775   // First we need to grab the pos(lsb) from MCInst.
 776   int Pos = Inst.getOperand(2).getImm();
 777   int Size = (int) Insn - Pos + 1;
 778   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 779   return MCDisassembler::Success;
 780 }
 781
 782 static DecodeStatus DecodeExtSize(MCInst &Inst,
 783                                   unsigned Insn,
 784                                   uint64_t Address,
 785                                   const void *Decoder) {
 786   int Size = (int) Insn  + 1;
 787   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 788   return MCDisassembler::Success;
 789 }