1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define DEBUG_TYPE "mips-disassembler"
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 /// A disasembler class for Mips.
34 class MipsDisassemblerBase : public MCDisassembler {
36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
38 : MCDisassembler(STI, Ctx),
39 IsN64(STI.getFeatureBits() & Mips::FeatureN64),
40 IsBigEndian(IsBigEndian) {}
42 virtual ~MipsDisassemblerBase() {}
44 bool isN64() const { return IsN64; }
52 /// A disasembler class for Mips32.
53 class MipsDisassembler : public MipsDisassemblerBase {
56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
57 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
63 bool hasMips32r6() const {
64 return STI.getFeatureBits() & Mips::FeatureMips32r6;
67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
77 raw_ostream &CStream) const override;
80 /// A disasembler class for Mips64.
81 class Mips64Disassembler : public MipsDisassemblerBase {
83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
85 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
88 ArrayRef<uint8_t> Bytes, uint64_t Address,
90 raw_ostream &CStream) const override;
93 } // end anonymous namespace
95 // Forward declare these because the autogenerated code will reference them.
96 // Definitions are further down.
97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
100 const void *Decoder);
102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
105 const void *Decoder);
107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
110 const void *Decoder);
112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
115 const void *Decoder);
117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
120 const void *Decoder);
122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
125 const void *Decoder);
127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
130 const void *Decoder);
132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
135 const void *Decoder);
137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
140 const void *Decoder);
142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
145 const void *Decoder);
147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
150 const void *Decoder);
152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
154 const void *Decoder);
156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
159 const void *Decoder);
161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
164 const void *Decoder);
166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
169 const void *Decoder);
171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
174 const void *Decoder);
176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
179 const void *Decoder);
181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
184 const void *Decoder);
186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
189 const void *Decoder);
191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
194 const void *Decoder);
196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
199 const void *Decoder);
201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
204 const void *Decoder);
206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
209 const void *Decoder);
211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
214 const void *Decoder);
216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
219 const void *Decoder);
221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
224 const void *Decoder);
226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
229 const void *Decoder);
231 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
232 // shifted left by 1 bit.
233 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
236 const void *Decoder);
238 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
239 // shifted left by 1 bit.
240 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
243 const void *Decoder);
245 static DecodeStatus DecodeMem(MCInst &Inst,
248 const void *Decoder);
250 static DecodeStatus DecodeCacheOp(MCInst &Inst,
253 const void *Decoder);
255 static DecodeStatus DecodeSyncI(MCInst &Inst,
258 const void *Decoder);
260 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
261 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
266 const void *Decoder);
268 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
271 const void *Decoder);
273 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
276 const void *Decoder);
278 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
280 const void *Decoder);
282 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
284 const void *Decoder);
286 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
288 const void *Decoder);
290 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
293 const void *Decoder);
295 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
298 const void *Decoder);
300 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
303 const void *Decoder);
305 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
308 const void *Decoder);
310 static DecodeStatus DecodeSimm4(MCInst &Inst,
313 const void *Decoder);
315 static DecodeStatus DecodeSimm16(MCInst &Inst,
318 const void *Decoder);
320 // Decode the immediate field of an LSA instruction which
322 static DecodeStatus DecodeLSAImm(MCInst &Inst,
325 const void *Decoder);
327 static DecodeStatus DecodeInsSize(MCInst &Inst,
330 const void *Decoder);
332 static DecodeStatus DecodeExtSize(MCInst &Inst,
335 const void *Decoder);
337 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
338 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
341 uint64_t Address, const void *Decoder);
343 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
345 template <typename InsnType>
346 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
347 const void *Decoder);
349 template <typename InsnType>
351 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
352 const void *Decoder);
354 template <typename InsnType>
356 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
357 const void *Decoder);
359 template <typename InsnType>
361 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
362 const void *Decoder);
364 template <typename InsnType>
366 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
367 const void *Decoder);
369 template <typename InsnType>
371 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
372 const void *Decoder);
374 template <typename InsnType>
376 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
377 const void *Decoder);
379 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
381 const void *Decoder);
383 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
385 const void *Decoder);
388 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
392 static MCDisassembler *createMipsDisassembler(
394 const MCSubtargetInfo &STI,
396 return new MipsDisassembler(STI, Ctx, true);
399 static MCDisassembler *createMipselDisassembler(
401 const MCSubtargetInfo &STI,
403 return new MipsDisassembler(STI, Ctx, false);
406 static MCDisassembler *createMips64Disassembler(
408 const MCSubtargetInfo &STI,
410 return new Mips64Disassembler(STI, Ctx, true);
413 static MCDisassembler *createMips64elDisassembler(
415 const MCSubtargetInfo &STI,
417 return new Mips64Disassembler(STI, Ctx, false);
420 extern "C" void LLVMInitializeMipsDisassembler() {
421 // Register the disassembler.
422 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
423 createMipsDisassembler);
424 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
425 createMipselDisassembler);
426 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
427 createMips64Disassembler);
428 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
429 createMips64elDisassembler);
432 #include "MipsGenDisassemblerTables.inc"
434 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
435 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
436 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
437 return *(RegInfo->getRegClass(RC).begin() + RegNo);
440 template <typename InsnType>
441 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
442 const void *Decoder) {
443 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
444 // The size of the n field depends on the element size
445 // The register class also depends on this.
446 InsnType tmp = fieldFromInstruction(insn, 17, 5);
448 DecodeFN RegDecoder = nullptr;
449 if ((tmp & 0x18) == 0x00) { // INSVE_B
451 RegDecoder = DecodeMSA128BRegisterClass;
452 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
454 RegDecoder = DecodeMSA128HRegisterClass;
455 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
457 RegDecoder = DecodeMSA128WRegisterClass;
458 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
460 RegDecoder = DecodeMSA128DRegisterClass;
462 llvm_unreachable("Invalid encoding");
464 assert(NSize != 0 && RegDecoder != nullptr);
467 tmp = fieldFromInstruction(insn, 6, 5);
468 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
469 return MCDisassembler::Fail;
471 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
472 return MCDisassembler::Fail;
474 tmp = fieldFromInstruction(insn, 16, NSize);
475 MI.addOperand(MCOperand::CreateImm(tmp));
477 tmp = fieldFromInstruction(insn, 11, 5);
478 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
479 return MCDisassembler::Fail;
481 MI.addOperand(MCOperand::CreateImm(0));
483 return MCDisassembler::Success;
486 template <typename InsnType>
487 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
489 const void *Decoder) {
490 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
491 // (otherwise we would have matched the ADDI instruction from the earlier
495 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
497 // BEQZALC if rs == 0 && rt != 0
498 // BEQC if rs < rt && rs != 0
500 InsnType Rs = fieldFromInstruction(insn, 21, 5);
501 InsnType Rt = fieldFromInstruction(insn, 16, 5);
502 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
506 MI.setOpcode(Mips::BOVC);
508 } else if (Rs != 0 && Rs < Rt) {
509 MI.setOpcode(Mips::BEQC);
512 MI.setOpcode(Mips::BEQZALC);
515 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
518 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
520 MI.addOperand(MCOperand::CreateImm(Imm));
522 return MCDisassembler::Success;
525 template <typename InsnType>
526 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
528 const void *Decoder) {
529 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
530 // (otherwise we would have matched the ADDI instruction from the earlier
534 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
536 // BNEZALC if rs == 0 && rt != 0
537 // BNEC if rs < rt && rs != 0
539 InsnType Rs = fieldFromInstruction(insn, 21, 5);
540 InsnType Rt = fieldFromInstruction(insn, 16, 5);
541 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
545 MI.setOpcode(Mips::BNVC);
547 } else if (Rs != 0 && Rs < Rt) {
548 MI.setOpcode(Mips::BNEC);
551 MI.setOpcode(Mips::BNEZALC);
554 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
557 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
559 MI.addOperand(MCOperand::CreateImm(Imm));
561 return MCDisassembler::Success;
564 template <typename InsnType>
565 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
567 const void *Decoder) {
568 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
569 // (otherwise we would have matched the BLEZL instruction from the earlier
573 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
574 // Invalid if rs == 0
575 // BLEZC if rs == 0 && rt != 0
576 // BGEZC if rs == rt && rt != 0
577 // BGEC if rs != rt && rs != 0 && rt != 0
579 InsnType Rs = fieldFromInstruction(insn, 21, 5);
580 InsnType Rt = fieldFromInstruction(insn, 16, 5);
581 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
585 return MCDisassembler::Fail;
587 MI.setOpcode(Mips::BLEZC);
589 MI.setOpcode(Mips::BGEZC);
592 MI.setOpcode(Mips::BGEC);
596 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
599 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
602 MI.addOperand(MCOperand::CreateImm(Imm));
604 return MCDisassembler::Success;
607 template <typename InsnType>
608 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
610 const void *Decoder) {
611 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
612 // (otherwise we would have matched the BGTZL instruction from the earlier
616 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
617 // Invalid if rs == 0
618 // BGTZC if rs == 0 && rt != 0
619 // BLTZC if rs == rt && rt != 0
620 // BLTC if rs != rt && rs != 0 && rt != 0
624 InsnType Rs = fieldFromInstruction(insn, 21, 5);
625 InsnType Rt = fieldFromInstruction(insn, 16, 5);
626 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
629 return MCDisassembler::Fail;
631 MI.setOpcode(Mips::BGTZC);
633 MI.setOpcode(Mips::BLTZC);
635 MI.setOpcode(Mips::BLTC);
640 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
643 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
646 MI.addOperand(MCOperand::CreateImm(Imm));
648 return MCDisassembler::Success;
651 template <typename InsnType>
652 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
654 const void *Decoder) {
655 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
656 // (otherwise we would have matched the BGTZ instruction from the earlier
660 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
662 // BGTZALC if rs == 0 && rt != 0
663 // BLTZALC if rs != 0 && rs == rt
664 // BLTUC if rs != 0 && rs != rt
666 InsnType Rs = fieldFromInstruction(insn, 21, 5);
667 InsnType Rt = fieldFromInstruction(insn, 16, 5);
668 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
673 MI.setOpcode(Mips::BGTZ);
675 } else if (Rs == 0) {
676 MI.setOpcode(Mips::BGTZALC);
678 } else if (Rs == Rt) {
679 MI.setOpcode(Mips::BLTZALC);
682 MI.setOpcode(Mips::BLTUC);
688 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
692 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
695 MI.addOperand(MCOperand::CreateImm(Imm));
697 return MCDisassembler::Success;
700 template <typename InsnType>
701 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
703 const void *Decoder) {
704 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
705 // (otherwise we would have matched the BLEZL instruction from the earlier
709 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
710 // Invalid if rs == 0
711 // BLEZALC if rs == 0 && rt != 0
712 // BGEZALC if rs == rt && rt != 0
713 // BGEUC if rs != rt && rs != 0 && rt != 0
715 InsnType Rs = fieldFromInstruction(insn, 21, 5);
716 InsnType Rt = fieldFromInstruction(insn, 16, 5);
717 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
721 return MCDisassembler::Fail;
723 MI.setOpcode(Mips::BLEZALC);
725 MI.setOpcode(Mips::BGEZALC);
728 MI.setOpcode(Mips::BGEUC);
732 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
734 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
737 MI.addOperand(MCOperand::CreateImm(Imm));
739 return MCDisassembler::Success;
742 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
743 /// according to the given endianess.
744 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
745 uint64_t &Size, uint32_t &Insn,
747 // We want to read exactly 2 Bytes of data.
748 if (Bytes.size() < 2) {
750 return MCDisassembler::Fail;
754 Insn = (Bytes[0] << 8) | Bytes[1];
756 Insn = (Bytes[1] << 8) | Bytes[0];
759 return MCDisassembler::Success;
762 /// Read four bytes from the ArrayRef and return 32 bit word sorted
763 /// according to the given endianess
764 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
765 uint64_t &Size, uint32_t &Insn,
766 bool IsBigEndian, bool IsMicroMips) {
767 // We want to read exactly 4 Bytes of data.
768 if (Bytes.size() < 4) {
770 return MCDisassembler::Fail;
773 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
774 // always precede the low 16 bits in the instruction stream (that is, they
775 // are placed at lower addresses in the instruction stream).
777 // microMIPS byte ordering:
778 // Big-endian: 0 | 1 | 2 | 3
779 // Little-endian: 1 | 0 | 3 | 2
782 // Encoded as a big-endian 32-bit word in the stream.
784 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
787 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
790 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
795 return MCDisassembler::Success;
798 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
799 ArrayRef<uint8_t> Bytes,
801 raw_ostream &VStream,
802 raw_ostream &CStream) const {
807 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
809 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
810 // Calling the auto-generated decoder function.
811 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
813 if (Result != MCDisassembler::Fail) {
818 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
819 if (Result == MCDisassembler::Fail)
820 return MCDisassembler::Fail;
822 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
823 // Calling the auto-generated decoder function.
824 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
826 if (Result != MCDisassembler::Fail) {
830 return MCDisassembler::Fail;
833 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
834 if (Result == MCDisassembler::Fail)
835 return MCDisassembler::Fail;
838 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
840 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
841 if (Result != MCDisassembler::Fail) {
847 if (hasMips32r6() && isGP64()) {
848 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
849 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
851 if (Result != MCDisassembler::Fail) {
858 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
859 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
861 if (Result != MCDisassembler::Fail) {
867 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
868 // Calling the auto-generated decoder function.
870 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
871 if (Result != MCDisassembler::Fail) {
876 return MCDisassembler::Fail;
879 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
880 ArrayRef<uint8_t> Bytes,
882 raw_ostream &VStream,
883 raw_ostream &CStream) const {
886 DecodeStatus Result =
887 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
888 if (Result == MCDisassembler::Fail)
889 return MCDisassembler::Fail;
891 // Calling the auto-generated decoder function.
893 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
894 if (Result != MCDisassembler::Fail) {
898 // If we fail to decode in Mips64 decoder space we can try in Mips32
900 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
901 if (Result != MCDisassembler::Fail) {
906 return MCDisassembler::Fail;
909 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
912 const void *Decoder) {
914 return MCDisassembler::Fail;
918 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
921 const void *Decoder) {
924 return MCDisassembler::Fail;
926 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
927 Inst.addOperand(MCOperand::CreateReg(Reg));
928 return MCDisassembler::Success;
931 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
934 const void *Decoder) {
936 return MCDisassembler::Fail;
937 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
938 Inst.addOperand(MCOperand::CreateReg(Reg));
939 return MCDisassembler::Success;
942 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
945 const void *Decoder) {
947 return MCDisassembler::Fail;
948 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
949 Inst.addOperand(MCOperand::CreateReg(Reg));
950 return MCDisassembler::Success;
953 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
956 const void *Decoder) {
958 return MCDisassembler::Fail;
959 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
960 Inst.addOperand(MCOperand::CreateReg(Reg));
961 return MCDisassembler::Success;
964 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
967 const void *Decoder) {
968 if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
969 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
971 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
974 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
977 const void *Decoder) {
978 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
981 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
984 const void *Decoder) {
986 return MCDisassembler::Fail;
988 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
989 Inst.addOperand(MCOperand::CreateReg(Reg));
990 return MCDisassembler::Success;
993 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
996 const void *Decoder) {
998 return MCDisassembler::Fail;
1000 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1001 Inst.addOperand(MCOperand::CreateReg(Reg));
1002 return MCDisassembler::Success;
1005 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1008 const void *Decoder) {
1010 return MCDisassembler::Fail;
1011 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1012 Inst.addOperand(MCOperand::CreateReg(Reg));
1013 return MCDisassembler::Success;
1016 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1019 const void *Decoder) {
1021 return MCDisassembler::Fail;
1022 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1023 Inst.addOperand(MCOperand::CreateReg(Reg));
1024 return MCDisassembler::Success;
1027 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1029 const void *Decoder) {
1031 return MCDisassembler::Fail;
1033 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1034 Inst.addOperand(MCOperand::CreateReg(Reg));
1035 return MCDisassembler::Success;
1038 static DecodeStatus DecodeMem(MCInst &Inst,
1041 const void *Decoder) {
1042 int Offset = SignExtend32<16>(Insn & 0xffff);
1043 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1044 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1046 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1047 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1049 if(Inst.getOpcode() == Mips::SC){
1050 Inst.addOperand(MCOperand::CreateReg(Reg));
1053 Inst.addOperand(MCOperand::CreateReg(Reg));
1054 Inst.addOperand(MCOperand::CreateReg(Base));
1055 Inst.addOperand(MCOperand::CreateImm(Offset));
1057 return MCDisassembler::Success;
1060 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1063 const void *Decoder) {
1064 int Offset = SignExtend32<16>(Insn & 0xffff);
1065 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1066 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1068 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1070 Inst.addOperand(MCOperand::CreateReg(Base));
1071 Inst.addOperand(MCOperand::CreateImm(Offset));
1072 Inst.addOperand(MCOperand::CreateImm(Hint));
1074 return MCDisassembler::Success;
1077 static DecodeStatus DecodeSyncI(MCInst &Inst,
1080 const void *Decoder) {
1081 int Offset = SignExtend32<16>(Insn & 0xffff);
1082 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1084 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1086 Inst.addOperand(MCOperand::CreateReg(Base));
1087 Inst.addOperand(MCOperand::CreateImm(Offset));
1089 return MCDisassembler::Success;
1092 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1093 uint64_t Address, const void *Decoder) {
1094 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1095 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1096 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1098 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1099 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1101 Inst.addOperand(MCOperand::CreateReg(Reg));
1102 Inst.addOperand(MCOperand::CreateReg(Base));
1104 // The immediate field of an LD/ST instruction is scaled which means it must
1105 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1111 switch(Inst.getOpcode())
1114 assert (0 && "Unexpected instruction");
1115 return MCDisassembler::Fail;
1119 Inst.addOperand(MCOperand::CreateImm(Offset));
1123 Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1127 Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1131 Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1135 return MCDisassembler::Success;
1138 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1141 const void *Decoder) {
1142 unsigned Offset = Insn & 0xf;
1143 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1144 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1146 switch (Inst.getOpcode()) {
1147 case Mips::LBU16_MM:
1148 case Mips::LHU16_MM:
1150 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1151 == MCDisassembler::Fail)
1152 return MCDisassembler::Fail;
1157 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1158 == MCDisassembler::Fail)
1159 return MCDisassembler::Fail;
1163 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1164 == MCDisassembler::Fail)
1165 return MCDisassembler::Fail;
1167 switch (Inst.getOpcode()) {
1168 case Mips::LBU16_MM:
1170 Inst.addOperand(MCOperand::CreateImm(-1));
1172 Inst.addOperand(MCOperand::CreateImm(Offset));
1175 Inst.addOperand(MCOperand::CreateImm(Offset));
1177 case Mips::LHU16_MM:
1179 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1183 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1187 return MCDisassembler::Success;
1190 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1193 const void *Decoder) {
1194 int Offset = SignExtend32<12>(Insn & 0x0fff);
1195 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1196 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1198 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1199 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1201 switch (Inst.getOpcode()) {
1202 case Mips::SWM32_MM:
1203 case Mips::LWM32_MM:
1204 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1205 == MCDisassembler::Fail)
1206 return MCDisassembler::Fail;
1207 Inst.addOperand(MCOperand::CreateReg(Base));
1208 Inst.addOperand(MCOperand::CreateImm(Offset));
1211 Inst.addOperand(MCOperand::CreateReg(Reg));
1214 Inst.addOperand(MCOperand::CreateReg(Reg));
1215 Inst.addOperand(MCOperand::CreateReg(Base));
1216 Inst.addOperand(MCOperand::CreateImm(Offset));
1219 return MCDisassembler::Success;
1222 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1225 const void *Decoder) {
1226 int Offset = SignExtend32<16>(Insn & 0xffff);
1227 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1228 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1230 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1231 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1233 Inst.addOperand(MCOperand::CreateReg(Reg));
1234 Inst.addOperand(MCOperand::CreateReg(Base));
1235 Inst.addOperand(MCOperand::CreateImm(Offset));
1237 return MCDisassembler::Success;
1240 static DecodeStatus DecodeFMem(MCInst &Inst,
1243 const void *Decoder) {
1244 int Offset = SignExtend32<16>(Insn & 0xffff);
1245 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1246 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1248 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1249 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1251 Inst.addOperand(MCOperand::CreateReg(Reg));
1252 Inst.addOperand(MCOperand::CreateReg(Base));
1253 Inst.addOperand(MCOperand::CreateImm(Offset));
1255 return MCDisassembler::Success;
1258 static DecodeStatus DecodeFMem2(MCInst &Inst,
1261 const void *Decoder) {
1262 int Offset = SignExtend32<16>(Insn & 0xffff);
1263 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1264 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1266 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1267 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1269 Inst.addOperand(MCOperand::CreateReg(Reg));
1270 Inst.addOperand(MCOperand::CreateReg(Base));
1271 Inst.addOperand(MCOperand::CreateImm(Offset));
1273 return MCDisassembler::Success;
1276 static DecodeStatus DecodeFMem3(MCInst &Inst,
1279 const void *Decoder) {
1280 int Offset = SignExtend32<16>(Insn & 0xffff);
1281 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1282 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1284 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1285 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1287 Inst.addOperand(MCOperand::CreateReg(Reg));
1288 Inst.addOperand(MCOperand::CreateReg(Base));
1289 Inst.addOperand(MCOperand::CreateImm(Offset));
1291 return MCDisassembler::Success;
1294 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1297 const void *Decoder) {
1298 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1299 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1300 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1302 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1303 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1305 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1306 Inst.addOperand(MCOperand::CreateReg(Rt));
1309 Inst.addOperand(MCOperand::CreateReg(Rt));
1310 Inst.addOperand(MCOperand::CreateReg(Base));
1311 Inst.addOperand(MCOperand::CreateImm(Offset));
1313 return MCDisassembler::Success;
1316 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1319 const void *Decoder) {
1320 // Currently only hardware register 29 is supported.
1322 return MCDisassembler::Fail;
1323 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1324 return MCDisassembler::Success;
1327 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1330 const void *Decoder) {
1331 if (RegNo > 30 || RegNo %2)
1332 return MCDisassembler::Fail;
1335 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1336 Inst.addOperand(MCOperand::CreateReg(Reg));
1337 return MCDisassembler::Success;
1340 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1343 const void *Decoder) {
1345 return MCDisassembler::Fail;
1347 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1348 Inst.addOperand(MCOperand::CreateReg(Reg));
1349 return MCDisassembler::Success;
1352 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1355 const void *Decoder) {
1357 return MCDisassembler::Fail;
1359 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1360 Inst.addOperand(MCOperand::CreateReg(Reg));
1361 return MCDisassembler::Success;
1364 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1367 const void *Decoder) {
1369 return MCDisassembler::Fail;
1371 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1372 Inst.addOperand(MCOperand::CreateReg(Reg));
1373 return MCDisassembler::Success;
1376 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1379 const void *Decoder) {
1381 return MCDisassembler::Fail;
1383 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1384 Inst.addOperand(MCOperand::CreateReg(Reg));
1385 return MCDisassembler::Success;
1388 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1391 const void *Decoder) {
1393 return MCDisassembler::Fail;
1395 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1396 Inst.addOperand(MCOperand::CreateReg(Reg));
1397 return MCDisassembler::Success;
1400 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1403 const void *Decoder) {
1405 return MCDisassembler::Fail;
1407 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1408 Inst.addOperand(MCOperand::CreateReg(Reg));
1409 return MCDisassembler::Success;
1412 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1415 const void *Decoder) {
1417 return MCDisassembler::Fail;
1419 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1420 Inst.addOperand(MCOperand::CreateReg(Reg));
1421 return MCDisassembler::Success;
1424 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1427 const void *Decoder) {
1429 return MCDisassembler::Fail;
1431 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1432 Inst.addOperand(MCOperand::CreateReg(Reg));
1433 return MCDisassembler::Success;
1436 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1439 const void *Decoder) {
1441 return MCDisassembler::Fail;
1443 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1444 Inst.addOperand(MCOperand::CreateReg(Reg));
1445 return MCDisassembler::Success;
1448 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1451 const void *Decoder) {
1452 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1453 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1454 return MCDisassembler::Success;
1457 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1460 const void *Decoder) {
1462 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1463 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1464 return MCDisassembler::Success;
1467 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1470 const void *Decoder) {
1471 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1473 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1474 return MCDisassembler::Success;
1477 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1480 const void *Decoder) {
1481 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1483 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1484 return MCDisassembler::Success;
1487 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1490 const void *Decoder) {
1491 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1492 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1493 return MCDisassembler::Success;
1496 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1499 const void *Decoder) {
1500 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1501 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1502 return MCDisassembler::Success;
1505 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1508 const void *Decoder) {
1510 Inst.addOperand(MCOperand::CreateImm(1));
1511 else if (Value == 0x7)
1512 Inst.addOperand(MCOperand::CreateImm(-1));
1514 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1515 return MCDisassembler::Success;
1518 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1521 const void *Decoder) {
1522 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1523 return MCDisassembler::Success;
1526 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1529 const void *Decoder) {
1531 Inst.addOperand(MCOperand::CreateImm(-1));
1533 Inst.addOperand(MCOperand::CreateImm(Value));
1534 return MCDisassembler::Success;
1537 static DecodeStatus DecodeSimm4(MCInst &Inst,
1540 const void *Decoder) {
1541 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1542 return MCDisassembler::Success;
1545 static DecodeStatus DecodeSimm16(MCInst &Inst,
1548 const void *Decoder) {
1549 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1550 return MCDisassembler::Success;
1553 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1556 const void *Decoder) {
1557 // We add one to the immediate field as it was encoded as 'imm - 1'.
1558 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1559 return MCDisassembler::Success;
1562 static DecodeStatus DecodeInsSize(MCInst &Inst,
1565 const void *Decoder) {
1566 // First we need to grab the pos(lsb) from MCInst.
1567 int Pos = Inst.getOperand(2).getImm();
1568 int Size = (int) Insn - Pos + 1;
1569 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1570 return MCDisassembler::Success;
1573 static DecodeStatus DecodeExtSize(MCInst &Inst,
1576 const void *Decoder) {
1577 int Size = (int) Insn + 1;
1578 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1579 return MCDisassembler::Success;
1582 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1583 uint64_t Address, const void *Decoder) {
1584 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1585 return MCDisassembler::Success;
1588 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1589 uint64_t Address, const void *Decoder) {
1590 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1591 return MCDisassembler::Success;
1594 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1597 const void *Decoder) {
1598 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1599 Mips::S6, Mips::FP};
1602 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1603 // Empty register lists are not allowed.
1605 return MCDisassembler::Fail;
1607 RegNum = RegLst & 0xf;
1608 for (unsigned i = 0; i < RegNum; i++)
1609 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1612 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1614 return MCDisassembler::Success;
1617 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1619 const void *Decoder) {
1620 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1623 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1624 // Empty register lists are not allowed.
1626 return MCDisassembler::Fail;
1628 RegNum = RegLst & 0x3;
1629 for (unsigned i = 0; i < RegNum - 1; i++)
1630 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1632 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1634 return MCDisassembler::Success;