1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define DEBUG_TYPE "mips-disassembler"
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 class MipsDisassembler : public MCDisassembler {
37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
38 : MCDisassembler(STI, Ctx),
39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
40 IsBigEndian(IsBigEndian) {}
42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
44 bool hasMips32r6() const {
45 return STI.getFeatureBits()[Mips::FeatureMips32r6];
48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
52 bool hasCOP3() const {
53 // Only present in MIPS-I and MIPS-II
54 return !hasMips32() && !hasMips3();
57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
58 ArrayRef<uint8_t> Bytes, uint64_t Address,
60 raw_ostream &CStream) const override;
63 } // end anonymous namespace
65 // Forward declare these because the autogenerated code will reference them.
66 // Definitions are further down.
67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
100 const void *Decoder);
102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
105 const void *Decoder);
107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
110 const void *Decoder);
112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
115 const void *Decoder);
117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
120 const void *Decoder);
122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
125 const void *Decoder);
127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
129 const void *Decoder);
131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
134 const void *Decoder);
136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
139 const void *Decoder);
141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
144 const void *Decoder);
146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
149 const void *Decoder);
151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
154 const void *Decoder);
156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
159 const void *Decoder);
161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
164 const void *Decoder);
166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
169 const void *Decoder);
171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
174 const void *Decoder);
176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
179 const void *Decoder);
181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
184 const void *Decoder);
186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
189 const void *Decoder);
191 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
194 const void *Decoder);
196 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
199 const void *Decoder);
201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
204 const void *Decoder);
206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
209 const void *Decoder);
211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
212 // shifted left by 1 bit.
213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
216 const void *Decoder);
218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
219 // shifted left by 1 bit.
220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
223 const void *Decoder);
225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
226 // shifted left by 1 bit.
227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
230 const void *Decoder);
232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
233 // shifted left by 1 bit.
234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
237 const void *Decoder);
239 static DecodeStatus DecodeMem(MCInst &Inst,
242 const void *Decoder);
244 static DecodeStatus DecodeMemEVA(MCInst &Inst,
247 const void *Decoder);
249 static DecodeStatus DecodeCacheOp(MCInst &Inst,
252 const void *Decoder);
254 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
257 const void *Decoder);
259 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
262 const void *Decoder);
264 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
267 const void *Decoder);
269 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
272 const void *Decoder);
274 static DecodeStatus DecodeSyncI(MCInst &Inst,
277 const void *Decoder);
279 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
285 const void *Decoder);
287 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
290 const void *Decoder);
292 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
295 const void *Decoder);
297 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
300 const void *Decoder);
302 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
305 const void *Decoder);
307 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
310 const void *Decoder);
312 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
315 const void *Decoder);
317 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
319 const void *Decoder);
321 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
323 const void *Decoder);
325 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
327 const void *Decoder);
329 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
331 const void *Decoder);
333 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
336 const void *Decoder);
338 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
341 const void *Decoder);
343 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
346 const void *Decoder);
348 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
351 const void *Decoder);
353 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
356 const void *Decoder);
358 static DecodeStatus DecodeSimm4(MCInst &Inst,
361 const void *Decoder);
363 static DecodeStatus DecodeSimm16(MCInst &Inst,
366 const void *Decoder);
368 // Decode the immediate field of an LSA instruction which
370 static DecodeStatus DecodeLSAImm(MCInst &Inst,
373 const void *Decoder);
375 static DecodeStatus DecodeInsSize(MCInst &Inst,
378 const void *Decoder);
380 static DecodeStatus DecodeExtSize(MCInst &Inst,
383 const void *Decoder);
385 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
386 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
389 uint64_t Address, const void *Decoder);
391 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
392 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
395 uint64_t Address, const void *Decoder);
397 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
398 uint64_t Address, const void *Decoder);
400 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
401 uint64_t Address, const void *Decoder);
403 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
405 template <typename InsnType>
406 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
407 const void *Decoder);
409 template <typename InsnType>
411 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
412 const void *Decoder);
414 template <typename InsnType>
416 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
417 const void *Decoder);
419 template <typename InsnType>
421 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
422 const void *Decoder);
424 template <typename InsnType>
426 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
427 const void *Decoder);
429 template <typename InsnType>
431 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
432 const void *Decoder);
434 template <typename InsnType>
436 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
437 const void *Decoder);
439 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
441 const void *Decoder);
443 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
445 const void *Decoder);
447 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
449 const void *Decoder);
452 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
456 static MCDisassembler *createMipsDisassembler(
458 const MCSubtargetInfo &STI,
460 return new MipsDisassembler(STI, Ctx, true);
463 static MCDisassembler *createMipselDisassembler(
465 const MCSubtargetInfo &STI,
467 return new MipsDisassembler(STI, Ctx, false);
470 extern "C" void LLVMInitializeMipsDisassembler() {
471 // Register the disassembler.
472 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
473 createMipsDisassembler);
474 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
475 createMipselDisassembler);
476 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
477 createMipsDisassembler);
478 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
479 createMipselDisassembler);
482 #include "MipsGenDisassemblerTables.inc"
484 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
485 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
486 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
487 return *(RegInfo->getRegClass(RC).begin() + RegNo);
490 template <typename InsnType>
491 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
492 const void *Decoder) {
493 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
494 // The size of the n field depends on the element size
495 // The register class also depends on this.
496 InsnType tmp = fieldFromInstruction(insn, 17, 5);
498 DecodeFN RegDecoder = nullptr;
499 if ((tmp & 0x18) == 0x00) { // INSVE_B
501 RegDecoder = DecodeMSA128BRegisterClass;
502 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
504 RegDecoder = DecodeMSA128HRegisterClass;
505 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
507 RegDecoder = DecodeMSA128WRegisterClass;
508 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
510 RegDecoder = DecodeMSA128DRegisterClass;
512 llvm_unreachable("Invalid encoding");
514 assert(NSize != 0 && RegDecoder != nullptr);
517 tmp = fieldFromInstruction(insn, 6, 5);
518 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
519 return MCDisassembler::Fail;
521 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
522 return MCDisassembler::Fail;
524 tmp = fieldFromInstruction(insn, 16, NSize);
525 MI.addOperand(MCOperand::createImm(tmp));
527 tmp = fieldFromInstruction(insn, 11, 5);
528 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
529 return MCDisassembler::Fail;
531 MI.addOperand(MCOperand::createImm(0));
533 return MCDisassembler::Success;
536 template <typename InsnType>
537 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
539 const void *Decoder) {
540 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
541 // (otherwise we would have matched the ADDI instruction from the earlier
545 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
547 // BEQZALC if rs == 0 && rt != 0
548 // BEQC if rs < rt && rs != 0
550 InsnType Rs = fieldFromInstruction(insn, 21, 5);
551 InsnType Rt = fieldFromInstruction(insn, 16, 5);
552 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
556 MI.setOpcode(Mips::BOVC);
558 } else if (Rs != 0 && Rs < Rt) {
559 MI.setOpcode(Mips::BEQC);
562 MI.setOpcode(Mips::BEQZALC);
565 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
568 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
570 MI.addOperand(MCOperand::createImm(Imm));
572 return MCDisassembler::Success;
575 template <typename InsnType>
576 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
578 const void *Decoder) {
579 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
580 // (otherwise we would have matched the ADDI instruction from the earlier
584 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
586 // BNEZALC if rs == 0 && rt != 0
587 // BNEC if rs < rt && rs != 0
589 InsnType Rs = fieldFromInstruction(insn, 21, 5);
590 InsnType Rt = fieldFromInstruction(insn, 16, 5);
591 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
595 MI.setOpcode(Mips::BNVC);
597 } else if (Rs != 0 && Rs < Rt) {
598 MI.setOpcode(Mips::BNEC);
601 MI.setOpcode(Mips::BNEZALC);
604 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
607 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
609 MI.addOperand(MCOperand::createImm(Imm));
611 return MCDisassembler::Success;
614 template <typename InsnType>
615 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
617 const void *Decoder) {
618 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
619 // (otherwise we would have matched the BLEZL instruction from the earlier
623 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
624 // Invalid if rs == 0
625 // BLEZC if rs == 0 && rt != 0
626 // BGEZC if rs == rt && rt != 0
627 // BGEC if rs != rt && rs != 0 && rt != 0
629 InsnType Rs = fieldFromInstruction(insn, 21, 5);
630 InsnType Rt = fieldFromInstruction(insn, 16, 5);
631 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
635 return MCDisassembler::Fail;
637 MI.setOpcode(Mips::BLEZC);
639 MI.setOpcode(Mips::BGEZC);
642 MI.setOpcode(Mips::BGEC);
646 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
652 MI.addOperand(MCOperand::createImm(Imm));
654 return MCDisassembler::Success;
657 template <typename InsnType>
658 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
660 const void *Decoder) {
661 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
662 // (otherwise we would have matched the BGTZL instruction from the earlier
666 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
667 // Invalid if rs == 0
668 // BGTZC if rs == 0 && rt != 0
669 // BLTZC if rs == rt && rt != 0
670 // BLTC if rs != rt && rs != 0 && rt != 0
674 InsnType Rs = fieldFromInstruction(insn, 21, 5);
675 InsnType Rt = fieldFromInstruction(insn, 16, 5);
676 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
679 return MCDisassembler::Fail;
681 MI.setOpcode(Mips::BGTZC);
683 MI.setOpcode(Mips::BLTZC);
685 MI.setOpcode(Mips::BLTC);
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
696 MI.addOperand(MCOperand::createImm(Imm));
698 return MCDisassembler::Success;
701 template <typename InsnType>
702 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
704 const void *Decoder) {
705 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
706 // (otherwise we would have matched the BGTZ instruction from the earlier
710 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
712 // BGTZALC if rs == 0 && rt != 0
713 // BLTZALC if rs != 0 && rs == rt
714 // BLTUC if rs != 0 && rs != rt
716 InsnType Rs = fieldFromInstruction(insn, 21, 5);
717 InsnType Rt = fieldFromInstruction(insn, 16, 5);
718 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
723 MI.setOpcode(Mips::BGTZ);
725 } else if (Rs == 0) {
726 MI.setOpcode(Mips::BGTZALC);
728 } else if (Rs == Rt) {
729 MI.setOpcode(Mips::BLTZALC);
732 MI.setOpcode(Mips::BLTUC);
738 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
742 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
745 MI.addOperand(MCOperand::createImm(Imm));
747 return MCDisassembler::Success;
750 template <typename InsnType>
751 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
753 const void *Decoder) {
754 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
755 // (otherwise we would have matched the BLEZL instruction from the earlier
759 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
760 // Invalid if rs == 0
761 // BLEZALC if rs == 0 && rt != 0
762 // BGEZALC if rs == rt && rt != 0
763 // BGEUC if rs != rt && rs != 0 && rt != 0
765 InsnType Rs = fieldFromInstruction(insn, 21, 5);
766 InsnType Rt = fieldFromInstruction(insn, 16, 5);
767 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
771 return MCDisassembler::Fail;
773 MI.setOpcode(Mips::BLEZALC);
775 MI.setOpcode(Mips::BGEZALC);
778 MI.setOpcode(Mips::BGEUC);
782 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
787 MI.addOperand(MCOperand::createImm(Imm));
789 return MCDisassembler::Success;
792 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
793 /// according to the given endianess.
794 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
795 uint64_t &Size, uint32_t &Insn,
797 // We want to read exactly 2 Bytes of data.
798 if (Bytes.size() < 2) {
800 return MCDisassembler::Fail;
804 Insn = (Bytes[0] << 8) | Bytes[1];
806 Insn = (Bytes[1] << 8) | Bytes[0];
809 return MCDisassembler::Success;
812 /// Read four bytes from the ArrayRef and return 32 bit word sorted
813 /// according to the given endianess
814 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
815 uint64_t &Size, uint32_t &Insn,
816 bool IsBigEndian, bool IsMicroMips) {
817 // We want to read exactly 4 Bytes of data.
818 if (Bytes.size() < 4) {
820 return MCDisassembler::Fail;
823 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
824 // always precede the low 16 bits in the instruction stream (that is, they
825 // are placed at lower addresses in the instruction stream).
827 // microMIPS byte ordering:
828 // Big-endian: 0 | 1 | 2 | 3
829 // Little-endian: 1 | 0 | 3 | 2
832 // Encoded as a big-endian 32-bit word in the stream.
834 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
837 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
840 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
845 return MCDisassembler::Success;
848 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
849 ArrayRef<uint8_t> Bytes,
851 raw_ostream &VStream,
852 raw_ostream &CStream) const {
857 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
860 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
861 // Calling the auto-generated decoder function for microMIPS32R6
862 // (and microMIPS64R6) 16-bit instructions.
863 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
865 if (Result != MCDisassembler::Fail) {
871 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
872 // Calling the auto-generated decoder function for microMIPS 16-bit
874 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
876 if (Result != MCDisassembler::Fail) {
881 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
882 if (Result == MCDisassembler::Fail)
883 return MCDisassembler::Fail;
886 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
887 // Calling the auto-generated decoder function.
888 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
890 if (Result != MCDisassembler::Fail) {
896 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
897 // Calling the auto-generated decoder function.
898 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
900 if (Result != MCDisassembler::Fail) {
904 return MCDisassembler::Fail;
907 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
908 if (Result == MCDisassembler::Fail)
909 return MCDisassembler::Fail;
912 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
914 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
915 if (Result != MCDisassembler::Fail) {
921 if (hasMips32r6() && isGP64()) {
922 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
923 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
925 if (Result != MCDisassembler::Fail) {
932 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
933 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
935 if (Result != MCDisassembler::Fail) {
942 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
943 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
945 if (Result != MCDisassembler::Fail) {
952 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
953 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
955 if (Result != MCDisassembler::Fail) {
961 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
962 // Calling the auto-generated decoder function.
964 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
965 if (Result != MCDisassembler::Fail) {
970 return MCDisassembler::Fail;
973 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
976 const void *Decoder) {
978 return MCDisassembler::Fail;
982 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
985 const void *Decoder) {
988 return MCDisassembler::Fail;
990 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
991 Inst.addOperand(MCOperand::createReg(Reg));
992 return MCDisassembler::Success;
995 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
998 const void *Decoder) {
1000 return MCDisassembler::Fail;
1001 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1002 Inst.addOperand(MCOperand::createReg(Reg));
1003 return MCDisassembler::Success;
1006 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
1009 const void *Decoder) {
1011 return MCDisassembler::Fail;
1012 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1013 Inst.addOperand(MCOperand::createReg(Reg));
1014 return MCDisassembler::Success;
1017 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1020 const void *Decoder) {
1022 return MCDisassembler::Fail;
1023 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1024 Inst.addOperand(MCOperand::createReg(Reg));
1025 return MCDisassembler::Success;
1028 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1031 const void *Decoder) {
1033 return MCDisassembler::Fail;
1034 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1035 Inst.addOperand(MCOperand::createReg(Reg));
1036 return MCDisassembler::Success;
1039 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1042 const void *Decoder) {
1043 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1044 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1046 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1049 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1052 const void *Decoder) {
1053 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1056 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1059 const void *Decoder) {
1061 return MCDisassembler::Fail;
1063 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1064 Inst.addOperand(MCOperand::createReg(Reg));
1065 return MCDisassembler::Success;
1068 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1071 const void *Decoder) {
1073 return MCDisassembler::Fail;
1075 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1076 Inst.addOperand(MCOperand::createReg(Reg));
1077 return MCDisassembler::Success;
1080 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1083 const void *Decoder) {
1085 return MCDisassembler::Fail;
1086 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1087 Inst.addOperand(MCOperand::createReg(Reg));
1088 return MCDisassembler::Success;
1091 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1094 const void *Decoder) {
1096 return MCDisassembler::Fail;
1097 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1098 Inst.addOperand(MCOperand::createReg(Reg));
1099 return MCDisassembler::Success;
1102 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1104 const void *Decoder) {
1106 return MCDisassembler::Fail;
1108 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1109 Inst.addOperand(MCOperand::createReg(Reg));
1110 return MCDisassembler::Success;
1113 static DecodeStatus DecodeMem(MCInst &Inst,
1116 const void *Decoder) {
1117 int Offset = SignExtend32<16>(Insn & 0xffff);
1118 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1119 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1121 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1122 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1124 if (Inst.getOpcode() == Mips::SC ||
1125 Inst.getOpcode() == Mips::SCD)
1126 Inst.addOperand(MCOperand::createReg(Reg));
1128 Inst.addOperand(MCOperand::createReg(Reg));
1129 Inst.addOperand(MCOperand::createReg(Base));
1130 Inst.addOperand(MCOperand::createImm(Offset));
1132 return MCDisassembler::Success;
1135 static DecodeStatus DecodeMemEVA(MCInst &Inst,
1138 const void *Decoder) {
1139 int Offset = SignExtend32<9>(Insn >> 7);
1140 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1141 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1143 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1144 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1146 if (Inst.getOpcode() == Mips::SCE)
1147 Inst.addOperand(MCOperand::createReg(Reg));
1149 Inst.addOperand(MCOperand::createReg(Reg));
1150 Inst.addOperand(MCOperand::createReg(Base));
1151 Inst.addOperand(MCOperand::createImm(Offset));
1153 return MCDisassembler::Success;
1156 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1159 const void *Decoder) {
1160 int Offset = SignExtend32<16>(Insn & 0xffff);
1161 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1162 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1164 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1166 Inst.addOperand(MCOperand::createReg(Base));
1167 Inst.addOperand(MCOperand::createImm(Offset));
1168 Inst.addOperand(MCOperand::createImm(Hint));
1170 return MCDisassembler::Success;
1173 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1176 const void *Decoder) {
1177 int Offset = SignExtend32<12>(Insn & 0xfff);
1178 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1179 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1181 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1183 Inst.addOperand(MCOperand::createReg(Base));
1184 Inst.addOperand(MCOperand::createImm(Offset));
1185 Inst.addOperand(MCOperand::createImm(Hint));
1187 return MCDisassembler::Success;
1190 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
1193 const void *Decoder) {
1194 int Offset = SignExtend32<9>(Insn & 0x1ff);
1195 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1196 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1198 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1200 Inst.addOperand(MCOperand::createReg(Base));
1201 Inst.addOperand(MCOperand::createImm(Offset));
1202 Inst.addOperand(MCOperand::createImm(Hint));
1204 return MCDisassembler::Success;
1207 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
1210 const void *Decoder) {
1211 int Offset = SignExtend32<9>(Insn >> 7);
1212 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1213 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1215 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1217 Inst.addOperand(MCOperand::createReg(Base));
1218 Inst.addOperand(MCOperand::createImm(Offset));
1219 Inst.addOperand(MCOperand::createImm(Hint));
1221 return MCDisassembler::Success;
1224 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
1227 const void *Decoder) {
1228 int Offset = SignExtend32<9>(Insn & 0x1ff);
1229 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1230 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1232 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1233 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1235 Inst.addOperand(MCOperand::createReg(Reg));
1236 Inst.addOperand(MCOperand::createReg(Base));
1237 Inst.addOperand(MCOperand::createImm(Offset));
1239 return MCDisassembler::Success;
1242 static DecodeStatus DecodeSyncI(MCInst &Inst,
1245 const void *Decoder) {
1246 int Offset = SignExtend32<16>(Insn & 0xffff);
1247 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1249 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1251 Inst.addOperand(MCOperand::createReg(Base));
1252 Inst.addOperand(MCOperand::createImm(Offset));
1254 return MCDisassembler::Success;
1257 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1258 uint64_t Address, const void *Decoder) {
1259 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1260 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1261 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1263 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1264 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1266 Inst.addOperand(MCOperand::createReg(Reg));
1267 Inst.addOperand(MCOperand::createReg(Base));
1269 // The immediate field of an LD/ST instruction is scaled which means it must
1270 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1276 switch(Inst.getOpcode())
1279 assert (0 && "Unexpected instruction");
1280 return MCDisassembler::Fail;
1284 Inst.addOperand(MCOperand::createImm(Offset));
1288 Inst.addOperand(MCOperand::createImm(Offset * 2));
1292 Inst.addOperand(MCOperand::createImm(Offset * 4));
1296 Inst.addOperand(MCOperand::createImm(Offset * 8));
1300 return MCDisassembler::Success;
1303 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1306 const void *Decoder) {
1307 unsigned Offset = Insn & 0xf;
1308 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1309 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1311 switch (Inst.getOpcode()) {
1312 case Mips::LBU16_MM:
1313 case Mips::LHU16_MM:
1315 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1316 == MCDisassembler::Fail)
1317 return MCDisassembler::Fail;
1322 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1323 == MCDisassembler::Fail)
1324 return MCDisassembler::Fail;
1328 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1329 == MCDisassembler::Fail)
1330 return MCDisassembler::Fail;
1332 switch (Inst.getOpcode()) {
1333 case Mips::LBU16_MM:
1335 Inst.addOperand(MCOperand::createImm(-1));
1337 Inst.addOperand(MCOperand::createImm(Offset));
1340 Inst.addOperand(MCOperand::createImm(Offset));
1342 case Mips::LHU16_MM:
1344 Inst.addOperand(MCOperand::createImm(Offset << 1));
1348 Inst.addOperand(MCOperand::createImm(Offset << 2));
1352 return MCDisassembler::Success;
1355 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1358 const void *Decoder) {
1359 unsigned Offset = Insn & 0x1F;
1360 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1362 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1364 Inst.addOperand(MCOperand::createReg(Reg));
1365 Inst.addOperand(MCOperand::createReg(Mips::SP));
1366 Inst.addOperand(MCOperand::createImm(Offset << 2));
1368 return MCDisassembler::Success;
1371 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1374 const void *Decoder) {
1375 unsigned Offset = Insn & 0x7F;
1376 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1378 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1380 Inst.addOperand(MCOperand::createReg(Reg));
1381 Inst.addOperand(MCOperand::createReg(Mips::GP));
1382 Inst.addOperand(MCOperand::createImm(Offset << 2));
1384 return MCDisassembler::Success;
1387 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1390 const void *Decoder) {
1391 int Offset = SignExtend32<4>(Insn & 0xf);
1393 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1394 == MCDisassembler::Fail)
1395 return MCDisassembler::Fail;
1397 Inst.addOperand(MCOperand::createReg(Mips::SP));
1398 Inst.addOperand(MCOperand::createImm(Offset << 2));
1400 return MCDisassembler::Success;
1403 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1406 const void *Decoder) {
1407 int Offset = SignExtend32<9>(Insn & 0x1ff);
1408 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1409 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1411 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1412 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1414 Inst.addOperand(MCOperand::createReg(Reg));
1415 Inst.addOperand(MCOperand::createReg(Base));
1416 Inst.addOperand(MCOperand::createImm(Offset));
1418 return MCDisassembler::Success;
1421 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1424 const void *Decoder) {
1425 int Offset = SignExtend32<12>(Insn & 0x0fff);
1426 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1427 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1429 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1430 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1432 switch (Inst.getOpcode()) {
1433 case Mips::SWM32_MM:
1434 case Mips::LWM32_MM:
1435 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1436 == MCDisassembler::Fail)
1437 return MCDisassembler::Fail;
1438 Inst.addOperand(MCOperand::createReg(Base));
1439 Inst.addOperand(MCOperand::createImm(Offset));
1442 Inst.addOperand(MCOperand::createReg(Reg));
1445 Inst.addOperand(MCOperand::createReg(Reg));
1446 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1447 Inst.addOperand(MCOperand::createReg(Reg+1));
1449 Inst.addOperand(MCOperand::createReg(Base));
1450 Inst.addOperand(MCOperand::createImm(Offset));
1453 return MCDisassembler::Success;
1456 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1459 const void *Decoder) {
1460 int Offset = SignExtend32<16>(Insn & 0xffff);
1461 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1462 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1464 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1465 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1467 Inst.addOperand(MCOperand::createReg(Reg));
1468 Inst.addOperand(MCOperand::createReg(Base));
1469 Inst.addOperand(MCOperand::createImm(Offset));
1471 return MCDisassembler::Success;
1474 static DecodeStatus DecodeFMem(MCInst &Inst,
1477 const void *Decoder) {
1478 int Offset = SignExtend32<16>(Insn & 0xffff);
1479 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1480 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1482 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1483 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1485 Inst.addOperand(MCOperand::createReg(Reg));
1486 Inst.addOperand(MCOperand::createReg(Base));
1487 Inst.addOperand(MCOperand::createImm(Offset));
1489 return MCDisassembler::Success;
1492 static DecodeStatus DecodeFMem2(MCInst &Inst,
1495 const void *Decoder) {
1496 int Offset = SignExtend32<16>(Insn & 0xffff);
1497 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1498 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1500 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1501 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1503 Inst.addOperand(MCOperand::createReg(Reg));
1504 Inst.addOperand(MCOperand::createReg(Base));
1505 Inst.addOperand(MCOperand::createImm(Offset));
1507 return MCDisassembler::Success;
1510 static DecodeStatus DecodeFMem3(MCInst &Inst,
1513 const void *Decoder) {
1514 int Offset = SignExtend32<16>(Insn & 0xffff);
1515 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1516 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1518 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1519 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1521 Inst.addOperand(MCOperand::createReg(Reg));
1522 Inst.addOperand(MCOperand::createReg(Base));
1523 Inst.addOperand(MCOperand::createImm(Offset));
1525 return MCDisassembler::Success;
1528 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1531 const void *Decoder) {
1532 int Offset = SignExtend32<11>(Insn & 0x07ff);
1533 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1534 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1536 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1537 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1539 Inst.addOperand(MCOperand::createReg(Reg));
1540 Inst.addOperand(MCOperand::createReg(Base));
1541 Inst.addOperand(MCOperand::createImm(Offset));
1543 return MCDisassembler::Success;
1545 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1548 const void *Decoder) {
1549 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1550 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1551 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1553 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1554 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1556 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1557 Inst.addOperand(MCOperand::createReg(Rt));
1560 Inst.addOperand(MCOperand::createReg(Rt));
1561 Inst.addOperand(MCOperand::createReg(Base));
1562 Inst.addOperand(MCOperand::createImm(Offset));
1564 return MCDisassembler::Success;
1567 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1570 const void *Decoder) {
1571 // Currently only hardware register 29 is supported.
1573 return MCDisassembler::Fail;
1574 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1575 return MCDisassembler::Success;
1578 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1581 const void *Decoder) {
1582 if (RegNo > 30 || RegNo %2)
1583 return MCDisassembler::Fail;
1586 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1587 Inst.addOperand(MCOperand::createReg(Reg));
1588 return MCDisassembler::Success;
1591 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1594 const void *Decoder) {
1596 return MCDisassembler::Fail;
1598 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1599 Inst.addOperand(MCOperand::createReg(Reg));
1600 return MCDisassembler::Success;
1603 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1606 const void *Decoder) {
1608 return MCDisassembler::Fail;
1610 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1611 Inst.addOperand(MCOperand::createReg(Reg));
1612 return MCDisassembler::Success;
1615 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1618 const void *Decoder) {
1620 return MCDisassembler::Fail;
1622 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1623 Inst.addOperand(MCOperand::createReg(Reg));
1624 return MCDisassembler::Success;
1627 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1630 const void *Decoder) {
1632 return MCDisassembler::Fail;
1634 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1635 Inst.addOperand(MCOperand::createReg(Reg));
1636 return MCDisassembler::Success;
1639 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1642 const void *Decoder) {
1644 return MCDisassembler::Fail;
1646 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1647 Inst.addOperand(MCOperand::createReg(Reg));
1648 return MCDisassembler::Success;
1651 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1654 const void *Decoder) {
1656 return MCDisassembler::Fail;
1658 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1659 Inst.addOperand(MCOperand::createReg(Reg));
1660 return MCDisassembler::Success;
1663 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1666 const void *Decoder) {
1668 return MCDisassembler::Fail;
1670 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1671 Inst.addOperand(MCOperand::createReg(Reg));
1672 return MCDisassembler::Success;
1675 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1678 const void *Decoder) {
1680 return MCDisassembler::Fail;
1682 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1683 Inst.addOperand(MCOperand::createReg(Reg));
1684 return MCDisassembler::Success;
1687 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
1690 const void *Decoder) {
1692 return MCDisassembler::Fail;
1694 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
1695 Inst.addOperand(MCOperand::createReg(Reg));
1696 return MCDisassembler::Success;
1699 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1702 const void *Decoder) {
1704 return MCDisassembler::Fail;
1706 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1707 Inst.addOperand(MCOperand::createReg(Reg));
1708 return MCDisassembler::Success;
1711 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1714 const void *Decoder) {
1715 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1716 Inst.addOperand(MCOperand::createImm(BranchOffset));
1717 return MCDisassembler::Success;
1720 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1723 const void *Decoder) {
1725 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1726 Inst.addOperand(MCOperand::createImm(JumpOffset));
1727 return MCDisassembler::Success;
1730 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1733 const void *Decoder) {
1734 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1736 Inst.addOperand(MCOperand::createImm(BranchOffset));
1737 return MCDisassembler::Success;
1740 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1743 const void *Decoder) {
1744 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1746 Inst.addOperand(MCOperand::createImm(BranchOffset));
1747 return MCDisassembler::Success;
1750 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1753 const void *Decoder) {
1754 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1755 Inst.addOperand(MCOperand::createImm(BranchOffset));
1756 return MCDisassembler::Success;
1759 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1762 const void *Decoder) {
1763 int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1764 Inst.addOperand(MCOperand::createImm(BranchOffset));
1765 return MCDisassembler::Success;
1768 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1771 const void *Decoder) {
1772 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1773 Inst.addOperand(MCOperand::createImm(BranchOffset));
1774 return MCDisassembler::Success;
1777 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1780 const void *Decoder) {
1781 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1782 Inst.addOperand(MCOperand::createImm(JumpOffset));
1783 return MCDisassembler::Success;
1786 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1789 const void *Decoder) {
1791 Inst.addOperand(MCOperand::createImm(1));
1792 else if (Value == 0x7)
1793 Inst.addOperand(MCOperand::createImm(-1));
1795 Inst.addOperand(MCOperand::createImm(Value << 2));
1796 return MCDisassembler::Success;
1799 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1802 const void *Decoder) {
1803 Inst.addOperand(MCOperand::createImm(Value << 2));
1804 return MCDisassembler::Success;
1807 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1810 const void *Decoder) {
1812 Inst.addOperand(MCOperand::createImm(-1));
1814 Inst.addOperand(MCOperand::createImm(Value));
1815 return MCDisassembler::Success;
1818 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
1821 const void *Decoder) {
1822 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
1823 return MCDisassembler::Success;
1826 static DecodeStatus DecodeSimm4(MCInst &Inst,
1829 const void *Decoder) {
1830 Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1831 return MCDisassembler::Success;
1834 static DecodeStatus DecodeSimm16(MCInst &Inst,
1837 const void *Decoder) {
1838 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1839 return MCDisassembler::Success;
1842 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1845 const void *Decoder) {
1846 // We add one to the immediate field as it was encoded as 'imm - 1'.
1847 Inst.addOperand(MCOperand::createImm(Insn + 1));
1848 return MCDisassembler::Success;
1851 static DecodeStatus DecodeInsSize(MCInst &Inst,
1854 const void *Decoder) {
1855 // First we need to grab the pos(lsb) from MCInst.
1856 int Pos = Inst.getOperand(2).getImm();
1857 int Size = (int) Insn - Pos + 1;
1858 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1859 return MCDisassembler::Success;
1862 static DecodeStatus DecodeExtSize(MCInst &Inst,
1865 const void *Decoder) {
1866 int Size = (int) Insn + 1;
1867 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1868 return MCDisassembler::Success;
1871 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1872 uint64_t Address, const void *Decoder) {
1873 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1874 return MCDisassembler::Success;
1877 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1878 uint64_t Address, const void *Decoder) {
1879 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1880 return MCDisassembler::Success;
1883 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1884 uint64_t Address, const void *Decoder) {
1885 int32_t DecodedValue;
1887 case 0: DecodedValue = 256; break;
1888 case 1: DecodedValue = 257; break;
1889 case 510: DecodedValue = -258; break;
1890 case 511: DecodedValue = -257; break;
1891 default: DecodedValue = SignExtend32<9>(Insn); break;
1893 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1894 return MCDisassembler::Success;
1897 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1898 uint64_t Address, const void *Decoder) {
1899 // Insn must be >= 0, since it is unsigned that condition is always true.
1901 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1903 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1904 return MCDisassembler::Success;
1907 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1908 uint64_t Address, const void *Decoder) {
1909 Inst.addOperand(MCOperand::createImm(Insn << 2));
1910 return MCDisassembler::Success;
1913 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1916 const void *Decoder) {
1917 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1918 Mips::S6, Mips::FP};
1921 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1922 // Empty register lists are not allowed.
1924 return MCDisassembler::Fail;
1926 RegNum = RegLst & 0xf;
1927 for (unsigned i = 0; i < RegNum; i++)
1928 Inst.addOperand(MCOperand::createReg(Regs[i]));
1931 Inst.addOperand(MCOperand::createReg(Mips::RA));
1933 return MCDisassembler::Success;
1936 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1938 const void *Decoder) {
1939 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1940 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1941 unsigned RegNum = RegLst & 0x3;
1943 for (unsigned i = 0; i <= RegNum; i++)
1944 Inst.addOperand(MCOperand::createReg(Regs[i]));
1946 Inst.addOperand(MCOperand::createReg(Mips::RA));
1948 return MCDisassembler::Success;
1951 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
1952 uint64_t Address, const void *Decoder) {
1954 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1958 return MCDisassembler::Fail;
1960 Inst.addOperand(MCOperand::createReg(Mips::A1));
1961 Inst.addOperand(MCOperand::createReg(Mips::A2));
1964 Inst.addOperand(MCOperand::createReg(Mips::A1));
1965 Inst.addOperand(MCOperand::createReg(Mips::A3));
1968 Inst.addOperand(MCOperand::createReg(Mips::A2));
1969 Inst.addOperand(MCOperand::createReg(Mips::A3));
1972 Inst.addOperand(MCOperand::createReg(Mips::A0));
1973 Inst.addOperand(MCOperand::createReg(Mips::S5));
1976 Inst.addOperand(MCOperand::createReg(Mips::A0));
1977 Inst.addOperand(MCOperand::createReg(Mips::S6));
1980 Inst.addOperand(MCOperand::createReg(Mips::A0));
1981 Inst.addOperand(MCOperand::createReg(Mips::A1));
1984 Inst.addOperand(MCOperand::createReg(Mips::A0));
1985 Inst.addOperand(MCOperand::createReg(Mips::A2));
1988 Inst.addOperand(MCOperand::createReg(Mips::A0));
1989 Inst.addOperand(MCOperand::createReg(Mips::A3));
1993 return MCDisassembler::Success;
1996 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1997 uint64_t Address, const void *Decoder) {
1998 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
1999 return MCDisassembler::Success;