lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 class MipsDisassembler : public MCDisassembler {
  34   bool IsMicroMips;
  35   bool IsBigEndian;
  36 public:
  37   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
  43   bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
  44   bool hasMips32r6() const {
  45     return STI.getFeatureBits()[Mips::FeatureMips32r6];
  46   }
  47
  48   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
  49
  50   bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
  51
  52   bool hasCOP3() const {
  53     // Only present in MIPS-I and MIPS-II
  54     return !hasMips32() && !hasMips3();
  55   }
  56
  57   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  58                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  59                               raw_ostream &VStream,
  60                               raw_ostream &CStream) const override;
  61 };
  62
  63 } // end anonymous namespace
  64
  65 // Forward declare these because the autogenerated code will reference them.
  66 // Definitions are further down.
  67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  68                                              unsigned RegNo,
  69                                              uint64_t Address,
  70                                              const void *Decoder);
  71
  72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
  73                                                  unsigned RegNo,
  74                                                  uint64_t Address,
  75                                                  const void *Decoder);
  76
  77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
  78                                                unsigned RegNo,
  79                                                uint64_t Address,
  80                                                const void *Decoder);
  81
  82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
  83                                                    unsigned RegNo,
  84                                                    uint64_t Address,
  85                                                    const void *Decoder);
  86
  87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
  88                                                     unsigned RegNo,
  89                                                     uint64_t Address,
  90                                                     const void *Decoder);
  91
  92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
  93                                              unsigned RegNo,
  94                                              uint64_t Address,
  95                                              const void *Decoder);
  96
  97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
  98                                            unsigned Insn,
  99                                            uint64_t Address,
 100                                            const void *Decoder);
 101
 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 103                                             unsigned RegNo,
 104                                             uint64_t Address,
 105                                             const void *Decoder);
 106
 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 108                                              unsigned RegNo,
 109                                              uint64_t Address,
 110                                              const void *Decoder);
 111
 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 113                                              unsigned RegNo,
 114                                              uint64_t Address,
 115                                              const void *Decoder);
 116
 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 118                                            unsigned RegNo,
 119                                            uint64_t Address,
 120                                            const void *Decoder);
 121
 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 123                                            unsigned RegNo,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 128                                              uint64_t Address,
 129                                              const void *Decoder);
 130
 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 132                                               unsigned Insn,
 133                                               uint64_t Address,
 134                                               const void *Decoder);
 135
 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 137                                               unsigned RegNo,
 138                                               uint64_t Address,
 139                                               const void *Decoder);
 140
 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 142                                                 unsigned RegNo,
 143                                                 uint64_t Address,
 144                                                 const void *Decoder);
 145
 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 147                                                unsigned RegNo,
 148                                                uint64_t Address,
 149                                                const void *Decoder);
 150
 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 152                                                unsigned RegNo,
 153                                                uint64_t Address,
 154                                                const void *Decoder);
 155
 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 157                                                unsigned RegNo,
 158                                                uint64_t Address,
 159                                                const void *Decoder);
 160
 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 162                                                unsigned RegNo,
 163                                                uint64_t Address,
 164                                                const void *Decoder);
 165
 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 167                                                unsigned RegNo,
 168                                                uint64_t Address,
 169                                                const void *Decoder);
 170
 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
 182                                             unsigned RegNo,
 183                                             uint64_t Address,
 184                                             const void *Decoder);
 185
 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 187                                             unsigned RegNo,
 188                                             uint64_t Address,
 189                                             const void *Decoder);
 190
 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 192                                        unsigned Offset,
 193                                        uint64_t Address,
 194                                        const void *Decoder);
 195
 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 197                                      unsigned Insn,
 198                                      uint64_t Address,
 199                                      const void *Decoder);
 200
 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 202                                          unsigned Offset,
 203                                          uint64_t Address,
 204                                          const void *Decoder);
 205
 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 207                                          unsigned Offset,
 208                                          uint64_t Address,
 209                                          const void *Decoder);
 210
 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 212 // shifted left by 1 bit.
 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 214                                           unsigned Offset,
 215                                           uint64_t Address,
 216                                           const void *Decoder);
 217
 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 219 // shifted left by 1 bit.
 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 221                                            unsigned Offset,
 222                                            uint64_t Address,
 223                                            const void *Decoder);
 224
 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 226 // shifted left by 1 bit.
 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 228                                          unsigned Offset,
 229                                          uint64_t Address,
 230                                          const void *Decoder);
 231
 232 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
 233 // shifted left by 1 bit.
 234 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
 235                                            unsigned Offset,
 236                                            uint64_t Address,
 237                                            const void *Decoder);
 238
 239 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 240 // shifted left by 1 bit.
 241 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 242                                        unsigned Insn,
 243                                        uint64_t Address,
 244                                        const void *Decoder);
 245
 246 static DecodeStatus DecodeMem(MCInst &Inst,
 247                               unsigned Insn,
 248                               uint64_t Address,
 249                               const void *Decoder);
 250
 251 static DecodeStatus DecodeMemEVA(MCInst &Inst,
 252                                  unsigned Insn,
 253                                  uint64_t Address,
 254                                  const void *Decoder);
 255
 256 static DecodeStatus DecodeLoadByte9(MCInst &Inst,
 257                                     unsigned Insn,
 258                                     uint64_t Address,
 259                                     const void *Decoder);
 260
 261 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
 262                                      unsigned Insn,
 263                                      uint64_t Address,
 264                                      const void *Decoder);
 265
 266 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 267                               unsigned Insn,
 268                               uint64_t Address,
 269                               const void *Decoder);
 270
 271 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
 272                                              unsigned Insn,
 273                                              uint64_t Address,
 274                                              const void *Decoder);
 275
 276 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 277                                     unsigned Insn,
 278                                     uint64_t Address,
 279                                     const void *Decoder);
 280
 281 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
 282                                        unsigned Insn,
 283                                        uint64_t Address,
 284                                        const void *Decoder);
 285
 286 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
 287                                     unsigned Insn,
 288                                     uint64_t Address,
 289                                     const void *Decoder);
 290
 291 static DecodeStatus DecodeSyncI(MCInst &Inst,
 292                                 unsigned Insn,
 293                                 uint64_t Address,
 294                                 const void *Decoder);
 295
 296 static DecodeStatus DecodeSynciR6(MCInst &Inst,
 297                                   unsigned Insn,
 298                                   uint64_t Address,
 299                                   const void *Decoder);
 300
 301 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 302                                     uint64_t Address, const void *Decoder);
 303
 304 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 305                                     unsigned Insn,
 306                                     uint64_t Address,
 307                                     const void *Decoder);
 308
 309 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 310                                           unsigned Insn,
 311                                           uint64_t Address,
 312                                           const void *Decoder);
 313
 314 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 315                                           unsigned Insn,
 316                                           uint64_t Address,
 317                                           const void *Decoder);
 318
 319 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
 320                                                unsigned Insn,
 321                                                uint64_t Address,
 322                                                const void *Decoder);
 323
 324 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
 325                                     unsigned Insn,
 326                                     uint64_t Address,
 327                                     const void *Decoder);
 328
 329 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 330                                      unsigned Insn,
 331                                      uint64_t Address,
 332                                      const void *Decoder);
 333
 334 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 335                                      unsigned Insn,
 336                                      uint64_t Address,
 337                                      const void *Decoder);
 338
 339 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 340                                uint64_t Address,
 341                                const void *Decoder);
 342
 343 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 344                                uint64_t Address,
 345                                const void *Decoder);
 346
 347 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 348                                uint64_t Address,
 349                                const void *Decoder);
 350
 351 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 352                                uint64_t Address,
 353                                const void *Decoder);
 354
 355 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 356                                        unsigned Insn,
 357                                        uint64_t Address,
 358                                        const void *Decoder);
 359
 360 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 361                                        unsigned Value,
 362                                        uint64_t Address,
 363                                        const void *Decoder);
 364
 365 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 366                                     unsigned Value,
 367                                     uint64_t Address,
 368                                     const void *Decoder);
 369
 370 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 371                                   unsigned Value,
 372                                   uint64_t Address,
 373                                   const void *Decoder);
 374
 375 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
 376                                               unsigned Value,
 377                                               uint64_t Address,
 378                                               const void *Decoder);
 379
 380 static DecodeStatus DecodeSimm4(MCInst &Inst,
 381                                 unsigned Value,
 382                                 uint64_t Address,
 383                                 const void *Decoder);
 384
 385 static DecodeStatus DecodeSimm16(MCInst &Inst,
 386                                  unsigned Insn,
 387                                  uint64_t Address,
 388                                  const void *Decoder);
 389
 390 template <unsigned Bits, int Offset>
 391 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
 392                                          uint64_t Address, const void *Decoder);
 393
 394 static DecodeStatus DecodeInsSize(MCInst &Inst,
 395                                   unsigned Insn,
 396                                   uint64_t Address,
 397                                   const void *Decoder);
 398
 399 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 400                                      uint64_t Address, const void *Decoder);
 401
 402 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 403                                      uint64_t Address, const void *Decoder);
 404
 405 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 406                                   uint64_t Address, const void *Decoder);
 407
 408 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 409                                     uint64_t Address, const void *Decoder);
 410
 411 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 412                                    uint64_t Address, const void *Decoder);
 413
 414 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 415                                      uint64_t Address, const void *Decoder);
 416
 417 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 418 /// handle.
 419 template <typename InsnType>
 420 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 421                                    const void *Decoder);
 422
 423 template <typename InsnType>
 424 static DecodeStatus
 425 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 426                       const void *Decoder);
 427
 428 template <typename InsnType>
 429 static DecodeStatus
 430 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 431                        const void *Decoder);
 432
 433 template <typename InsnType>
 434 static DecodeStatus
 435 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 436                        const void *Decoder);
 437
 438 template <typename InsnType>
 439 static DecodeStatus
 440 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 441                        const void *Decoder);
 442
 443 template <typename InsnType>
 444 static DecodeStatus
 445 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 446                       const void *Decoder);
 447
 448 template <typename InsnType>
 449 static DecodeStatus
 450 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 451                        const void *Decoder);
 452
 453 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 454                                          uint64_t Address,
 455                                          const void *Decoder);
 456
 457 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 458                                            uint64_t Address,
 459                                            const void *Decoder);
 460
 461 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
 462                                        uint64_t Address,
 463                                        const void *Decoder);
 464
 465 namespace llvm {
 466 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 467               TheMips64elTarget;
 468 }
 469
 470 static MCDisassembler *createMipsDisassembler(
 471                        const Target &T,
 472                        const MCSubtargetInfo &STI,
 473                        MCContext &Ctx) {
 474   return new MipsDisassembler(STI, Ctx, true);
 475 }
 476
 477 static MCDisassembler *createMipselDisassembler(
 478                        const Target &T,
 479                        const MCSubtargetInfo &STI,
 480                        MCContext &Ctx) {
 481   return new MipsDisassembler(STI, Ctx, false);
 482 }
 483
 484 extern "C" void LLVMInitializeMipsDisassembler() {
 485   // Register the disassembler.
 486   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 487                                          createMipsDisassembler);
 488   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 489                                          createMipselDisassembler);
 490   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 491                                          createMipsDisassembler);
 492   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 493                                          createMipselDisassembler);
 494 }
 495
 496 #include "MipsGenDisassemblerTables.inc"
 497
 498 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 499   const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
 500   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 501   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 502 }
 503
 504 template <typename InsnType>
 505 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 506                                    const void *Decoder) {
 507   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 508   // The size of the n field depends on the element size
 509   // The register class also depends on this.
 510   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 511   unsigned NSize = 0;
 512   DecodeFN RegDecoder = nullptr;
 513   if ((tmp & 0x18) == 0x00) { // INSVE_B
 514     NSize = 4;
 515     RegDecoder = DecodeMSA128BRegisterClass;
 516   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 517     NSize = 3;
 518     RegDecoder = DecodeMSA128HRegisterClass;
 519   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 520     NSize = 2;
 521     RegDecoder = DecodeMSA128WRegisterClass;
 522   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 523     NSize = 1;
 524     RegDecoder = DecodeMSA128DRegisterClass;
 525   } else
 526     llvm_unreachable("Invalid encoding");
 527
 528   assert(NSize != 0 && RegDecoder != nullptr);
 529
 530   // $wd
 531   tmp = fieldFromInstruction(insn, 6, 5);
 532   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 533     return MCDisassembler::Fail;
 534   // $wd_in
 535   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 536     return MCDisassembler::Fail;
 537   // $n
 538   tmp = fieldFromInstruction(insn, 16, NSize);
 539   MI.addOperand(MCOperand::createImm(tmp));
 540   // $ws
 541   tmp = fieldFromInstruction(insn, 11, 5);
 542   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 543     return MCDisassembler::Fail;
 544   // $n2
 545   MI.addOperand(MCOperand::createImm(0));
 546
 547   return MCDisassembler::Success;
 548 }
 549
 550 template <typename InsnType>
 551 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 552                                           uint64_t Address,
 553                                           const void *Decoder) {
 554   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 555   // (otherwise we would have matched the ADDI instruction from the earlier
 556   // ISA's instead).
 557   //
 558   // We have:
 559   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 560   //      BOVC if rs >= rt
 561   //      BEQZALC if rs == 0 && rt != 0
 562   //      BEQC if rs < rt && rs != 0
 563
 564   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 565   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 566   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 567   bool HasRs = false;
 568
 569   if (Rs >= Rt) {
 570     MI.setOpcode(Mips::BOVC);
 571     HasRs = true;
 572   } else if (Rs != 0 && Rs < Rt) {
 573     MI.setOpcode(Mips::BEQC);
 574     HasRs = true;
 575   } else
 576     MI.setOpcode(Mips::BEQZALC);
 577
 578   if (HasRs)
 579     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 580                                        Rs)));
 581
 582   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 583                                      Rt)));
 584   MI.addOperand(MCOperand::createImm(Imm));
 585
 586   return MCDisassembler::Success;
 587 }
 588
 589 template <typename InsnType>
 590 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 591                                            uint64_t Address,
 592                                            const void *Decoder) {
 593   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 594   // (otherwise we would have matched the ADDI instruction from the earlier
 595   // ISA's instead).
 596   //
 597   // We have:
 598   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 599   //      BNVC if rs >= rt
 600   //      BNEZALC if rs == 0 && rt != 0
 601   //      BNEC if rs < rt && rs != 0
 602
 603   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 604   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 605   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 606   bool HasRs = false;
 607
 608   if (Rs >= Rt) {
 609     MI.setOpcode(Mips::BNVC);
 610     HasRs = true;
 611   } else if (Rs != 0 && Rs < Rt) {
 612     MI.setOpcode(Mips::BNEC);
 613     HasRs = true;
 614   } else
 615     MI.setOpcode(Mips::BNEZALC);
 616
 617   if (HasRs)
 618     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 619                                        Rs)));
 620
 621   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 622                                      Rt)));
 623   MI.addOperand(MCOperand::createImm(Imm));
 624
 625   return MCDisassembler::Success;
 626 }
 627
 628 template <typename InsnType>
 629 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 630                                            uint64_t Address,
 631                                            const void *Decoder) {
 632   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 633   // (otherwise we would have matched the BLEZL instruction from the earlier
 634   // ISA's instead).
 635   //
 636   // We have:
 637   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 638   //      Invalid if rs == 0
 639   //      BLEZC   if rs == 0  && rt != 0
 640   //      BGEZC   if rs == rt && rt != 0
 641   //      BGEC    if rs != rt && rs != 0  && rt != 0
 642
 643   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 644   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 645   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 646   bool HasRs = false;
 647
 648   if (Rt == 0)
 649     return MCDisassembler::Fail;
 650   else if (Rs == 0)
 651     MI.setOpcode(Mips::BLEZC);
 652   else if (Rs == Rt)
 653     MI.setOpcode(Mips::BGEZC);
 654   else {
 655     HasRs = true;
 656     MI.setOpcode(Mips::BGEC);
 657   }
 658
 659   if (HasRs)
 660     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 661                                        Rs)));
 662
 663   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 664                                      Rt)));
 665
 666   MI.addOperand(MCOperand::createImm(Imm));
 667
 668   return MCDisassembler::Success;
 669 }
 670
 671 template <typename InsnType>
 672 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 673                                            uint64_t Address,
 674                                            const void *Decoder) {
 675   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 676   // (otherwise we would have matched the BGTZL instruction from the earlier
 677   // ISA's instead).
 678   //
 679   // We have:
 680   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 681   //      Invalid if rs == 0
 682   //      BGTZC   if rs == 0  && rt != 0
 683   //      BLTZC   if rs == rt && rt != 0
 684   //      BLTC    if rs != rt && rs != 0  && rt != 0
 685
 686   bool HasRs = false;
 687
 688   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 689   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 690   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 691
 692   if (Rt == 0)
 693     return MCDisassembler::Fail;
 694   else if (Rs == 0)
 695     MI.setOpcode(Mips::BGTZC);
 696   else if (Rs == Rt)
 697     MI.setOpcode(Mips::BLTZC);
 698   else {
 699     MI.setOpcode(Mips::BLTC);
 700     HasRs = true;
 701   }
 702
 703   if (HasRs)
 704     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 705                                               Rs)));
 706
 707   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 708                                      Rt)));
 709
 710   MI.addOperand(MCOperand::createImm(Imm));
 711
 712   return MCDisassembler::Success;
 713 }
 714
 715 template <typename InsnType>
 716 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 717                                           uint64_t Address,
 718                                           const void *Decoder) {
 719   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 720   // (otherwise we would have matched the BGTZ instruction from the earlier
 721   // ISA's instead).
 722   //
 723   // We have:
 724   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 725   //      BGTZ    if rt == 0
 726   //      BGTZALC if rs == 0 && rt != 0
 727   //      BLTZALC if rs != 0 && rs == rt
 728   //      BLTUC   if rs != 0 && rs != rt
 729
 730   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 731   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 732   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 733   bool HasRs = false;
 734   bool HasRt = false;
 735
 736   if (Rt == 0) {
 737     MI.setOpcode(Mips::BGTZ);
 738     HasRs = true;
 739   } else if (Rs == 0) {
 740     MI.setOpcode(Mips::BGTZALC);
 741     HasRt = true;
 742   } else if (Rs == Rt) {
 743     MI.setOpcode(Mips::BLTZALC);
 744     HasRs = true;
 745   } else {
 746     MI.setOpcode(Mips::BLTUC);
 747     HasRs = true;
 748     HasRt = true;
 749   }
 750
 751   if (HasRs)
 752     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 753                                        Rs)));
 754
 755   if (HasRt)
 756     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 757                                        Rt)));
 758
 759   MI.addOperand(MCOperand::createImm(Imm));
 760
 761   return MCDisassembler::Success;
 762 }
 763
 764 template <typename InsnType>
 765 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 766                                            uint64_t Address,
 767                                            const void *Decoder) {
 768   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 769   // (otherwise we would have matched the BLEZL instruction from the earlier
 770   // ISA's instead).
 771   //
 772   // We have:
 773   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 774   //      Invalid   if rs == 0
 775   //      BLEZALC   if rs == 0  && rt != 0
 776   //      BGEZALC   if rs == rt && rt != 0
 777   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 778
 779   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 780   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 781   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 782   bool HasRs = false;
 783
 784   if (Rt == 0)
 785     return MCDisassembler::Fail;
 786   else if (Rs == 0)
 787     MI.setOpcode(Mips::BLEZALC);
 788   else if (Rs == Rt)
 789     MI.setOpcode(Mips::BGEZALC);
 790   else {
 791     HasRs = true;
 792     MI.setOpcode(Mips::BGEUC);
 793   }
 794
 795   if (HasRs)
 796     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 797                                        Rs)));
 798   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 799                                      Rt)));
 800
 801   MI.addOperand(MCOperand::createImm(Imm));
 802
 803   return MCDisassembler::Success;
 804 }
 805
 806 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 807 /// according to the given endianess.
 808 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 809                                       uint64_t &Size, uint32_t &Insn,
 810                                       bool IsBigEndian) {
 811   // We want to read exactly 2 Bytes of data.
 812   if (Bytes.size() < 2) {
 813     Size = 0;
 814     return MCDisassembler::Fail;
 815   }
 816
 817   if (IsBigEndian) {
 818     Insn = (Bytes[0] << 8) | Bytes[1];
 819   } else {
 820     Insn = (Bytes[1] << 8) | Bytes[0];
 821   }
 822
 823   return MCDisassembler::Success;
 824 }
 825
 826 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 827 /// according to the given endianess
 828 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 829                                       uint64_t &Size, uint32_t &Insn,
 830                                       bool IsBigEndian, bool IsMicroMips) {
 831   // We want to read exactly 4 Bytes of data.
 832   if (Bytes.size() < 4) {
 833     Size = 0;
 834     return MCDisassembler::Fail;
 835   }
 836
 837   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 838   // always precede the low 16 bits in the instruction stream (that is, they
 839   // are placed at lower addresses in the instruction stream).
 840   //
 841   // microMIPS byte ordering:
 842   //   Big-endian:    0 | 1 | 2 | 3
 843   //   Little-endian: 1 | 0 | 3 | 2
 844
 845   if (IsBigEndian) {
 846     // Encoded as a big-endian 32-bit word in the stream.
 847     Insn =
 848         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 849   } else {
 850     if (IsMicroMips) {
 851       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 852              (Bytes[1] << 24);
 853     } else {
 854       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 855              (Bytes[3] << 24);
 856     }
 857   }
 858
 859   return MCDisassembler::Success;
 860 }
 861
 862 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 863                                               ArrayRef<uint8_t> Bytes,
 864                                               uint64_t Address,
 865                                               raw_ostream &VStream,
 866                                               raw_ostream &CStream) const {
 867   uint32_t Insn;
 868   DecodeStatus Result;
 869
 870   if (IsMicroMips) {
 871     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 872     if (Result == MCDisassembler::Fail)
 873       return MCDisassembler::Fail;
 874
 875     if (hasMips32r6()) {
 876       DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
 877       // Calling the auto-generated decoder function for microMIPS32R6
 878       // (and microMIPS64R6) 16-bit instructions.
 879       Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
 880                                  Address, this, STI);
 881       if (Result != MCDisassembler::Fail) {
 882         Size = 2;
 883         return Result;
 884       }
 885     }
 886
 887     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 888     // Calling the auto-generated decoder function for microMIPS 16-bit
 889     // instructions.
 890     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 891                                this, STI);
 892     if (Result != MCDisassembler::Fail) {
 893       Size = 2;
 894       return Result;
 895     }
 896
 897     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 898     if (Result == MCDisassembler::Fail)
 899       return MCDisassembler::Fail;
 900
 901     if (hasMips32r6()) {
 902       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
 903       // Calling the auto-generated decoder function.
 904       Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
 905                                  this, STI);
 906       if (Result != MCDisassembler::Fail) {
 907         Size = 4;
 908         return Result;
 909       }
 910     }
 911
 912     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 913     // Calling the auto-generated decoder function.
 914     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 915                                this, STI);
 916     if (Result != MCDisassembler::Fail) {
 917       Size = 4;
 918       return Result;
 919     }
 920     // This is an invalid instruction. Let the disassembler move forward by the
 921     // minimum instruction size.
 922     Size = 2;
 923     return MCDisassembler::Fail;
 924   }
 925
 926   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 927   if (Result == MCDisassembler::Fail) {
 928     Size = 4;
 929     return MCDisassembler::Fail;
 930   }
 931
 932   if (hasCOP3()) {
 933     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 934     Result =
 935         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 936     if (Result != MCDisassembler::Fail) {
 937       Size = 4;
 938       return Result;
 939     }
 940   }
 941
 942   if (hasMips32r6() && isGP64()) {
 943     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 944     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 945                                Address, this, STI);
 946     if (Result != MCDisassembler::Fail) {
 947       Size = 4;
 948       return Result;
 949     }
 950   }
 951
 952   if (hasMips32r6()) {
 953     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 954     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 955                                Address, this, STI);
 956     if (Result != MCDisassembler::Fail) {
 957       Size = 4;
 958       return Result;
 959     }
 960   }
 961
 962   if (hasCnMips()) {
 963     DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
 964     Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
 965                                Address, this, STI);
 966     if (Result != MCDisassembler::Fail) {
 967       Size = 4;
 968       return Result;
 969     }
 970   }
 971
 972   if (isGP64()) {
 973     DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
 974     Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
 975                                Address, this, STI);
 976     if (Result != MCDisassembler::Fail) {
 977       Size = 4;
 978       return Result;
 979     }
 980   }
 981
 982   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 983   // Calling the auto-generated decoder function.
 984   Result =
 985       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 986   if (Result != MCDisassembler::Fail) {
 987     Size = 4;
 988     return Result;
 989   }
 990
 991   Size = 4;
 992   return MCDisassembler::Fail;
 993 }
 994
 995 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 996                                                  unsigned RegNo,
 997                                                  uint64_t Address,
 998                                                  const void *Decoder) {
 999
1000   return MCDisassembler::Fail;
1001
1002 }
1003
1004 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
1005                                              unsigned RegNo,
1006                                              uint64_t Address,
1007                                              const void *Decoder) {
1008
1009   if (RegNo > 31)
1010     return MCDisassembler::Fail;
1011
1012   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1013   Inst.addOperand(MCOperand::createReg(Reg));
1014   return MCDisassembler::Success;
1015 }
1016
1017 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
1018                                                unsigned RegNo,
1019                                                uint64_t Address,
1020                                                const void *Decoder) {
1021   if (RegNo > 7)
1022     return MCDisassembler::Fail;
1023   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1024   Inst.addOperand(MCOperand::createReg(Reg));
1025   return MCDisassembler::Success;
1026 }
1027
1028 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
1029                                                    unsigned RegNo,
1030                                                    uint64_t Address,
1031                                                    const void *Decoder) {
1032   if (RegNo > 7)
1033     return MCDisassembler::Fail;
1034   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1035   Inst.addOperand(MCOperand::createReg(Reg));
1036   return MCDisassembler::Success;
1037 }
1038
1039 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1040                                                     unsigned RegNo,
1041                                                     uint64_t Address,
1042                                                     const void *Decoder) {
1043   if (RegNo > 7)
1044     return MCDisassembler::Fail;
1045   unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1046   Inst.addOperand(MCOperand::createReg(Reg));
1047   return MCDisassembler::Success;
1048 }
1049
1050 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1051                                              unsigned RegNo,
1052                                              uint64_t Address,
1053                                              const void *Decoder) {
1054   if (RegNo > 31)
1055     return MCDisassembler::Fail;
1056   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1057   Inst.addOperand(MCOperand::createReg(Reg));
1058   return MCDisassembler::Success;
1059 }
1060
1061 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1062                                            unsigned RegNo,
1063                                            uint64_t Address,
1064                                            const void *Decoder) {
1065   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1066     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1067
1068   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1069 }
1070
1071 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1072                                             unsigned RegNo,
1073                                             uint64_t Address,
1074                                             const void *Decoder) {
1075   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1076 }
1077
1078 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1079                                              unsigned RegNo,
1080                                              uint64_t Address,
1081                                              const void *Decoder) {
1082   if (RegNo > 31)
1083     return MCDisassembler::Fail;
1084
1085   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1086   Inst.addOperand(MCOperand::createReg(Reg));
1087   return MCDisassembler::Success;
1088 }
1089
1090 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1091                                              unsigned RegNo,
1092                                              uint64_t Address,
1093                                              const void *Decoder) {
1094   if (RegNo > 31)
1095     return MCDisassembler::Fail;
1096
1097   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1098   Inst.addOperand(MCOperand::createReg(Reg));
1099   return MCDisassembler::Success;
1100 }
1101
1102 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1103                                            unsigned RegNo,
1104                                            uint64_t Address,
1105                                            const void *Decoder) {
1106   if (RegNo > 31)
1107     return MCDisassembler::Fail;
1108   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1109   Inst.addOperand(MCOperand::createReg(Reg));
1110   return MCDisassembler::Success;
1111 }
1112
1113 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1114                                            unsigned RegNo,
1115                                            uint64_t Address,
1116                                            const void *Decoder) {
1117   if (RegNo > 7)
1118     return MCDisassembler::Fail;
1119   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1120   Inst.addOperand(MCOperand::createReg(Reg));
1121   return MCDisassembler::Success;
1122 }
1123
1124 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1125                                              uint64_t Address,
1126                                              const void *Decoder) {
1127   if (RegNo > 31)
1128     return MCDisassembler::Fail;
1129
1130   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1131   Inst.addOperand(MCOperand::createReg(Reg));
1132   return MCDisassembler::Success;
1133 }
1134
1135 static DecodeStatus DecodeMem(MCInst &Inst,
1136                               unsigned Insn,
1137                               uint64_t Address,
1138                               const void *Decoder) {
1139   int Offset = SignExtend32<16>(Insn & 0xffff);
1140   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1141   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1142
1143   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1144   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1145
1146   if (Inst.getOpcode() == Mips::SC ||
1147       Inst.getOpcode() == Mips::SCD)
1148     Inst.addOperand(MCOperand::createReg(Reg));
1149
1150   Inst.addOperand(MCOperand::createReg(Reg));
1151   Inst.addOperand(MCOperand::createReg(Base));
1152   Inst.addOperand(MCOperand::createImm(Offset));
1153
1154   return MCDisassembler::Success;
1155 }
1156
1157 static DecodeStatus DecodeMemEVA(MCInst &Inst,
1158                                  unsigned Insn,
1159                                  uint64_t Address,
1160                                  const void *Decoder) {
1161   int Offset = SignExtend32<9>(Insn >> 7);
1162   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1163   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1164
1165   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1166   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1167
1168    if (Inst.getOpcode() == Mips::SCE)
1169      Inst.addOperand(MCOperand::createReg(Reg));
1170
1171   Inst.addOperand(MCOperand::createReg(Reg));
1172   Inst.addOperand(MCOperand::createReg(Base));
1173   Inst.addOperand(MCOperand::createImm(Offset));
1174
1175   return MCDisassembler::Success;
1176 }
1177
1178 static DecodeStatus DecodeLoadByte9(MCInst &Inst,
1179                                     unsigned Insn,
1180                                     uint64_t Address,
1181                                     const void *Decoder) {
1182   int Offset = SignExtend32<9>(Insn & 0x1ff);
1183   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1184   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1185
1186   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1187   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1188
1189   Inst.addOperand(MCOperand::createReg(Reg));
1190   Inst.addOperand(MCOperand::createReg(Base));
1191   Inst.addOperand(MCOperand::createImm(Offset));
1192
1193   return MCDisassembler::Success;
1194 }
1195
1196 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
1197                                      unsigned Insn,
1198                                      uint64_t Address,
1199                                      const void *Decoder) {
1200   int Offset = SignExtend32<16>(Insn & 0xffff);
1201   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1202   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1203
1204   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1205   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1206
1207   Inst.addOperand(MCOperand::createReg(Reg));
1208   Inst.addOperand(MCOperand::createReg(Base));
1209   Inst.addOperand(MCOperand::createImm(Offset));
1210
1211   return MCDisassembler::Success;
1212 }
1213
1214 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1215                               unsigned Insn,
1216                               uint64_t Address,
1217                               const void *Decoder) {
1218   int Offset = SignExtend32<16>(Insn & 0xffff);
1219   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1220   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1221
1222   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1223
1224   Inst.addOperand(MCOperand::createReg(Base));
1225   Inst.addOperand(MCOperand::createImm(Offset));
1226   Inst.addOperand(MCOperand::createImm(Hint));
1227
1228   return MCDisassembler::Success;
1229 }
1230
1231 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1232                                     unsigned Insn,
1233                                     uint64_t Address,
1234                                     const void *Decoder) {
1235   int Offset = SignExtend32<12>(Insn & 0xfff);
1236   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1237   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1238
1239   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1240
1241   Inst.addOperand(MCOperand::createReg(Base));
1242   Inst.addOperand(MCOperand::createImm(Offset));
1243   Inst.addOperand(MCOperand::createImm(Hint));
1244
1245   return MCDisassembler::Success;
1246 }
1247
1248 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
1249                                     unsigned Insn,
1250                                     uint64_t Address,
1251                                     const void *Decoder) {
1252   int Offset = SignExtend32<9>(Insn & 0x1ff);
1253   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1254   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1255
1256   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1257
1258   Inst.addOperand(MCOperand::createReg(Base));
1259   Inst.addOperand(MCOperand::createImm(Offset));
1260   Inst.addOperand(MCOperand::createImm(Hint));
1261
1262   return MCDisassembler::Success;
1263 }
1264
1265 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
1266                                              unsigned Insn,
1267                                              uint64_t Address,
1268                                              const void *Decoder) {
1269   int Offset = SignExtend32<9>(Insn >> 7);
1270   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1271   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1272
1273   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1274
1275   Inst.addOperand(MCOperand::createReg(Base));
1276   Inst.addOperand(MCOperand::createImm(Offset));
1277   Inst.addOperand(MCOperand::createImm(Hint));
1278
1279   return MCDisassembler::Success;
1280 }
1281
1282 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
1283                                        unsigned Insn,
1284                                        uint64_t Address,
1285                                        const void *Decoder) {
1286   int Offset = SignExtend32<9>(Insn & 0x1ff);
1287   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1288   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1289
1290   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1291   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1292
1293   Inst.addOperand(MCOperand::createReg(Reg));
1294   Inst.addOperand(MCOperand::createReg(Base));
1295   Inst.addOperand(MCOperand::createImm(Offset));
1296
1297   return MCDisassembler::Success;
1298 }
1299
1300 static DecodeStatus DecodeSyncI(MCInst &Inst,
1301                               unsigned Insn,
1302                               uint64_t Address,
1303                               const void *Decoder) {
1304   int Offset = SignExtend32<16>(Insn & 0xffff);
1305   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1306
1307   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1308
1309   Inst.addOperand(MCOperand::createReg(Base));
1310   Inst.addOperand(MCOperand::createImm(Offset));
1311
1312   return MCDisassembler::Success;
1313 }
1314
1315 static DecodeStatus DecodeSynciR6(MCInst &Inst,
1316                                   unsigned Insn,
1317                                   uint64_t Address,
1318                                   const void *Decoder) {
1319   int Immediate = SignExtend32<16>(Insn & 0xffff);
1320   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1321
1322   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1323
1324   Inst.addOperand(MCOperand::createReg(Base));
1325   Inst.addOperand(MCOperand::createImm(Immediate));
1326
1327   return MCDisassembler::Success;
1328 }
1329
1330 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1331                                     uint64_t Address, const void *Decoder) {
1332   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1333   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1334   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1335
1336   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1337   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1338
1339   Inst.addOperand(MCOperand::createReg(Reg));
1340   Inst.addOperand(MCOperand::createReg(Base));
1341
1342   // The immediate field of an LD/ST instruction is scaled which means it must
1343   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1344   // data format.
1345   // .b - 1 byte
1346   // .h - 2 bytes
1347   // .w - 4 bytes
1348   // .d - 8 bytes
1349   switch(Inst.getOpcode())
1350   {
1351   default:
1352     assert (0 && "Unexpected instruction");
1353     return MCDisassembler::Fail;
1354     break;
1355   case Mips::LD_B:
1356   case Mips::ST_B:
1357     Inst.addOperand(MCOperand::createImm(Offset));
1358     break;
1359   case Mips::LD_H:
1360   case Mips::ST_H:
1361     Inst.addOperand(MCOperand::createImm(Offset * 2));
1362     break;
1363   case Mips::LD_W:
1364   case Mips::ST_W:
1365     Inst.addOperand(MCOperand::createImm(Offset * 4));
1366     break;
1367   case Mips::LD_D:
1368   case Mips::ST_D:
1369     Inst.addOperand(MCOperand::createImm(Offset * 8));
1370     break;
1371   }
1372
1373   return MCDisassembler::Success;
1374 }
1375
1376 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1377                                     unsigned Insn,
1378                                     uint64_t Address,
1379                                     const void *Decoder) {
1380   unsigned Offset = Insn & 0xf;
1381   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1382   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1383
1384   switch (Inst.getOpcode()) {
1385     case Mips::LBU16_MM:
1386     case Mips::LHU16_MM:
1387     case Mips::LW16_MM:
1388       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1389             == MCDisassembler::Fail)
1390         return MCDisassembler::Fail;
1391       break;
1392     case Mips::SB16_MM:
1393     case Mips::SB16_MMR6:
1394     case Mips::SH16_MM:
1395     case Mips::SH16_MMR6:
1396     case Mips::SW16_MM:
1397     case Mips::SW16_MMR6:
1398       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1399             == MCDisassembler::Fail)
1400         return MCDisassembler::Fail;
1401       break;
1402   }
1403
1404   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1405         == MCDisassembler::Fail)
1406     return MCDisassembler::Fail;
1407
1408   switch (Inst.getOpcode()) {
1409     case Mips::LBU16_MM:
1410       if (Offset == 0xf)
1411         Inst.addOperand(MCOperand::createImm(-1));
1412       else
1413         Inst.addOperand(MCOperand::createImm(Offset));
1414       break;
1415     case Mips::SB16_MM:
1416     case Mips::SB16_MMR6:
1417       Inst.addOperand(MCOperand::createImm(Offset));
1418       break;
1419     case Mips::LHU16_MM:
1420     case Mips::SH16_MM:
1421     case Mips::SH16_MMR6:
1422       Inst.addOperand(MCOperand::createImm(Offset << 1));
1423       break;
1424     case Mips::LW16_MM:
1425     case Mips::SW16_MM:
1426     case Mips::SW16_MMR6:
1427       Inst.addOperand(MCOperand::createImm(Offset << 2));
1428       break;
1429   }
1430
1431   return MCDisassembler::Success;
1432 }
1433
1434 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1435                                           unsigned Insn,
1436                                           uint64_t Address,
1437                                           const void *Decoder) {
1438   unsigned Offset = Insn & 0x1F;
1439   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1440
1441   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1442
1443   Inst.addOperand(MCOperand::createReg(Reg));
1444   Inst.addOperand(MCOperand::createReg(Mips::SP));
1445   Inst.addOperand(MCOperand::createImm(Offset << 2));
1446
1447   return MCDisassembler::Success;
1448 }
1449
1450 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1451                                           unsigned Insn,
1452                                           uint64_t Address,
1453                                           const void *Decoder) {
1454   unsigned Offset = Insn & 0x7F;
1455   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1456
1457   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1458
1459   Inst.addOperand(MCOperand::createReg(Reg));
1460   Inst.addOperand(MCOperand::createReg(Mips::GP));
1461   Inst.addOperand(MCOperand::createImm(Offset << 2));
1462
1463   return MCDisassembler::Success;
1464 }
1465
1466 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1467                                                unsigned Insn,
1468                                                uint64_t Address,
1469                                                const void *Decoder) {
1470   int Offset;
1471   switch (Inst.getOpcode()) {
1472   case Mips::LWM16_MMR6:
1473   case Mips::SWM16_MMR6:
1474     Offset = fieldFromInstruction(Insn, 4, 4);
1475     break;
1476   default:
1477     Offset = SignExtend32<4>(Insn & 0xf);
1478     break;
1479   }
1480
1481   if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1482       == MCDisassembler::Fail)
1483     return MCDisassembler::Fail;
1484
1485   Inst.addOperand(MCOperand::createReg(Mips::SP));
1486   Inst.addOperand(MCOperand::createImm(Offset << 2));
1487
1488   return MCDisassembler::Success;
1489 }
1490
1491 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1492                                     unsigned Insn,
1493                                     uint64_t Address,
1494                                     const void *Decoder) {
1495   int Offset = SignExtend32<9>(Insn & 0x1ff);
1496   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1497   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1498
1499   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1500   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1501
1502   if (Inst.getOpcode() == Mips::SCE_MM)
1503     Inst.addOperand(MCOperand::createReg(Reg));
1504
1505   Inst.addOperand(MCOperand::createReg(Reg));
1506   Inst.addOperand(MCOperand::createReg(Base));
1507   Inst.addOperand(MCOperand::createImm(Offset));
1508
1509   return MCDisassembler::Success;
1510 }
1511
1512 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1513                                      unsigned Insn,
1514                                      uint64_t Address,
1515                                      const void *Decoder) {
1516   int Offset = SignExtend32<12>(Insn & 0x0fff);
1517   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1518   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1519
1520   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1521   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1522
1523   switch (Inst.getOpcode()) {
1524   case Mips::SWM32_MM:
1525   case Mips::LWM32_MM:
1526     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1527         == MCDisassembler::Fail)
1528       return MCDisassembler::Fail;
1529     Inst.addOperand(MCOperand::createReg(Base));
1530     Inst.addOperand(MCOperand::createImm(Offset));
1531     break;
1532   case Mips::SC_MM:
1533     Inst.addOperand(MCOperand::createReg(Reg));
1534     // fallthrough
1535   default:
1536     Inst.addOperand(MCOperand::createReg(Reg));
1537     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1538       Inst.addOperand(MCOperand::createReg(Reg+1));
1539
1540     Inst.addOperand(MCOperand::createReg(Base));
1541     Inst.addOperand(MCOperand::createImm(Offset));
1542   }
1543
1544   return MCDisassembler::Success;
1545 }
1546
1547 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1548                                      unsigned Insn,
1549                                      uint64_t Address,
1550                                      const void *Decoder) {
1551   int Offset = SignExtend32<16>(Insn & 0xffff);
1552   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1553   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1554
1555   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1556   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1557
1558   Inst.addOperand(MCOperand::createReg(Reg));
1559   Inst.addOperand(MCOperand::createReg(Base));
1560   Inst.addOperand(MCOperand::createImm(Offset));
1561
1562   return MCDisassembler::Success;
1563 }
1564
1565 static DecodeStatus DecodeFMem(MCInst &Inst,
1566                                unsigned Insn,
1567                                uint64_t Address,
1568                                const void *Decoder) {
1569   int Offset = SignExtend32<16>(Insn & 0xffff);
1570   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1571   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1572
1573   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1574   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1575
1576   Inst.addOperand(MCOperand::createReg(Reg));
1577   Inst.addOperand(MCOperand::createReg(Base));
1578   Inst.addOperand(MCOperand::createImm(Offset));
1579
1580   return MCDisassembler::Success;
1581 }
1582
1583 static DecodeStatus DecodeFMem2(MCInst &Inst,
1584                                unsigned Insn,
1585                                uint64_t Address,
1586                                const void *Decoder) {
1587   int Offset = SignExtend32<16>(Insn & 0xffff);
1588   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1589   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1590
1591   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1592   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1593
1594   Inst.addOperand(MCOperand::createReg(Reg));
1595   Inst.addOperand(MCOperand::createReg(Base));
1596   Inst.addOperand(MCOperand::createImm(Offset));
1597
1598   return MCDisassembler::Success;
1599 }
1600
1601 static DecodeStatus DecodeFMem3(MCInst &Inst,
1602                                unsigned Insn,
1603                                uint64_t Address,
1604                                const void *Decoder) {
1605   int Offset = SignExtend32<16>(Insn & 0xffff);
1606   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1607   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1608
1609   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1610   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1611
1612   Inst.addOperand(MCOperand::createReg(Reg));
1613   Inst.addOperand(MCOperand::createReg(Base));
1614   Inst.addOperand(MCOperand::createImm(Offset));
1615
1616   return MCDisassembler::Success;
1617 }
1618
1619 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1620                                     unsigned Insn,
1621                                     uint64_t Address,
1622                                     const void *Decoder) {
1623   int Offset = SignExtend32<11>(Insn & 0x07ff);
1624   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1625   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1626
1627   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1628   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1629
1630   Inst.addOperand(MCOperand::createReg(Reg));
1631   Inst.addOperand(MCOperand::createReg(Base));
1632   Inst.addOperand(MCOperand::createImm(Offset));
1633
1634   return MCDisassembler::Success;
1635 }
1636 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1637                                        unsigned Insn,
1638                                        uint64_t Address,
1639                                        const void *Decoder) {
1640   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1641   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1642   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1643
1644   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1645   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1646
1647   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1648     Inst.addOperand(MCOperand::createReg(Rt));
1649   }
1650
1651   Inst.addOperand(MCOperand::createReg(Rt));
1652   Inst.addOperand(MCOperand::createReg(Base));
1653   Inst.addOperand(MCOperand::createImm(Offset));
1654
1655   return MCDisassembler::Success;
1656 }
1657
1658 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1659                                               unsigned RegNo,
1660                                               uint64_t Address,
1661                                               const void *Decoder) {
1662   // Currently only hardware register 29 is supported.
1663   if (RegNo != 29)
1664     return  MCDisassembler::Fail;
1665   Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1666   return MCDisassembler::Success;
1667 }
1668
1669 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1670                                               unsigned RegNo,
1671                                               uint64_t Address,
1672                                               const void *Decoder) {
1673   if (RegNo > 30 || RegNo %2)
1674     return MCDisassembler::Fail;
1675
1676   ;
1677   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1678   Inst.addOperand(MCOperand::createReg(Reg));
1679   return MCDisassembler::Success;
1680 }
1681
1682 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1683                                                 unsigned RegNo,
1684                                                 uint64_t Address,
1685                                                 const void *Decoder) {
1686   if (RegNo >= 4)
1687     return MCDisassembler::Fail;
1688
1689   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1690   Inst.addOperand(MCOperand::createReg(Reg));
1691   return MCDisassembler::Success;
1692 }
1693
1694 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1695                                                unsigned RegNo,
1696                                                uint64_t Address,
1697                                                const void *Decoder) {
1698   if (RegNo >= 4)
1699     return MCDisassembler::Fail;
1700
1701   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1702   Inst.addOperand(MCOperand::createReg(Reg));
1703   return MCDisassembler::Success;
1704 }
1705
1706 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1707                                                unsigned RegNo,
1708                                                uint64_t Address,
1709                                                const void *Decoder) {
1710   if (RegNo >= 4)
1711     return MCDisassembler::Fail;
1712
1713   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1714   Inst.addOperand(MCOperand::createReg(Reg));
1715   return MCDisassembler::Success;
1716 }
1717
1718 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1719                                                unsigned RegNo,
1720                                                uint64_t Address,
1721                                                const void *Decoder) {
1722   if (RegNo > 31)
1723     return MCDisassembler::Fail;
1724
1725   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1726   Inst.addOperand(MCOperand::createReg(Reg));
1727   return MCDisassembler::Success;
1728 }
1729
1730 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1731                                                unsigned RegNo,
1732                                                uint64_t Address,
1733                                                const void *Decoder) {
1734   if (RegNo > 31)
1735     return MCDisassembler::Fail;
1736
1737   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1738   Inst.addOperand(MCOperand::createReg(Reg));
1739   return MCDisassembler::Success;
1740 }
1741
1742 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1743                                                unsigned RegNo,
1744                                                uint64_t Address,
1745                                                const void *Decoder) {
1746   if (RegNo > 31)
1747     return MCDisassembler::Fail;
1748
1749   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1750   Inst.addOperand(MCOperand::createReg(Reg));
1751   return MCDisassembler::Success;
1752 }
1753
1754 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1755                                                unsigned RegNo,
1756                                                uint64_t Address,
1757                                                const void *Decoder) {
1758   if (RegNo > 31)
1759     return MCDisassembler::Fail;
1760
1761   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1762   Inst.addOperand(MCOperand::createReg(Reg));
1763   return MCDisassembler::Success;
1764 }
1765
1766 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1767                                                unsigned RegNo,
1768                                                uint64_t Address,
1769                                                const void *Decoder) {
1770   if (RegNo > 7)
1771     return MCDisassembler::Fail;
1772
1773   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1774   Inst.addOperand(MCOperand::createReg(Reg));
1775   return MCDisassembler::Success;
1776 }
1777
1778 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
1779                                             unsigned RegNo,
1780                                             uint64_t Address,
1781                                             const void *Decoder) {
1782   if (RegNo > 31)
1783     return MCDisassembler::Fail;
1784
1785   unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
1786   Inst.addOperand(MCOperand::createReg(Reg));
1787   return MCDisassembler::Success;
1788 }
1789
1790 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1791                                             unsigned RegNo,
1792                                             uint64_t Address,
1793                                             const void *Decoder) {
1794   if (RegNo > 31)
1795     return MCDisassembler::Fail;
1796
1797   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1798   Inst.addOperand(MCOperand::createReg(Reg));
1799   return MCDisassembler::Success;
1800 }
1801
1802 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1803                                        unsigned Offset,
1804                                        uint64_t Address,
1805                                        const void *Decoder) {
1806   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1807   Inst.addOperand(MCOperand::createImm(BranchOffset));
1808   return MCDisassembler::Success;
1809 }
1810
1811 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1812                                      unsigned Insn,
1813                                      uint64_t Address,
1814                                      const void *Decoder) {
1815
1816   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1817   Inst.addOperand(MCOperand::createImm(JumpOffset));
1818   return MCDisassembler::Success;
1819 }
1820
1821 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1822                                          unsigned Offset,
1823                                          uint64_t Address,
1824                                          const void *Decoder) {
1825   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1826
1827   Inst.addOperand(MCOperand::createImm(BranchOffset));
1828   return MCDisassembler::Success;
1829 }
1830
1831 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1832                                          unsigned Offset,
1833                                          uint64_t Address,
1834                                          const void *Decoder) {
1835   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1836
1837   Inst.addOperand(MCOperand::createImm(BranchOffset));
1838   return MCDisassembler::Success;
1839 }
1840
1841 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1842                                           unsigned Offset,
1843                                           uint64_t Address,
1844                                           const void *Decoder) {
1845   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1846   Inst.addOperand(MCOperand::createImm(BranchOffset));
1847   return MCDisassembler::Success;
1848 }
1849
1850 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1851                                            unsigned Offset,
1852                                            uint64_t Address,
1853                                            const void *Decoder) {
1854   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1855   Inst.addOperand(MCOperand::createImm(BranchOffset));
1856   return MCDisassembler::Success;
1857 }
1858
1859 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1860                                          unsigned Offset,
1861                                          uint64_t Address,
1862                                          const void *Decoder) {
1863   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1864   Inst.addOperand(MCOperand::createImm(BranchOffset));
1865   return MCDisassembler::Success;
1866 }
1867
1868 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
1869   unsigned Offset,
1870   uint64_t Address,
1871   const void *Decoder) {
1872   int32_t BranchOffset = SignExtend32<26>(Offset) << 1;
1873
1874   Inst.addOperand(MCOperand::createImm(BranchOffset));
1875   return MCDisassembler::Success;
1876 }
1877
1878 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1879                                        unsigned Insn,
1880                                        uint64_t Address,
1881                                        const void *Decoder) {
1882   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1883   Inst.addOperand(MCOperand::createImm(JumpOffset));
1884   return MCDisassembler::Success;
1885 }
1886
1887 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1888                                        unsigned Value,
1889                                        uint64_t Address,
1890                                        const void *Decoder) {
1891   if (Value == 0)
1892     Inst.addOperand(MCOperand::createImm(1));
1893   else if (Value == 0x7)
1894     Inst.addOperand(MCOperand::createImm(-1));
1895   else
1896     Inst.addOperand(MCOperand::createImm(Value << 2));
1897   return MCDisassembler::Success;
1898 }
1899
1900 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1901                                     unsigned Value,
1902                                     uint64_t Address,
1903                                     const void *Decoder) {
1904   Inst.addOperand(MCOperand::createImm(Value << 2));
1905   return MCDisassembler::Success;
1906 }
1907
1908 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1909                                   unsigned Value,
1910                                   uint64_t Address,
1911                                   const void *Decoder) {
1912   if (Value == 0x7F)
1913     Inst.addOperand(MCOperand::createImm(-1));
1914   else
1915     Inst.addOperand(MCOperand::createImm(Value));
1916   return MCDisassembler::Success;
1917 }
1918
1919 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
1920                                               unsigned Value,
1921                                               uint64_t Address,
1922                                               const void *Decoder) {
1923   Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
1924   return MCDisassembler::Success;
1925 }
1926
1927 static DecodeStatus DecodeSimm4(MCInst &Inst,
1928                                 unsigned Value,
1929                                 uint64_t Address,
1930                                 const void *Decoder) {
1931   Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1932   return MCDisassembler::Success;
1933 }
1934
1935 static DecodeStatus DecodeSimm16(MCInst &Inst,
1936                                  unsigned Insn,
1937                                  uint64_t Address,
1938                                  const void *Decoder) {
1939   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1940   return MCDisassembler::Success;
1941 }
1942
1943 template <unsigned Bits, int Offset>
1944 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
1945                                          uint64_t Address,
1946                                          const void *Decoder) {
1947   Value &= ((1 << Bits) - 1);
1948   Inst.addOperand(MCOperand::createImm(Value + Offset));
1949   return MCDisassembler::Success;
1950 }
1951
1952 static DecodeStatus DecodeInsSize(MCInst &Inst,
1953                                   unsigned Insn,
1954                                   uint64_t Address,
1955                                   const void *Decoder) {
1956   // First we need to grab the pos(lsb) from MCInst.
1957   int Pos = Inst.getOperand(2).getImm();
1958   int Size = (int) Insn - Pos + 1;
1959   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1960   return MCDisassembler::Success;
1961 }
1962
1963 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1964                                      uint64_t Address, const void *Decoder) {
1965   Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1966   return MCDisassembler::Success;
1967 }
1968
1969 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1970                                      uint64_t Address, const void *Decoder) {
1971   Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1972   return MCDisassembler::Success;
1973 }
1974
1975 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1976                                   uint64_t Address, const void *Decoder) {
1977   int32_t DecodedValue;
1978   switch (Insn) {
1979   case 0: DecodedValue = 256; break;
1980   case 1: DecodedValue = 257; break;
1981   case 510: DecodedValue = -258; break;
1982   case 511: DecodedValue = -257; break;
1983   default: DecodedValue = SignExtend32<9>(Insn); break;
1984   }
1985   Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1986   return MCDisassembler::Success;
1987 }
1988
1989 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1990                                     uint64_t Address, const void *Decoder) {
1991   // Insn must be >= 0, since it is unsigned that condition is always true.
1992   assert(Insn < 16);
1993   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1994                              255, 32768, 65535};
1995   Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1996   return MCDisassembler::Success;
1997 }
1998
1999 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
2000                                     uint64_t Address, const void *Decoder) {
2001   Inst.addOperand(MCOperand::createImm(Insn << 2));
2002   return MCDisassembler::Success;
2003 }
2004
2005 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
2006                                          unsigned Insn,
2007                                          uint64_t Address,
2008                                          const void *Decoder) {
2009   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2010                      Mips::S6, Mips::S7, Mips::FP};
2011   unsigned RegNum;
2012
2013   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2014
2015   // Empty register lists are not allowed.
2016   if (RegLst == 0)
2017     return MCDisassembler::Fail;
2018
2019   RegNum = RegLst & 0xf;
2020
2021   // RegLst values 10-15, and 26-31 are reserved.
2022   if (RegNum > 9)
2023     return MCDisassembler::Fail;
2024
2025   for (unsigned i = 0; i < RegNum; i++)
2026     Inst.addOperand(MCOperand::createReg(Regs[i]));
2027
2028   if (RegLst & 0x10)
2029     Inst.addOperand(MCOperand::createReg(Mips::RA));
2030
2031   return MCDisassembler::Success;
2032 }
2033
2034 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2035                                            uint64_t Address,
2036                                            const void *Decoder) {
2037   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2038   unsigned RegLst;
2039   switch(Inst.getOpcode()) {
2040   default:
2041     RegLst = fieldFromInstruction(Insn, 4, 2);
2042     break;
2043   case Mips::LWM16_MMR6:
2044   case Mips::SWM16_MMR6:
2045     RegLst = fieldFromInstruction(Insn, 8, 2);
2046     break;
2047   }
2048   unsigned RegNum = RegLst & 0x3;
2049
2050   for (unsigned i = 0; i <= RegNum; i++)
2051     Inst.addOperand(MCOperand::createReg(Regs[i]));
2052
2053   Inst.addOperand(MCOperand::createReg(Mips::RA));
2054
2055   return MCDisassembler::Success;
2056 }
2057
2058 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
2059                                        uint64_t Address, const void *Decoder) {
2060
2061   unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2062
2063   switch (RegPair) {
2064   default:
2065     return MCDisassembler::Fail;
2066   case 0:
2067     Inst.addOperand(MCOperand::createReg(Mips::A1));
2068     Inst.addOperand(MCOperand::createReg(Mips::A2));
2069     break;
2070   case 1:
2071     Inst.addOperand(MCOperand::createReg(Mips::A1));
2072     Inst.addOperand(MCOperand::createReg(Mips::A3));
2073     break;
2074   case 2:
2075     Inst.addOperand(MCOperand::createReg(Mips::A2));
2076     Inst.addOperand(MCOperand::createReg(Mips::A3));
2077     break;
2078   case 3:
2079     Inst.addOperand(MCOperand::createReg(Mips::A0));
2080     Inst.addOperand(MCOperand::createReg(Mips::S5));
2081     break;
2082   case 4:
2083     Inst.addOperand(MCOperand::createReg(Mips::A0));
2084     Inst.addOperand(MCOperand::createReg(Mips::S6));
2085     break;
2086   case 5:
2087     Inst.addOperand(MCOperand::createReg(Mips::A0));
2088     Inst.addOperand(MCOperand::createReg(Mips::A1));
2089     break;
2090   case 6:
2091     Inst.addOperand(MCOperand::createReg(Mips::A0));
2092     Inst.addOperand(MCOperand::createReg(Mips::A2));
2093     break;
2094   case 7:
2095     Inst.addOperand(MCOperand::createReg(Mips::A0));
2096     Inst.addOperand(MCOperand::createReg(Mips::A3));
2097     break;
2098   }
2099
2100   return MCDisassembler::Success;
2101 }
2102
2103 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2104                                      uint64_t Address, const void *Decoder) {
2105   Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2106   return MCDisassembler::Success;
2107 }