lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// A disassembler class for Mips.
  34 class MipsDisassemblerBase : public MCDisassembler {
  35 public:
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  37                        bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   virtual ~MipsDisassemblerBase() {}
  43
  44   bool isGP64Bit() const { return IsGP64Bit; }
  45
  46 private:
  47   bool IsGP64Bit;
  48 protected:
  49   bool IsBigEndian;
  50 };
  51
  52 /// A disassembler class for Mips32.
  53 class MipsDisassembler : public MipsDisassemblerBase {
  54   bool IsMicroMips;
  55 public:
  56   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  57       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  58     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  59   }
  60
  61   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  62   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  63   bool hasMips32r6() const {
  64     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  65   }
  66
  67   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  68
  69   bool hasCOP3() const {
  70     // Only present in MIPS-I and MIPS-II
  71     return !hasMips32() && !hasMips3();
  72   }
  73
  74   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  75                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  76                               raw_ostream &VStream,
  77                               raw_ostream &CStream) const override;
  78 };
  79
  80 /// A disassembler class for Mips64.
  81 class Mips64Disassembler : public MipsDisassemblerBase {
  82 public:
  83   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  84                      bool bigEndian) :
  85     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  86
  87   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  88                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  89                               raw_ostream &VStream,
  90                               raw_ostream &CStream) const override;
  91 };
  92
  93 } // end anonymous namespace
  94
  95 // Forward declare these because the autogenerated code will reference them.
  96 // Definitions are further down.
  97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  98                                              unsigned RegNo,
  99                                              uint64_t Address,
 100                                              const void *Decoder);
 101
 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 103                                                  unsigned RegNo,
 104                                                  uint64_t Address,
 105                                                  const void *Decoder);
 106
 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 108                                                unsigned RegNo,
 109                                                uint64_t Address,
 110                                                const void *Decoder);
 111
 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 113                                                    unsigned RegNo,
 114                                                    uint64_t Address,
 115                                                    const void *Decoder);
 116
 117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 118                                              unsigned RegNo,
 119                                              uint64_t Address,
 120                                              const void *Decoder);
 121
 122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 123                                            unsigned Insn,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 128                                             unsigned RegNo,
 129                                             uint64_t Address,
 130                                             const void *Decoder);
 131
 132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 133                                              unsigned RegNo,
 134                                              uint64_t Address,
 135                                              const void *Decoder);
 136
 137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 138                                              unsigned RegNo,
 139                                              uint64_t Address,
 140                                              const void *Decoder);
 141
 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 143                                            unsigned RegNo,
 144                                            uint64_t Address,
 145                                            const void *Decoder);
 146
 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 148                                            unsigned RegNo,
 149                                            uint64_t Address,
 150                                            const void *Decoder);
 151
 152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 153                                              uint64_t Address,
 154                                              const void *Decoder);
 155
 156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 157                                               unsigned Insn,
 158                                               uint64_t Address,
 159                                               const void *Decoder);
 160
 161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 162                                               unsigned RegNo,
 163                                               uint64_t Address,
 164                                               const void *Decoder);
 165
 166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 167                                                 unsigned RegNo,
 168                                                 uint64_t Address,
 169                                                 const void *Decoder);
 170
 171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 182                                                unsigned RegNo,
 183                                                uint64_t Address,
 184                                                const void *Decoder);
 185
 186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 187                                                unsigned RegNo,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 192                                                unsigned RegNo,
 193                                                uint64_t Address,
 194                                                const void *Decoder);
 195
 196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 197                                                unsigned RegNo,
 198                                                uint64_t Address,
 199                                                const void *Decoder);
 200
 201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 202                                                unsigned RegNo,
 203                                                uint64_t Address,
 204                                                const void *Decoder);
 205
 206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 207                                             unsigned RegNo,
 208                                             uint64_t Address,
 209                                             const void *Decoder);
 210
 211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 212                                        unsigned Offset,
 213                                        uint64_t Address,
 214                                        const void *Decoder);
 215
 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 217                                      unsigned Insn,
 218                                      uint64_t Address,
 219                                      const void *Decoder);
 220
 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 222                                          unsigned Offset,
 223                                          uint64_t Address,
 224                                          const void *Decoder);
 225
 226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 227                                          unsigned Offset,
 228                                          uint64_t Address,
 229                                          const void *Decoder);
 230
 231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 232 // shifted left by 1 bit.
 233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 234                                           unsigned Offset,
 235                                           uint64_t Address,
 236                                           const void *Decoder);
 237
 238 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 239 // shifted left by 1 bit.
 240 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 241                                            unsigned Offset,
 242                                            uint64_t Address,
 243                                            const void *Decoder);
 244
 245 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 246 // shifted left by 1 bit.
 247 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 248                                          unsigned Offset,
 249                                          uint64_t Address,
 250                                          const void *Decoder);
 251
 252 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 253 // shifted left by 1 bit.
 254 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 255                                        unsigned Insn,
 256                                        uint64_t Address,
 257                                        const void *Decoder);
 258
 259 static DecodeStatus DecodeMem(MCInst &Inst,
 260                               unsigned Insn,
 261                               uint64_t Address,
 262                               const void *Decoder);
 263
 264 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 265                               unsigned Insn,
 266                               uint64_t Address,
 267                               const void *Decoder);
 268
 269 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
 270                                     unsigned Insn,
 271                                     uint64_t Address,
 272                                     const void *Decoder);
 273
 274 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 275                                     unsigned Insn,
 276                                     uint64_t Address,
 277                                     const void *Decoder);
 278
 279 static DecodeStatus DecodeSyncI(MCInst &Inst,
 280                                 unsigned Insn,
 281                                 uint64_t Address,
 282                                 const void *Decoder);
 283
 284 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 285                                     uint64_t Address, const void *Decoder);
 286
 287 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 288                                     unsigned Insn,
 289                                     uint64_t Address,
 290                                     const void *Decoder);
 291
 292 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 293                                           unsigned Insn,
 294                                           uint64_t Address,
 295                                           const void *Decoder);
 296
 297 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 298                                           unsigned Insn,
 299                                           uint64_t Address,
 300                                           const void *Decoder);
 301
 302 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
 303                                                unsigned Insn,
 304                                                uint64_t Address,
 305                                                const void *Decoder);
 306
 307 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 308                                      unsigned Insn,
 309                                      uint64_t Address,
 310                                      const void *Decoder);
 311
 312 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 313                                      unsigned Insn,
 314                                      uint64_t Address,
 315                                      const void *Decoder);
 316
 317 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 318                                uint64_t Address,
 319                                const void *Decoder);
 320
 321 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 322                                uint64_t Address,
 323                                const void *Decoder);
 324
 325 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 326                                uint64_t Address,
 327                                const void *Decoder);
 328
 329 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 330                                uint64_t Address,
 331                                const void *Decoder);
 332
 333 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 334                                        unsigned Insn,
 335                                        uint64_t Address,
 336                                        const void *Decoder);
 337
 338 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 339                                        unsigned Value,
 340                                        uint64_t Address,
 341                                        const void *Decoder);
 342
 343 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 344                                     unsigned Value,
 345                                     uint64_t Address,
 346                                     const void *Decoder);
 347
 348 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 349                                   unsigned Value,
 350                                   uint64_t Address,
 351                                   const void *Decoder);
 352
 353 static DecodeStatus DecodeSimm4(MCInst &Inst,
 354                                 unsigned Value,
 355                                 uint64_t Address,
 356                                 const void *Decoder);
 357
 358 static DecodeStatus DecodeSimm16(MCInst &Inst,
 359                                  unsigned Insn,
 360                                  uint64_t Address,
 361                                  const void *Decoder);
 362
 363 // Decode the immediate field of an LSA instruction which
 364 // is off by one.
 365 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 366                                  unsigned Insn,
 367                                  uint64_t Address,
 368                                  const void *Decoder);
 369
 370 static DecodeStatus DecodeInsSize(MCInst &Inst,
 371                                   unsigned Insn,
 372                                   uint64_t Address,
 373                                   const void *Decoder);
 374
 375 static DecodeStatus DecodeExtSize(MCInst &Inst,
 376                                   unsigned Insn,
 377                                   uint64_t Address,
 378                                   const void *Decoder);
 379
 380 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 381                                      uint64_t Address, const void *Decoder);
 382
 383 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 384                                      uint64_t Address, const void *Decoder);
 385
 386 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 387                                   uint64_t Address, const void *Decoder);
 388
 389 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 390                                     uint64_t Address, const void *Decoder);
 391
 392 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 393                                    uint64_t Address, const void *Decoder);
 394
 395 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 396                                      uint64_t Address, const void *Decoder);
 397
 398 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 399 /// handle.
 400 template <typename InsnType>
 401 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 402                                    const void *Decoder);
 403
 404 template <typename InsnType>
 405 static DecodeStatus
 406 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 407                       const void *Decoder);
 408
 409 template <typename InsnType>
 410 static DecodeStatus
 411 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 412                        const void *Decoder);
 413
 414 template <typename InsnType>
 415 static DecodeStatus
 416 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 417                        const void *Decoder);
 418
 419 template <typename InsnType>
 420 static DecodeStatus
 421 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 422                        const void *Decoder);
 423
 424 template <typename InsnType>
 425 static DecodeStatus
 426 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 427                       const void *Decoder);
 428
 429 template <typename InsnType>
 430 static DecodeStatus
 431 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 432                        const void *Decoder);
 433
 434 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 435                                          uint64_t Address,
 436                                          const void *Decoder);
 437
 438 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 439                                            uint64_t Address,
 440                                            const void *Decoder);
 441
 442 namespace llvm {
 443 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 444               TheMips64elTarget;
 445 }
 446
 447 static MCDisassembler *createMipsDisassembler(
 448                        const Target &T,
 449                        const MCSubtargetInfo &STI,
 450                        MCContext &Ctx) {
 451   return new MipsDisassembler(STI, Ctx, true);
 452 }
 453
 454 static MCDisassembler *createMipselDisassembler(
 455                        const Target &T,
 456                        const MCSubtargetInfo &STI,
 457                        MCContext &Ctx) {
 458   return new MipsDisassembler(STI, Ctx, false);
 459 }
 460
 461 static MCDisassembler *createMips64Disassembler(
 462                        const Target &T,
 463                        const MCSubtargetInfo &STI,
 464                        MCContext &Ctx) {
 465   return new Mips64Disassembler(STI, Ctx, true);
 466 }
 467
 468 static MCDisassembler *createMips64elDisassembler(
 469                        const Target &T,
 470                        const MCSubtargetInfo &STI,
 471                        MCContext &Ctx) {
 472   return new Mips64Disassembler(STI, Ctx, false);
 473 }
 474
 475 extern "C" void LLVMInitializeMipsDisassembler() {
 476   // Register the disassembler.
 477   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 478                                          createMipsDisassembler);
 479   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 480                                          createMipselDisassembler);
 481   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 482                                          createMips64Disassembler);
 483   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 484                                          createMips64elDisassembler);
 485 }
 486
 487 #include "MipsGenDisassemblerTables.inc"
 488
 489 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 490   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 491   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 492   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 493 }
 494
 495 template <typename InsnType>
 496 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 497                                    const void *Decoder) {
 498   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 499   // The size of the n field depends on the element size
 500   // The register class also depends on this.
 501   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 502   unsigned NSize = 0;
 503   DecodeFN RegDecoder = nullptr;
 504   if ((tmp & 0x18) == 0x00) { // INSVE_B
 505     NSize = 4;
 506     RegDecoder = DecodeMSA128BRegisterClass;
 507   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 508     NSize = 3;
 509     RegDecoder = DecodeMSA128HRegisterClass;
 510   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 511     NSize = 2;
 512     RegDecoder = DecodeMSA128WRegisterClass;
 513   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 514     NSize = 1;
 515     RegDecoder = DecodeMSA128DRegisterClass;
 516   } else
 517     llvm_unreachable("Invalid encoding");
 518
 519   assert(NSize != 0 && RegDecoder != nullptr);
 520
 521   // $wd
 522   tmp = fieldFromInstruction(insn, 6, 5);
 523   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 524     return MCDisassembler::Fail;
 525   // $wd_in
 526   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 527     return MCDisassembler::Fail;
 528   // $n
 529   tmp = fieldFromInstruction(insn, 16, NSize);
 530   MI.addOperand(MCOperand::CreateImm(tmp));
 531   // $ws
 532   tmp = fieldFromInstruction(insn, 11, 5);
 533   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 534     return MCDisassembler::Fail;
 535   // $n2
 536   MI.addOperand(MCOperand::CreateImm(0));
 537
 538   return MCDisassembler::Success;
 539 }
 540
 541 template <typename InsnType>
 542 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 543                                           uint64_t Address,
 544                                           const void *Decoder) {
 545   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 546   // (otherwise we would have matched the ADDI instruction from the earlier
 547   // ISA's instead).
 548   //
 549   // We have:
 550   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 551   //      BOVC if rs >= rt
 552   //      BEQZALC if rs == 0 && rt != 0
 553   //      BEQC if rs < rt && rs != 0
 554
 555   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 556   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 557   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 558   bool HasRs = false;
 559
 560   if (Rs >= Rt) {
 561     MI.setOpcode(Mips::BOVC);
 562     HasRs = true;
 563   } else if (Rs != 0 && Rs < Rt) {
 564     MI.setOpcode(Mips::BEQC);
 565     HasRs = true;
 566   } else
 567     MI.setOpcode(Mips::BEQZALC);
 568
 569   if (HasRs)
 570     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 571                                        Rs)));
 572
 573   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 574                                      Rt)));
 575   MI.addOperand(MCOperand::CreateImm(Imm));
 576
 577   return MCDisassembler::Success;
 578 }
 579
 580 template <typename InsnType>
 581 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 582                                            uint64_t Address,
 583                                            const void *Decoder) {
 584   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 585   // (otherwise we would have matched the ADDI instruction from the earlier
 586   // ISA's instead).
 587   //
 588   // We have:
 589   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 590   //      BNVC if rs >= rt
 591   //      BNEZALC if rs == 0 && rt != 0
 592   //      BNEC if rs < rt && rs != 0
 593
 594   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 595   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 596   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 597   bool HasRs = false;
 598
 599   if (Rs >= Rt) {
 600     MI.setOpcode(Mips::BNVC);
 601     HasRs = true;
 602   } else if (Rs != 0 && Rs < Rt) {
 603     MI.setOpcode(Mips::BNEC);
 604     HasRs = true;
 605   } else
 606     MI.setOpcode(Mips::BNEZALC);
 607
 608   if (HasRs)
 609     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 610                                        Rs)));
 611
 612   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 613                                      Rt)));
 614   MI.addOperand(MCOperand::CreateImm(Imm));
 615
 616   return MCDisassembler::Success;
 617 }
 618
 619 template <typename InsnType>
 620 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 621                                            uint64_t Address,
 622                                            const void *Decoder) {
 623   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 624   // (otherwise we would have matched the BLEZL instruction from the earlier
 625   // ISA's instead).
 626   //
 627   // We have:
 628   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 629   //      Invalid if rs == 0
 630   //      BLEZC   if rs == 0  && rt != 0
 631   //      BGEZC   if rs == rt && rt != 0
 632   //      BGEC    if rs != rt && rs != 0  && rt != 0
 633
 634   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 635   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 636   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 637   bool HasRs = false;
 638
 639   if (Rt == 0)
 640     return MCDisassembler::Fail;
 641   else if (Rs == 0)
 642     MI.setOpcode(Mips::BLEZC);
 643   else if (Rs == Rt)
 644     MI.setOpcode(Mips::BGEZC);
 645   else {
 646     HasRs = true;
 647     MI.setOpcode(Mips::BGEC);
 648   }
 649
 650   if (HasRs)
 651     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 652                                        Rs)));
 653
 654   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 655                                      Rt)));
 656
 657   MI.addOperand(MCOperand::CreateImm(Imm));
 658
 659   return MCDisassembler::Success;
 660 }
 661
 662 template <typename InsnType>
 663 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 664                                            uint64_t Address,
 665                                            const void *Decoder) {
 666   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 667   // (otherwise we would have matched the BGTZL instruction from the earlier
 668   // ISA's instead).
 669   //
 670   // We have:
 671   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 672   //      Invalid if rs == 0
 673   //      BGTZC   if rs == 0  && rt != 0
 674   //      BLTZC   if rs == rt && rt != 0
 675   //      BLTC    if rs != rt && rs != 0  && rt != 0
 676
 677   bool HasRs = false;
 678
 679   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 680   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 681   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 682
 683   if (Rt == 0)
 684     return MCDisassembler::Fail;
 685   else if (Rs == 0)
 686     MI.setOpcode(Mips::BGTZC);
 687   else if (Rs == Rt)
 688     MI.setOpcode(Mips::BLTZC);
 689   else {
 690     MI.setOpcode(Mips::BLTC);
 691     HasRs = true;
 692   }
 693
 694   if (HasRs)
 695     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 696                                               Rs)));
 697
 698   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 699                                      Rt)));
 700
 701   MI.addOperand(MCOperand::CreateImm(Imm));
 702
 703   return MCDisassembler::Success;
 704 }
 705
 706 template <typename InsnType>
 707 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 708                                           uint64_t Address,
 709                                           const void *Decoder) {
 710   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 711   // (otherwise we would have matched the BGTZ instruction from the earlier
 712   // ISA's instead).
 713   //
 714   // We have:
 715   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 716   //      BGTZ    if rt == 0
 717   //      BGTZALC if rs == 0 && rt != 0
 718   //      BLTZALC if rs != 0 && rs == rt
 719   //      BLTUC   if rs != 0 && rs != rt
 720
 721   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 722   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 723   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 724   bool HasRs = false;
 725   bool HasRt = false;
 726
 727   if (Rt == 0) {
 728     MI.setOpcode(Mips::BGTZ);
 729     HasRs = true;
 730   } else if (Rs == 0) {
 731     MI.setOpcode(Mips::BGTZALC);
 732     HasRt = true;
 733   } else if (Rs == Rt) {
 734     MI.setOpcode(Mips::BLTZALC);
 735     HasRs = true;
 736   } else {
 737     MI.setOpcode(Mips::BLTUC);
 738     HasRs = true;
 739     HasRt = true;
 740   }
 741
 742   if (HasRs)
 743     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 744                                        Rs)));
 745
 746   if (HasRt)
 747     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 748                                        Rt)));
 749
 750   MI.addOperand(MCOperand::CreateImm(Imm));
 751
 752   return MCDisassembler::Success;
 753 }
 754
 755 template <typename InsnType>
 756 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 757                                            uint64_t Address,
 758                                            const void *Decoder) {
 759   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 760   // (otherwise we would have matched the BLEZL instruction from the earlier
 761   // ISA's instead).
 762   //
 763   // We have:
 764   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 765   //      Invalid   if rs == 0
 766   //      BLEZALC   if rs == 0  && rt != 0
 767   //      BGEZALC   if rs == rt && rt != 0
 768   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 769
 770   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 771   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 772   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 773   bool HasRs = false;
 774
 775   if (Rt == 0)
 776     return MCDisassembler::Fail;
 777   else if (Rs == 0)
 778     MI.setOpcode(Mips::BLEZALC);
 779   else if (Rs == Rt)
 780     MI.setOpcode(Mips::BGEZALC);
 781   else {
 782     HasRs = true;
 783     MI.setOpcode(Mips::BGEUC);
 784   }
 785
 786   if (HasRs)
 787     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 788                                        Rs)));
 789   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 790                                      Rt)));
 791
 792   MI.addOperand(MCOperand::CreateImm(Imm));
 793
 794   return MCDisassembler::Success;
 795 }
 796
 797 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 798 /// according to the given endianess.
 799 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 800                                       uint64_t &Size, uint32_t &Insn,
 801                                       bool IsBigEndian) {
 802   // We want to read exactly 2 Bytes of data.
 803   if (Bytes.size() < 2) {
 804     Size = 0;
 805     return MCDisassembler::Fail;
 806   }
 807
 808   if (IsBigEndian) {
 809     Insn = (Bytes[0] << 8) | Bytes[1];
 810   } else {
 811     Insn = (Bytes[1] << 8) | Bytes[0];
 812   }
 813
 814   return MCDisassembler::Success;
 815 }
 816
 817 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 818 /// according to the given endianess
 819 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 820                                       uint64_t &Size, uint32_t &Insn,
 821                                       bool IsBigEndian, bool IsMicroMips) {
 822   // We want to read exactly 4 Bytes of data.
 823   if (Bytes.size() < 4) {
 824     Size = 0;
 825     return MCDisassembler::Fail;
 826   }
 827
 828   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 829   // always precede the low 16 bits in the instruction stream (that is, they
 830   // are placed at lower addresses in the instruction stream).
 831   //
 832   // microMIPS byte ordering:
 833   //   Big-endian:    0 | 1 | 2 | 3
 834   //   Little-endian: 1 | 0 | 3 | 2
 835
 836   if (IsBigEndian) {
 837     // Encoded as a big-endian 32-bit word in the stream.
 838     Insn =
 839         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 840   } else {
 841     if (IsMicroMips) {
 842       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 843              (Bytes[1] << 24);
 844     } else {
 845       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 846              (Bytes[3] << 24);
 847     }
 848   }
 849
 850   return MCDisassembler::Success;
 851 }
 852
 853 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 854                                               ArrayRef<uint8_t> Bytes,
 855                                               uint64_t Address,
 856                                               raw_ostream &VStream,
 857                                               raw_ostream &CStream) const {
 858   uint32_t Insn;
 859   DecodeStatus Result;
 860
 861   if (IsMicroMips) {
 862     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 863
 864     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 865     // Calling the auto-generated decoder function.
 866     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 867                                this, STI);
 868     if (Result != MCDisassembler::Fail) {
 869       Size = 2;
 870       return Result;
 871     }
 872
 873     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 874     if (Result == MCDisassembler::Fail)
 875       return MCDisassembler::Fail;
 876
 877     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 878     // Calling the auto-generated decoder function.
 879     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 880                                this, STI);
 881     if (Result != MCDisassembler::Fail) {
 882       Size = 4;
 883       return Result;
 884     }
 885     return MCDisassembler::Fail;
 886   }
 887
 888   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 889   if (Result == MCDisassembler::Fail)
 890     return MCDisassembler::Fail;
 891
 892   if (hasCOP3()) {
 893     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 894     Result =
 895         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 896     if (Result != MCDisassembler::Fail) {
 897       Size = 4;
 898       return Result;
 899     }
 900   }
 901
 902   if (hasMips32r6() && isGP64()) {
 903     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 904     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 905                                Address, this, STI);
 906     if (Result != MCDisassembler::Fail) {
 907       Size = 4;
 908       return Result;
 909     }
 910   }
 911
 912   if (hasMips32r6()) {
 913     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 914     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 915                                Address, this, STI);
 916     if (Result != MCDisassembler::Fail) {
 917       Size = 4;
 918       return Result;
 919     }
 920   }
 921
 922   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 923   // Calling the auto-generated decoder function.
 924   Result =
 925       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 926   if (Result != MCDisassembler::Fail) {
 927     Size = 4;
 928     return Result;
 929   }
 930
 931   return MCDisassembler::Fail;
 932 }
 933
 934 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 935                                                 ArrayRef<uint8_t> Bytes,
 936                                                 uint64_t Address,
 937                                                 raw_ostream &VStream,
 938                                                 raw_ostream &CStream) const {
 939   uint32_t Insn;
 940
 941   DecodeStatus Result =
 942       readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 943   if (Result == MCDisassembler::Fail)
 944     return MCDisassembler::Fail;
 945
 946   // Calling the auto-generated decoder function.
 947   Result =
 948       decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
 949   if (Result != MCDisassembler::Fail) {
 950     Size = 4;
 951     return Result;
 952   }
 953   // If we fail to decode in Mips64 decoder space we can try in Mips32
 954   Result =
 955       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 956   if (Result != MCDisassembler::Fail) {
 957     Size = 4;
 958     return Result;
 959   }
 960
 961   return MCDisassembler::Fail;
 962 }
 963
 964 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 965                                                  unsigned RegNo,
 966                                                  uint64_t Address,
 967                                                  const void *Decoder) {
 968
 969   return MCDisassembler::Fail;
 970
 971 }
 972
 973 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 974                                              unsigned RegNo,
 975                                              uint64_t Address,
 976                                              const void *Decoder) {
 977
 978   if (RegNo > 31)
 979     return MCDisassembler::Fail;
 980
 981   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 982   Inst.addOperand(MCOperand::CreateReg(Reg));
 983   return MCDisassembler::Success;
 984 }
 985
 986 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 987                                                unsigned RegNo,
 988                                                uint64_t Address,
 989                                                const void *Decoder) {
 990   if (RegNo > 7)
 991     return MCDisassembler::Fail;
 992   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 993   Inst.addOperand(MCOperand::CreateReg(Reg));
 994   return MCDisassembler::Success;
 995 }
 996
 997 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 998                                                    unsigned RegNo,
 999                                                    uint64_t Address,
1000                                                    const void *Decoder) {
1001   if (RegNo > 7)
1002     return MCDisassembler::Fail;
1003   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1004   Inst.addOperand(MCOperand::CreateReg(Reg));
1005   return MCDisassembler::Success;
1006 }
1007
1008 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1009                                              unsigned RegNo,
1010                                              uint64_t Address,
1011                                              const void *Decoder) {
1012   if (RegNo > 31)
1013     return MCDisassembler::Fail;
1014   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1015   Inst.addOperand(MCOperand::CreateReg(Reg));
1016   return MCDisassembler::Success;
1017 }
1018
1019 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1020                                            unsigned RegNo,
1021                                            uint64_t Address,
1022                                            const void *Decoder) {
1023   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
1024     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1025
1026   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1027 }
1028
1029 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1030                                             unsigned RegNo,
1031                                             uint64_t Address,
1032                                             const void *Decoder) {
1033   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1034 }
1035
1036 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1037                                              unsigned RegNo,
1038                                              uint64_t Address,
1039                                              const void *Decoder) {
1040   if (RegNo > 31)
1041     return MCDisassembler::Fail;
1042
1043   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1044   Inst.addOperand(MCOperand::CreateReg(Reg));
1045   return MCDisassembler::Success;
1046 }
1047
1048 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1049                                              unsigned RegNo,
1050                                              uint64_t Address,
1051                                              const void *Decoder) {
1052   if (RegNo > 31)
1053     return MCDisassembler::Fail;
1054
1055   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1056   Inst.addOperand(MCOperand::CreateReg(Reg));
1057   return MCDisassembler::Success;
1058 }
1059
1060 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1061                                            unsigned RegNo,
1062                                            uint64_t Address,
1063                                            const void *Decoder) {
1064   if (RegNo > 31)
1065     return MCDisassembler::Fail;
1066   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1067   Inst.addOperand(MCOperand::CreateReg(Reg));
1068   return MCDisassembler::Success;
1069 }
1070
1071 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1072                                            unsigned RegNo,
1073                                            uint64_t Address,
1074                                            const void *Decoder) {
1075   if (RegNo > 7)
1076     return MCDisassembler::Fail;
1077   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1078   Inst.addOperand(MCOperand::CreateReg(Reg));
1079   return MCDisassembler::Success;
1080 }
1081
1082 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1083                                              uint64_t Address,
1084                                              const void *Decoder) {
1085   if (RegNo > 31)
1086     return MCDisassembler::Fail;
1087
1088   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1089   Inst.addOperand(MCOperand::CreateReg(Reg));
1090   return MCDisassembler::Success;
1091 }
1092
1093 static DecodeStatus DecodeMem(MCInst &Inst,
1094                               unsigned Insn,
1095                               uint64_t Address,
1096                               const void *Decoder) {
1097   int Offset = SignExtend32<16>(Insn & 0xffff);
1098   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1099   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1100
1101   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1102   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1103
1104   if(Inst.getOpcode() == Mips::SC ||
1105      Inst.getOpcode() == Mips::SCD){
1106     Inst.addOperand(MCOperand::CreateReg(Reg));
1107   }
1108
1109   Inst.addOperand(MCOperand::CreateReg(Reg));
1110   Inst.addOperand(MCOperand::CreateReg(Base));
1111   Inst.addOperand(MCOperand::CreateImm(Offset));
1112
1113   return MCDisassembler::Success;
1114 }
1115
1116 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1117                               unsigned Insn,
1118                               uint64_t Address,
1119                               const void *Decoder) {
1120   int Offset = SignExtend32<16>(Insn & 0xffff);
1121   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1122   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1123
1124   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1125
1126   Inst.addOperand(MCOperand::CreateReg(Base));
1127   Inst.addOperand(MCOperand::CreateImm(Offset));
1128   Inst.addOperand(MCOperand::CreateImm(Hint));
1129
1130   return MCDisassembler::Success;
1131 }
1132
1133 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1134                                     unsigned Insn,
1135                                     uint64_t Address,
1136                                     const void *Decoder) {
1137   int Offset = SignExtend32<12>(Insn & 0xfff);
1138   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1139   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1140
1141   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1142
1143   Inst.addOperand(MCOperand::CreateReg(Base));
1144   Inst.addOperand(MCOperand::CreateImm(Offset));
1145   Inst.addOperand(MCOperand::CreateImm(Hint));
1146
1147   return MCDisassembler::Success;
1148 }
1149
1150 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
1151                                     unsigned Insn,
1152                                     uint64_t Address,
1153                                     const void *Decoder) {
1154   int Offset = fieldFromInstruction(Insn, 7, 9);
1155   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1156   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1157
1158   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1159
1160   Inst.addOperand(MCOperand::CreateReg(Base));
1161   Inst.addOperand(MCOperand::CreateImm(Offset));
1162   Inst.addOperand(MCOperand::CreateImm(Hint));
1163
1164   return MCDisassembler::Success;
1165 }
1166
1167 static DecodeStatus DecodeSyncI(MCInst &Inst,
1168                               unsigned Insn,
1169                               uint64_t Address,
1170                               const void *Decoder) {
1171   int Offset = SignExtend32<16>(Insn & 0xffff);
1172   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1173
1174   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1175
1176   Inst.addOperand(MCOperand::CreateReg(Base));
1177   Inst.addOperand(MCOperand::CreateImm(Offset));
1178
1179   return MCDisassembler::Success;
1180 }
1181
1182 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1183                                     uint64_t Address, const void *Decoder) {
1184   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1185   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1186   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1187
1188   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1189   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1190
1191   Inst.addOperand(MCOperand::CreateReg(Reg));
1192   Inst.addOperand(MCOperand::CreateReg(Base));
1193
1194   // The immediate field of an LD/ST instruction is scaled which means it must
1195   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1196   // data format.
1197   // .b - 1 byte
1198   // .h - 2 bytes
1199   // .w - 4 bytes
1200   // .d - 8 bytes
1201   switch(Inst.getOpcode())
1202   {
1203   default:
1204     assert (0 && "Unexpected instruction");
1205     return MCDisassembler::Fail;
1206     break;
1207   case Mips::LD_B:
1208   case Mips::ST_B:
1209     Inst.addOperand(MCOperand::CreateImm(Offset));
1210     break;
1211   case Mips::LD_H:
1212   case Mips::ST_H:
1213     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1214     break;
1215   case Mips::LD_W:
1216   case Mips::ST_W:
1217     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1218     break;
1219   case Mips::LD_D:
1220   case Mips::ST_D:
1221     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1222     break;
1223   }
1224
1225   return MCDisassembler::Success;
1226 }
1227
1228 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1229                                     unsigned Insn,
1230                                     uint64_t Address,
1231                                     const void *Decoder) {
1232   unsigned Offset = Insn & 0xf;
1233   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1234   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1235
1236   switch (Inst.getOpcode()) {
1237     case Mips::LBU16_MM:
1238     case Mips::LHU16_MM:
1239     case Mips::LW16_MM:
1240       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1241             == MCDisassembler::Fail)
1242         return MCDisassembler::Fail;
1243       break;
1244     case Mips::SB16_MM:
1245     case Mips::SH16_MM:
1246     case Mips::SW16_MM:
1247       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1248             == MCDisassembler::Fail)
1249         return MCDisassembler::Fail;
1250       break;
1251   }
1252
1253   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1254         == MCDisassembler::Fail)
1255     return MCDisassembler::Fail;
1256
1257   switch (Inst.getOpcode()) {
1258     case Mips::LBU16_MM:
1259       if (Offset == 0xf)
1260         Inst.addOperand(MCOperand::CreateImm(-1));
1261       else
1262         Inst.addOperand(MCOperand::CreateImm(Offset));
1263       break;
1264     case Mips::SB16_MM:
1265       Inst.addOperand(MCOperand::CreateImm(Offset));
1266       break;
1267     case Mips::LHU16_MM:
1268     case Mips::SH16_MM:
1269       Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1270       break;
1271     case Mips::LW16_MM:
1272     case Mips::SW16_MM:
1273       Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1274       break;
1275   }
1276
1277   return MCDisassembler::Success;
1278 }
1279
1280 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1281                                           unsigned Insn,
1282                                           uint64_t Address,
1283                                           const void *Decoder) {
1284   unsigned Offset = Insn & 0x1F;
1285   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1286
1287   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1288
1289   Inst.addOperand(MCOperand::CreateReg(Reg));
1290   Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1291   Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1292
1293   return MCDisassembler::Success;
1294 }
1295
1296 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1297                                           unsigned Insn,
1298                                           uint64_t Address,
1299                                           const void *Decoder) {
1300   unsigned Offset = Insn & 0x7F;
1301   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1302
1303   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1304
1305   Inst.addOperand(MCOperand::CreateReg(Reg));
1306   Inst.addOperand(MCOperand::CreateReg(Mips::GP));
1307   Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1308
1309   return MCDisassembler::Success;
1310 }
1311
1312 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1313                                                unsigned Insn,
1314                                                uint64_t Address,
1315                                                const void *Decoder) {
1316   int Offset = SignExtend32<4>(Insn & 0xf);
1317
1318   if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1319       == MCDisassembler::Fail)
1320     return MCDisassembler::Fail;
1321
1322   Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1323   Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1324
1325   return MCDisassembler::Success;
1326 }
1327
1328 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1329                                      unsigned Insn,
1330                                      uint64_t Address,
1331                                      const void *Decoder) {
1332   int Offset = SignExtend32<12>(Insn & 0x0fff);
1333   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1334   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1335
1336   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1337   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1338
1339   switch (Inst.getOpcode()) {
1340   case Mips::SWM32_MM:
1341   case Mips::LWM32_MM:
1342     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1343         == MCDisassembler::Fail)
1344       return MCDisassembler::Fail;
1345     Inst.addOperand(MCOperand::CreateReg(Base));
1346     Inst.addOperand(MCOperand::CreateImm(Offset));
1347     break;
1348   case Mips::SC_MM:
1349     Inst.addOperand(MCOperand::CreateReg(Reg));
1350     // fallthrough
1351   default:
1352     Inst.addOperand(MCOperand::CreateReg(Reg));
1353     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1354       Inst.addOperand(MCOperand::CreateReg(Reg+1));
1355
1356     Inst.addOperand(MCOperand::CreateReg(Base));
1357     Inst.addOperand(MCOperand::CreateImm(Offset));
1358   }
1359
1360   return MCDisassembler::Success;
1361 }
1362
1363 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1364                                      unsigned Insn,
1365                                      uint64_t Address,
1366                                      const void *Decoder) {
1367   int Offset = SignExtend32<16>(Insn & 0xffff);
1368   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1369   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1370
1371   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1372   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1373
1374   Inst.addOperand(MCOperand::CreateReg(Reg));
1375   Inst.addOperand(MCOperand::CreateReg(Base));
1376   Inst.addOperand(MCOperand::CreateImm(Offset));
1377
1378   return MCDisassembler::Success;
1379 }
1380
1381 static DecodeStatus DecodeFMem(MCInst &Inst,
1382                                unsigned Insn,
1383                                uint64_t Address,
1384                                const void *Decoder) {
1385   int Offset = SignExtend32<16>(Insn & 0xffff);
1386   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1387   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1388
1389   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1390   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1391
1392   Inst.addOperand(MCOperand::CreateReg(Reg));
1393   Inst.addOperand(MCOperand::CreateReg(Base));
1394   Inst.addOperand(MCOperand::CreateImm(Offset));
1395
1396   return MCDisassembler::Success;
1397 }
1398
1399 static DecodeStatus DecodeFMem2(MCInst &Inst,
1400                                unsigned Insn,
1401                                uint64_t Address,
1402                                const void *Decoder) {
1403   int Offset = SignExtend32<16>(Insn & 0xffff);
1404   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1405   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1406
1407   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1408   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1409
1410   Inst.addOperand(MCOperand::CreateReg(Reg));
1411   Inst.addOperand(MCOperand::CreateReg(Base));
1412   Inst.addOperand(MCOperand::CreateImm(Offset));
1413
1414   return MCDisassembler::Success;
1415 }
1416
1417 static DecodeStatus DecodeFMem3(MCInst &Inst,
1418                                unsigned Insn,
1419                                uint64_t Address,
1420                                const void *Decoder) {
1421   int Offset = SignExtend32<16>(Insn & 0xffff);
1422   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1423   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1424
1425   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1426   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1427
1428   Inst.addOperand(MCOperand::CreateReg(Reg));
1429   Inst.addOperand(MCOperand::CreateReg(Base));
1430   Inst.addOperand(MCOperand::CreateImm(Offset));
1431
1432   return MCDisassembler::Success;
1433 }
1434
1435 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1436                                     unsigned Insn,
1437                                     uint64_t Address,
1438                                     const void *Decoder) {
1439   int Offset = SignExtend32<11>(Insn & 0x07ff);
1440   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1441   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1442
1443   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1444   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1445
1446   Inst.addOperand(MCOperand::CreateReg(Reg));
1447   Inst.addOperand(MCOperand::CreateReg(Base));
1448   Inst.addOperand(MCOperand::CreateImm(Offset));
1449
1450   return MCDisassembler::Success;
1451 }
1452 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1453                                        unsigned Insn,
1454                                        uint64_t Address,
1455                                        const void *Decoder) {
1456   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1457   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1458   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1459
1460   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1461   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1462
1463   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1464     Inst.addOperand(MCOperand::CreateReg(Rt));
1465   }
1466
1467   Inst.addOperand(MCOperand::CreateReg(Rt));
1468   Inst.addOperand(MCOperand::CreateReg(Base));
1469   Inst.addOperand(MCOperand::CreateImm(Offset));
1470
1471   return MCDisassembler::Success;
1472 }
1473
1474 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1475                                               unsigned RegNo,
1476                                               uint64_t Address,
1477                                               const void *Decoder) {
1478   // Currently only hardware register 29 is supported.
1479   if (RegNo != 29)
1480     return  MCDisassembler::Fail;
1481   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1482   return MCDisassembler::Success;
1483 }
1484
1485 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1486                                               unsigned RegNo,
1487                                               uint64_t Address,
1488                                               const void *Decoder) {
1489   if (RegNo > 30 || RegNo %2)
1490     return MCDisassembler::Fail;
1491
1492   ;
1493   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1494   Inst.addOperand(MCOperand::CreateReg(Reg));
1495   return MCDisassembler::Success;
1496 }
1497
1498 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1499                                                 unsigned RegNo,
1500                                                 uint64_t Address,
1501                                                 const void *Decoder) {
1502   if (RegNo >= 4)
1503     return MCDisassembler::Fail;
1504
1505   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1506   Inst.addOperand(MCOperand::CreateReg(Reg));
1507   return MCDisassembler::Success;
1508 }
1509
1510 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1511                                                unsigned RegNo,
1512                                                uint64_t Address,
1513                                                const void *Decoder) {
1514   if (RegNo >= 4)
1515     return MCDisassembler::Fail;
1516
1517   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1518   Inst.addOperand(MCOperand::CreateReg(Reg));
1519   return MCDisassembler::Success;
1520 }
1521
1522 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1523                                                unsigned RegNo,
1524                                                uint64_t Address,
1525                                                const void *Decoder) {
1526   if (RegNo >= 4)
1527     return MCDisassembler::Fail;
1528
1529   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1530   Inst.addOperand(MCOperand::CreateReg(Reg));
1531   return MCDisassembler::Success;
1532 }
1533
1534 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1535                                                unsigned RegNo,
1536                                                uint64_t Address,
1537                                                const void *Decoder) {
1538   if (RegNo > 31)
1539     return MCDisassembler::Fail;
1540
1541   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1542   Inst.addOperand(MCOperand::CreateReg(Reg));
1543   return MCDisassembler::Success;
1544 }
1545
1546 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1547                                                unsigned RegNo,
1548                                                uint64_t Address,
1549                                                const void *Decoder) {
1550   if (RegNo > 31)
1551     return MCDisassembler::Fail;
1552
1553   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1554   Inst.addOperand(MCOperand::CreateReg(Reg));
1555   return MCDisassembler::Success;
1556 }
1557
1558 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1559                                                unsigned RegNo,
1560                                                uint64_t Address,
1561                                                const void *Decoder) {
1562   if (RegNo > 31)
1563     return MCDisassembler::Fail;
1564
1565   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1566   Inst.addOperand(MCOperand::CreateReg(Reg));
1567   return MCDisassembler::Success;
1568 }
1569
1570 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1571                                                unsigned RegNo,
1572                                                uint64_t Address,
1573                                                const void *Decoder) {
1574   if (RegNo > 31)
1575     return MCDisassembler::Fail;
1576
1577   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1578   Inst.addOperand(MCOperand::CreateReg(Reg));
1579   return MCDisassembler::Success;
1580 }
1581
1582 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1583                                                unsigned RegNo,
1584                                                uint64_t Address,
1585                                                const void *Decoder) {
1586   if (RegNo > 7)
1587     return MCDisassembler::Fail;
1588
1589   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1590   Inst.addOperand(MCOperand::CreateReg(Reg));
1591   return MCDisassembler::Success;
1592 }
1593
1594 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1595                                             unsigned RegNo,
1596                                             uint64_t Address,
1597                                             const void *Decoder) {
1598   if (RegNo > 31)
1599     return MCDisassembler::Fail;
1600
1601   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1602   Inst.addOperand(MCOperand::CreateReg(Reg));
1603   return MCDisassembler::Success;
1604 }
1605
1606 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1607                                        unsigned Offset,
1608                                        uint64_t Address,
1609                                        const void *Decoder) {
1610   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1611   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1612   return MCDisassembler::Success;
1613 }
1614
1615 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1616                                      unsigned Insn,
1617                                      uint64_t Address,
1618                                      const void *Decoder) {
1619
1620   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1621   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1622   return MCDisassembler::Success;
1623 }
1624
1625 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1626                                          unsigned Offset,
1627                                          uint64_t Address,
1628                                          const void *Decoder) {
1629   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1630
1631   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1632   return MCDisassembler::Success;
1633 }
1634
1635 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1636                                          unsigned Offset,
1637                                          uint64_t Address,
1638                                          const void *Decoder) {
1639   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1640
1641   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1642   return MCDisassembler::Success;
1643 }
1644
1645 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1646                                           unsigned Offset,
1647                                           uint64_t Address,
1648                                           const void *Decoder) {
1649   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1650   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1651   return MCDisassembler::Success;
1652 }
1653
1654 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1655                                            unsigned Offset,
1656                                            uint64_t Address,
1657                                            const void *Decoder) {
1658   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1659   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1660   return MCDisassembler::Success;
1661 }
1662
1663 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1664                                          unsigned Offset,
1665                                          uint64_t Address,
1666                                          const void *Decoder) {
1667   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1668   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1669   return MCDisassembler::Success;
1670 }
1671
1672 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1673                                        unsigned Insn,
1674                                        uint64_t Address,
1675                                        const void *Decoder) {
1676   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1677   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1678   return MCDisassembler::Success;
1679 }
1680
1681 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1682                                        unsigned Value,
1683                                        uint64_t Address,
1684                                        const void *Decoder) {
1685   if (Value == 0)
1686     Inst.addOperand(MCOperand::CreateImm(1));
1687   else if (Value == 0x7)
1688     Inst.addOperand(MCOperand::CreateImm(-1));
1689   else
1690     Inst.addOperand(MCOperand::CreateImm(Value << 2));
1691   return MCDisassembler::Success;
1692 }
1693
1694 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1695                                     unsigned Value,
1696                                     uint64_t Address,
1697                                     const void *Decoder) {
1698   Inst.addOperand(MCOperand::CreateImm(Value << 2));
1699   return MCDisassembler::Success;
1700 }
1701
1702 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1703                                   unsigned Value,
1704                                   uint64_t Address,
1705                                   const void *Decoder) {
1706   if (Value == 0x7F)
1707     Inst.addOperand(MCOperand::CreateImm(-1));
1708   else
1709     Inst.addOperand(MCOperand::CreateImm(Value));
1710   return MCDisassembler::Success;
1711 }
1712
1713 static DecodeStatus DecodeSimm4(MCInst &Inst,
1714                                 unsigned Value,
1715                                 uint64_t Address,
1716                                 const void *Decoder) {
1717   Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1718   return MCDisassembler::Success;
1719 }
1720
1721 static DecodeStatus DecodeSimm16(MCInst &Inst,
1722                                  unsigned Insn,
1723                                  uint64_t Address,
1724                                  const void *Decoder) {
1725   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1726   return MCDisassembler::Success;
1727 }
1728
1729 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1730                                  unsigned Insn,
1731                                  uint64_t Address,
1732                                  const void *Decoder) {
1733   // We add one to the immediate field as it was encoded as 'imm - 1'.
1734   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1735   return MCDisassembler::Success;
1736 }
1737
1738 static DecodeStatus DecodeInsSize(MCInst &Inst,
1739                                   unsigned Insn,
1740                                   uint64_t Address,
1741                                   const void *Decoder) {
1742   // First we need to grab the pos(lsb) from MCInst.
1743   int Pos = Inst.getOperand(2).getImm();
1744   int Size = (int) Insn - Pos + 1;
1745   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1746   return MCDisassembler::Success;
1747 }
1748
1749 static DecodeStatus DecodeExtSize(MCInst &Inst,
1750                                   unsigned Insn,
1751                                   uint64_t Address,
1752                                   const void *Decoder) {
1753   int Size = (int) Insn  + 1;
1754   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1755   return MCDisassembler::Success;
1756 }
1757
1758 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1759                                      uint64_t Address, const void *Decoder) {
1760   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1761   return MCDisassembler::Success;
1762 }
1763
1764 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1765                                      uint64_t Address, const void *Decoder) {
1766   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1767   return MCDisassembler::Success;
1768 }
1769
1770 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1771                                   uint64_t Address, const void *Decoder) {
1772   int32_t DecodedValue;
1773   switch (Insn) {
1774   case 0: DecodedValue = 256; break;
1775   case 1: DecodedValue = 257; break;
1776   case 510: DecodedValue = -258; break;
1777   case 511: DecodedValue = -257; break;
1778   default: DecodedValue = SignExtend32<9>(Insn); break;
1779   }
1780   Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1781   return MCDisassembler::Success;
1782 }
1783
1784 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1785                                     uint64_t Address, const void *Decoder) {
1786   // Insn must be >= 0, since it is unsigned that condition is always true.
1787   assert(Insn < 16);
1788   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1789                              255, 32768, 65535};
1790   Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1791   return MCDisassembler::Success;
1792 }
1793
1794 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1795                                     uint64_t Address, const void *Decoder) {
1796   Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1797   return MCDisassembler::Success;
1798 }
1799
1800 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1801                                          unsigned Insn,
1802                                          uint64_t Address,
1803                                          const void *Decoder) {
1804   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1805                      Mips::S6, Mips::FP};
1806   unsigned RegNum;
1807
1808   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1809   // Empty register lists are not allowed.
1810   if (RegLst == 0)
1811     return MCDisassembler::Fail;
1812
1813   RegNum = RegLst & 0xf;
1814   for (unsigned i = 0; i < RegNum; i++)
1815     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1816
1817   if (RegLst & 0x10)
1818     Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1819
1820   return MCDisassembler::Success;
1821 }
1822
1823 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1824                                            uint64_t Address,
1825                                            const void *Decoder) {
1826   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1827   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1828   unsigned RegNum = RegLst & 0x3;
1829
1830   for (unsigned i = 0; i <= RegNum; i++)
1831     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1832
1833   Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1834
1835   return MCDisassembler::Success;
1836 }
1837
1838 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1839                                      uint64_t Address, const void *Decoder) {
1840   Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));
1841   return MCDisassembler::Success;
1842 }