1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCParser/MCAsmLexer.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/MC/MCTargetAsmParser.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/ADT/APInt.h"
28 class MipsAssemblerOptions {
30 MipsAssemblerOptions():
31 aTReg(1), reorder(true), macro(true) {
34 unsigned getATRegNum() {return aTReg;}
35 bool setATReg(unsigned Reg);
37 bool isReorder() {return reorder;}
38 void setReorder() {reorder = true;}
39 void setNoreorder() {reorder = false;}
41 bool isMacro() {return macro;}
42 void setMacro() {macro = true;}
43 void setNomacro() {macro = false;}
53 class MipsAsmParser : public MCTargetAsmParser {
65 MipsAssemblerOptions Options;
66 bool hasConsumedDollar;
68 #define GET_ASSEMBLER_HEADER
69 #include "MipsGenAsmMatcher.inc"
71 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
72 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
73 MCStreamer &Out, unsigned &ErrorInfo,
74 bool MatchingInlineAsm);
76 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
78 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
80 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
82 bool ParseDirective(AsmToken DirectiveID);
84 MipsAsmParser::OperandMatchResultTy
85 parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
88 MipsAsmParser::OperandMatchResultTy
89 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
91 bool parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands, int RegKind);
93 MipsAsmParser::OperandMatchResultTy
94 parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
96 MipsAsmParser::OperandMatchResultTy
97 parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
99 MipsAsmParser::OperandMatchResultTy
100 parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
102 MipsAsmParser::OperandMatchResultTy
103 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
105 MipsAsmParser::OperandMatchResultTy
106 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
108 MipsAsmParser::OperandMatchResultTy
109 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
111 MipsAsmParser::OperandMatchResultTy
112 parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
114 MipsAsmParser::OperandMatchResultTy
115 parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
117 MipsAsmParser::OperandMatchResultTy
118 parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
120 MipsAsmParser::OperandMatchResultTy
121 parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
123 MipsAsmParser::OperandMatchResultTy
124 parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
126 MipsAsmParser::OperandMatchResultTy
127 parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
129 MipsAsmParser::OperandMatchResultTy
130 parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
132 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
135 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
138 int tryParseRegister(bool is64BitReg);
140 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
143 bool needsExpansion(MCInst &Inst);
145 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
146 SmallVectorImpl<MCInst> &Instructions);
147 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
148 SmallVectorImpl<MCInst> &Instructions);
149 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
150 SmallVectorImpl<MCInst> &Instructions);
151 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
152 SmallVectorImpl<MCInst> &Instructions);
153 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
154 SmallVectorImpl<MCInst> &Instructions,
155 bool isLoad,bool isImmOpnd);
156 bool reportParseError(StringRef ErrorMsg);
158 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
159 bool parseRelocOperand(const MCExpr *&Res);
161 const MCExpr* evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
163 bool isEvaluated(const MCExpr *Expr);
164 bool parseDirectiveSet();
166 bool parseSetAtDirective();
167 bool parseSetNoAtDirective();
168 bool parseSetMacroDirective();
169 bool parseSetNoMacroDirective();
170 bool parseSetReorderDirective();
171 bool parseSetNoReorderDirective();
173 bool parseSetAssignment();
175 bool parseDirectiveWord(unsigned Size, SMLoc L);
177 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
179 bool isMips64() const {
180 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
183 bool isFP64() const {
184 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
188 return STI.getFeatureBits() & Mips::FeatureN64;
191 int matchRegisterName(StringRef Symbol, bool is64BitReg);
193 int matchCPURegisterName(StringRef Symbol);
195 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
197 int matchFPURegisterName(StringRef Name);
199 int matchFCCRegisterName(StringRef Name);
201 int matchACRegisterName(StringRef Name);
203 int regKindToRegClass(int RegKind);
205 FpFormatTy getFpFormat() {return FpFormat;}
207 unsigned getReg(int RC, int RegNo);
211 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
212 SmallVectorImpl<MCInst> &Instructions);
214 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
215 : MCTargetAsmParser(), STI(sti), Parser(parser), hasConsumedDollar(false) {
216 // Initialize the set of available features.
217 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
220 MCAsmParser &getParser() const { return Parser; }
221 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
228 /// MipsOperand - Instances of this class represent a parsed Mips machine
230 class MipsOperand : public MCParsedAsmOperand {
261 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
289 SMLoc StartLoc, EndLoc;
292 void addRegOperands(MCInst &Inst, unsigned N) const {
293 assert(N == 1 && "Invalid number of operands!");
294 Inst.addOperand(MCOperand::CreateReg(getReg()));
297 void addPtrRegOperands(MCInst &Inst, unsigned N) const {
298 assert(N == 1 && "Invalid number of operands!");
299 Inst.addOperand(MCOperand::CreateReg(getPtrReg()));
302 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
303 // Add as immediate when possible. Null MCExpr = 0.
305 Inst.addOperand(MCOperand::CreateImm(0));
306 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
307 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
309 Inst.addOperand(MCOperand::CreateExpr(Expr));
312 void addImmOperands(MCInst &Inst, unsigned N) const {
313 assert(N == 1 && "Invalid number of operands!");
314 const MCExpr *Expr = getImm();
318 void addMemOperands(MCInst &Inst, unsigned N) const {
319 assert(N == 2 && "Invalid number of operands!");
321 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
323 const MCExpr *Expr = getMemOff();
327 bool isReg() const { return Kind == k_Register; }
328 bool isImm() const { return Kind == k_Immediate; }
329 bool isToken() const { return Kind == k_Token; }
330 bool isMem() const { return Kind == k_Memory; }
331 bool isPtrReg() const { return Kind == k_PtrReg; }
333 StringRef getToken() const {
334 assert(Kind == k_Token && "Invalid access!");
335 return StringRef(Tok.Data, Tok.Length);
338 unsigned getReg() const {
339 assert((Kind == k_Register) && "Invalid access!");
343 unsigned getPtrReg() const {
344 assert((Kind == k_PtrReg) && "Invalid access!");
348 void setRegKind(RegisterKind RegKind) {
349 assert((Kind == k_Register || Kind == k_PtrReg) && "Invalid access!");
353 const MCExpr *getImm() const {
354 assert((Kind == k_Immediate) && "Invalid access!");
358 unsigned getMemBase() const {
359 assert((Kind == k_Memory) && "Invalid access!");
363 const MCExpr *getMemOff() const {
364 assert((Kind == k_Memory) && "Invalid access!");
368 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
369 MipsOperand *Op = new MipsOperand(k_Token);
370 Op->Tok.Data = Str.data();
371 Op->Tok.Length = Str.size();
377 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
378 MipsOperand *Op = new MipsOperand(k_Register);
379 Op->Reg.RegNum = RegNum;
385 static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) {
386 MipsOperand *Op = new MipsOperand(k_PtrReg);
387 Op->Reg.RegNum = RegNum;
393 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
394 MipsOperand *Op = new MipsOperand(k_Immediate);
401 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
403 MipsOperand *Op = new MipsOperand(k_Memory);
411 bool isGPR32Asm() const {
412 return Kind == k_Register && Reg.Kind == Kind_GPR32;
414 void addRegAsmOperands(MCInst &Inst, unsigned N) const {
415 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
418 bool isGPR64Asm() const {
419 return Kind == k_Register && Reg.Kind == Kind_GPR64;
422 bool isHWRegsAsm() const {
423 assert((Kind == k_Register) && "Invalid access!");
424 return Reg.Kind == Kind_HWRegs;
427 bool isCCRAsm() const {
428 assert((Kind == k_Register) && "Invalid access!");
429 return Reg.Kind == Kind_CCRRegs;
432 bool isAFGR64Asm() const {
433 return Kind == k_Register && Reg.Kind == Kind_AFGR64Regs;
436 bool isFGR64Asm() const {
437 return Kind == k_Register && Reg.Kind == Kind_FGR64Regs;
440 bool isFGR32Asm() const {
441 return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
444 bool isFGRH32Asm() const {
445 return (Kind == k_Register) && Reg.Kind == Kind_FGRH32Regs;
448 bool isFCCRegsAsm() const {
449 return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
452 bool isACC64DSPAsm() const {
453 return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
456 bool isLO32DSPAsm() const {
457 return Kind == k_Register && Reg.Kind == Kind_LO32DSP;
460 bool isHI32DSPAsm() const {
461 return Kind == k_Register && Reg.Kind == Kind_HI32DSP;
464 /// getStartLoc - Get the location of the first token of this operand.
465 SMLoc getStartLoc() const {
468 /// getEndLoc - Get the location of the last token of this operand.
469 SMLoc getEndLoc() const {
473 virtual void print(raw_ostream &OS) const {
474 llvm_unreachable("unimplemented!");
476 }; // class MipsOperand
480 extern const MCInstrDesc MipsInsts[];
482 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
483 return MipsInsts[Opcode];
486 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
487 SmallVectorImpl<MCInst> &Instructions) {
488 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
490 if (MCID.hasDelaySlot() && Options.isReorder()) {
491 // If this instruction has a delay slot and .set reorder is active,
492 // emit a NOP after it.
493 Instructions.push_back(Inst);
495 NopInst.setOpcode(Mips::SLL);
496 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
497 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
498 NopInst.addOperand(MCOperand::CreateImm(0));
499 Instructions.push_back(NopInst);
503 if (MCID.mayLoad() || MCID.mayStore()) {
504 // Check the offset of memory operand, if it is a symbol
505 // reference or immediate we may have to expand instructions.
506 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
507 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
508 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY)
509 || (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
510 MCOperand &Op = Inst.getOperand(i);
512 int MemOffset = Op.getImm();
513 if (MemOffset < -32768 || MemOffset > 32767) {
514 // Offset can't exceed 16bit value.
515 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
518 } else if (Op.isExpr()) {
519 const MCExpr *Expr = Op.getExpr();
520 if (Expr->getKind() == MCExpr::SymbolRef) {
521 const MCSymbolRefExpr *SR =
522 static_cast<const MCSymbolRefExpr*>(Expr);
523 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
525 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
528 } else if (!isEvaluated(Expr)) {
529 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
537 if (needsExpansion(Inst))
538 expandInstruction(Inst, IDLoc, Instructions);
540 Instructions.push_back(Inst);
545 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
547 switch (Inst.getOpcode()) {
548 case Mips::LoadImm32Reg:
549 case Mips::LoadAddr32Imm:
550 case Mips::LoadAddr32Reg:
557 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
558 SmallVectorImpl<MCInst> &Instructions) {
559 switch (Inst.getOpcode()) {
560 case Mips::LoadImm32Reg:
561 return expandLoadImm(Inst, IDLoc, Instructions);
562 case Mips::LoadAddr32Imm:
563 return expandLoadAddressImm(Inst, IDLoc, Instructions);
564 case Mips::LoadAddr32Reg:
565 return expandLoadAddressReg(Inst, IDLoc, Instructions);
569 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
570 SmallVectorImpl<MCInst> &Instructions) {
572 const MCOperand &ImmOp = Inst.getOperand(1);
573 assert(ImmOp.isImm() && "expected immediate operand kind");
574 const MCOperand &RegOp = Inst.getOperand(0);
575 assert(RegOp.isReg() && "expected register operand kind");
577 int ImmValue = ImmOp.getImm();
578 tmpInst.setLoc(IDLoc);
579 if (0 <= ImmValue && ImmValue <= 65535) {
580 // For 0 <= j <= 65535.
581 // li d,j => ori d,$zero,j
582 tmpInst.setOpcode(Mips::ORi);
583 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
584 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
585 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
586 Instructions.push_back(tmpInst);
587 } else if (ImmValue < 0 && ImmValue >= -32768) {
588 // For -32768 <= j < 0.
589 // li d,j => addiu d,$zero,j
590 tmpInst.setOpcode(Mips::ADDiu);
591 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
592 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
593 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
594 Instructions.push_back(tmpInst);
596 // For any other value of j that is representable as a 32-bit integer.
597 // li d,j => lui d,hi16(j)
599 tmpInst.setOpcode(Mips::LUi);
600 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
601 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
602 Instructions.push_back(tmpInst);
604 tmpInst.setOpcode(Mips::ORi);
605 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
606 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
607 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
608 tmpInst.setLoc(IDLoc);
609 Instructions.push_back(tmpInst);
613 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
614 SmallVectorImpl<MCInst> &Instructions) {
616 const MCOperand &ImmOp = Inst.getOperand(2);
617 assert(ImmOp.isImm() && "expected immediate operand kind");
618 const MCOperand &SrcRegOp = Inst.getOperand(1);
619 assert(SrcRegOp.isReg() && "expected register operand kind");
620 const MCOperand &DstRegOp = Inst.getOperand(0);
621 assert(DstRegOp.isReg() && "expected register operand kind");
622 int ImmValue = ImmOp.getImm();
623 if (-32768 <= ImmValue && ImmValue <= 65535) {
624 // For -32768 <= j <= 65535.
625 // la d,j(s) => addiu d,s,j
626 tmpInst.setOpcode(Mips::ADDiu);
627 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
628 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
629 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
630 Instructions.push_back(tmpInst);
632 // For any other value of j that is representable as a 32-bit integer.
633 // la d,j(s) => lui d,hi16(j)
636 tmpInst.setOpcode(Mips::LUi);
637 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
638 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
639 Instructions.push_back(tmpInst);
641 tmpInst.setOpcode(Mips::ORi);
642 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
643 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
644 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
645 Instructions.push_back(tmpInst);
647 tmpInst.setOpcode(Mips::ADDu);
648 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
649 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
650 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
651 Instructions.push_back(tmpInst);
655 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
656 SmallVectorImpl<MCInst> &Instructions) {
658 const MCOperand &ImmOp = Inst.getOperand(1);
659 assert(ImmOp.isImm() && "expected immediate operand kind");
660 const MCOperand &RegOp = Inst.getOperand(0);
661 assert(RegOp.isReg() && "expected register operand kind");
662 int ImmValue = ImmOp.getImm();
663 if (-32768 <= ImmValue && ImmValue <= 65535) {
664 // For -32768 <= j <= 65535.
665 // la d,j => addiu d,$zero,j
666 tmpInst.setOpcode(Mips::ADDiu);
667 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
668 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
669 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
670 Instructions.push_back(tmpInst);
672 // For any other value of j that is representable as a 32-bit integer.
673 // la d,j => lui d,hi16(j)
675 tmpInst.setOpcode(Mips::LUi);
676 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
677 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
678 Instructions.push_back(tmpInst);
680 tmpInst.setOpcode(Mips::ORi);
681 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
682 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
683 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
684 Instructions.push_back(tmpInst);
688 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
689 SmallVectorImpl<MCInst> &Instructions, bool isLoad, bool isImmOpnd) {
690 const MCSymbolRefExpr *SR;
692 unsigned ImmOffset, HiOffset, LoOffset;
693 const MCExpr *ExprOffset;
695 unsigned AtRegNum = getReg((isMips64()) ? Mips::GPR64RegClassID
696 : Mips::GPR32RegClassID, getATReg());
697 // 1st operand is either the source or destination register.
698 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
699 unsigned RegOpNum = Inst.getOperand(0).getReg();
700 // 2nd operand is the base register.
701 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
702 unsigned BaseRegNum = Inst.getOperand(1).getReg();
703 // 3rd operand is either an immediate or expression.
705 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
706 ImmOffset = Inst.getOperand(2).getImm();
707 LoOffset = ImmOffset & 0x0000ffff;
708 HiOffset = (ImmOffset & 0xffff0000) >> 16;
709 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
710 if (LoOffset & 0x8000)
713 ExprOffset = Inst.getOperand(2).getExpr();
714 // All instructions will have the same location.
715 TempInst.setLoc(IDLoc);
716 // 1st instruction in expansion is LUi. For load instruction we can use
717 // the dst register as a temporary if base and dst are different,
718 // but for stores we must use $at.
719 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
720 TempInst.setOpcode(Mips::LUi);
721 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
723 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
725 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
726 SR = static_cast<const MCSymbolRefExpr*>(ExprOffset);
727 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
728 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
730 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
732 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
733 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
736 // Add the instruction to the list.
737 Instructions.push_back(TempInst);
738 // Prepare TempInst for next instruction.
740 // Add temp register to base.
741 TempInst.setOpcode(Mips::ADDu);
742 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
743 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
744 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
745 Instructions.push_back(TempInst);
747 // And finaly, create original instruction with low part
748 // of offset and new base.
749 TempInst.setOpcode(Inst.getOpcode());
750 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
751 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
753 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
755 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
756 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
757 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
759 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
761 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
762 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
765 Instructions.push_back(TempInst);
770 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
771 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
772 MCStreamer &Out, unsigned &ErrorInfo,
773 bool MatchingInlineAsm) {
775 SmallVector<MCInst, 8> Instructions;
776 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
779 switch (MatchResult) {
782 case Match_Success: {
783 if (processInstruction(Inst, IDLoc, Instructions))
785 for (unsigned i = 0; i < Instructions.size(); i++)
786 Out.EmitInstruction(Instructions[i]);
789 case Match_MissingFeature:
790 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
792 case Match_InvalidOperand: {
793 SMLoc ErrorLoc = IDLoc;
794 if (ErrorInfo != ~0U) {
795 if (ErrorInfo >= Operands.size())
796 return Error(IDLoc, "too few operands for instruction");
798 ErrorLoc = ((MipsOperand*) Operands[ErrorInfo])->getStartLoc();
799 if (ErrorLoc == SMLoc())
803 return Error(ErrorLoc, "invalid operand for instruction");
805 case Match_MnemonicFail:
806 return Error(IDLoc, "invalid instruction");
811 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
817 CC = StringSwitch<unsigned>(Name)
851 // Although SGI documentation just cuts out t0-t3 for n32/n64,
852 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
853 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
854 if (isMips64() && 8 <= CC && CC <= 11)
857 if (CC == -1 && isMips64())
858 CC = StringSwitch<unsigned>(Name)
871 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
873 if (Name[0] == 'f') {
874 StringRef NumString = Name.substr(1);
876 if (NumString.getAsInteger(10, IntVal))
877 return -1; // This is not an integer.
878 if (IntVal > 31) // Maximum index for fpu register.
885 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
887 if (Name.startswith("fcc")) {
888 StringRef NumString = Name.substr(3);
890 if (NumString.getAsInteger(10, IntVal))
891 return -1; // This is not an integer.
892 if (IntVal > 7) // There are only 8 fcc registers.
899 int MipsAsmParser::matchACRegisterName(StringRef Name) {
901 if (Name.startswith("ac")) {
902 StringRef NumString = Name.substr(2);
904 if (NumString.getAsInteger(10, IntVal))
905 return -1; // This is not an integer.
906 if (IntVal > 3) // There are only 3 acc registers.
913 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
916 CC = matchCPURegisterName(Name);
918 return matchRegisterByNumber(CC, is64BitReg ? Mips::GPR64RegClassID
919 : Mips::GPR32RegClassID);
920 CC= matchFPURegisterName(Name);
921 //TODO: decide about fpu register class
922 return matchRegisterByNumber(CC, isFP64() ? Mips::FGR64RegClassID
923 : Mips::FGR32RegClassID);
926 int MipsAsmParser::regKindToRegClass(int RegKind) {
929 case MipsOperand::Kind_GPR32: return Mips::GPR32RegClassID;
930 case MipsOperand::Kind_GPR64: return Mips::GPR64RegClassID;
931 case MipsOperand::Kind_HWRegs: return Mips::HWRegsRegClassID;
932 case MipsOperand::Kind_FGR32Regs: return Mips::FGR32RegClassID;
933 case MipsOperand::Kind_FGRH32Regs: return Mips::FGRH32RegClassID;
934 case MipsOperand::Kind_FGR64Regs: return Mips::FGR64RegClassID;
935 case MipsOperand::Kind_AFGR64Regs: return Mips::AFGR64RegClassID;
936 case MipsOperand::Kind_CCRRegs: return Mips::CCRRegClassID;
937 case MipsOperand::Kind_ACC64DSP: return Mips::ACC64DSPRegClassID;
938 case MipsOperand::Kind_FCCRegs: return Mips::FCCRegClassID;
944 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
952 int MipsAsmParser::getATReg() {
953 return Options.getATRegNum();
956 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
957 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
960 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
962 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
965 return getReg(RegClass, RegNum);
968 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
969 const AsmToken &Tok = Parser.getTok();
972 if (Tok.is(AsmToken::Identifier)) {
973 std::string lowerCase = Tok.getString().lower();
974 RegNum = matchRegisterName(lowerCase, is64BitReg);
975 } else if (Tok.is(AsmToken::Integer))
976 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
977 is64BitReg ? Mips::GPR64RegClassID : Mips::GPR32RegClassID);
981 bool MipsAsmParser::tryParseRegisterOperand(
982 SmallVectorImpl<MCParsedAsmOperand*> &Operands, bool is64BitReg) {
984 SMLoc S = Parser.getTok().getLoc();
987 RegNo = tryParseRegister(is64BitReg);
991 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
992 Parser.getTok().getLoc()));
993 Parser.Lex(); // Eat register token.
997 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
998 StringRef Mnemonic) {
999 // Check if the current operand has a custom associated parser, if so, try to
1000 // custom parse the operand, or fallback to the general approach.
1001 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1002 if (ResTy == MatchOperand_Success)
1004 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1005 // there was a match, but an error occurred, in which case, just return that
1006 // the operand parsing failed.
1007 if (ResTy == MatchOperand_ParseFail)
1010 switch (getLexer().getKind()) {
1012 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1014 case AsmToken::Dollar: {
1015 // Parse the register.
1016 SMLoc S = Parser.getTok().getLoc();
1017 Parser.Lex(); // Eat dollar token.
1018 // Parse the register operand.
1019 if (!tryParseRegisterOperand(Operands, isMips64())) {
1020 if (getLexer().is(AsmToken::LParen)) {
1021 // Check if it is indexed addressing operand.
1022 Operands.push_back(MipsOperand::CreateToken("(", S));
1023 Parser.Lex(); // Eat the parenthesis.
1024 if (getLexer().isNot(AsmToken::Dollar))
1027 Parser.Lex(); // Eat the dollar
1028 if (tryParseRegisterOperand(Operands, isMips64()))
1031 if (!getLexer().is(AsmToken::RParen))
1034 S = Parser.getTok().getLoc();
1035 Operands.push_back(MipsOperand::CreateToken(")", S));
1040 // Maybe it is a symbol reference.
1041 StringRef Identifier;
1042 if (Parser.parseIdentifier(Identifier))
1045 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1047 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1049 // Otherwise create a symbol reference.
1050 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
1053 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1056 case AsmToken::Identifier:
1057 // Look for the existing symbol, we should check if
1058 // we need to assigne the propper RegisterKind.
1059 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
1061 // Else drop to expression parsing.
1062 case AsmToken::LParen:
1063 case AsmToken::Minus:
1064 case AsmToken::Plus:
1065 case AsmToken::Integer:
1066 case AsmToken::String: {
1067 // Quoted label names.
1068 const MCExpr *IdVal;
1069 SMLoc S = Parser.getTok().getLoc();
1070 if (getParser().parseExpression(IdVal))
1072 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1073 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1076 case AsmToken::Percent: {
1077 // It is a symbol reference or constant expression.
1078 const MCExpr *IdVal;
1079 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1080 if (parseRelocOperand(IdVal))
1083 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1085 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1087 } // case AsmToken::Percent
1088 } // switch(getLexer().getKind())
1092 const MCExpr* MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1093 StringRef RelocStr) {
1095 // Check the type of the expression.
1096 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1097 // It's a constant, evaluate lo or hi value.
1098 if (RelocStr == "lo") {
1099 short Val = MCE->getValue();
1100 Res = MCConstantExpr::Create(Val, getContext());
1101 } else if (RelocStr == "hi") {
1102 int Val = MCE->getValue();
1103 int LoSign = Val & 0x8000;
1104 Val = (Val & 0xffff0000) >> 16;
1105 // Lower part is treated as a signed int, so if it is negative
1106 // we must add 1 to the hi part to compensate.
1109 Res = MCConstantExpr::Create(Val, getContext());
1111 llvm_unreachable("Invalid RelocStr value");
1116 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1117 // It's a symbol, create a symbolic expression from the symbol.
1118 StringRef Symbol = MSRE->getSymbol().getName();
1119 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1120 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1124 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1125 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1126 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1127 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1131 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1132 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1133 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1136 // Just return the original expression.
1140 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1142 switch (Expr->getKind()) {
1143 case MCExpr::Constant:
1145 case MCExpr::SymbolRef:
1146 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1147 case MCExpr::Binary:
1148 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1149 if (!isEvaluated(BE->getLHS()))
1151 return isEvaluated(BE->getRHS());
1154 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1161 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1162 Parser.Lex(); // Eat the % token.
1163 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1164 if (Tok.isNot(AsmToken::Identifier))
1167 std::string Str = Tok.getIdentifier().str();
1169 Parser.Lex(); // Eat the identifier.
1170 // Now make an expression from the rest of the operand.
1171 const MCExpr *IdVal;
1174 if (getLexer().getKind() == AsmToken::LParen) {
1176 Parser.Lex(); // Eat the '(' token.
1177 if (getLexer().getKind() == AsmToken::Percent) {
1178 Parser.Lex(); // Eat the % token.
1179 const AsmToken &nextTok = Parser.getTok();
1180 if (nextTok.isNot(AsmToken::Identifier))
1183 Str += nextTok.getIdentifier();
1184 Parser.Lex(); // Eat the identifier.
1185 if (getLexer().getKind() != AsmToken::LParen)
1190 if (getParser().parseParenExpression(IdVal, EndLoc))
1193 while (getLexer().getKind() == AsmToken::RParen)
1194 Parser.Lex(); // Eat the ')' token.
1197 return true; // Parenthesis must follow the relocation operand.
1199 Res = evaluateRelocExpr(IdVal, Str);
1203 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1205 StartLoc = Parser.getTok().getLoc();
1206 RegNo = tryParseRegister(isMips64());
1207 EndLoc = Parser.getTok().getLoc();
1208 return (RegNo == (unsigned) -1);
1211 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1215 while (getLexer().getKind() == AsmToken::LParen)
1218 switch (getLexer().getKind()) {
1221 case AsmToken::Identifier:
1222 case AsmToken::LParen:
1223 case AsmToken::Integer:
1224 case AsmToken::Minus:
1225 case AsmToken::Plus:
1227 Result = getParser().parseParenExpression(Res, S);
1229 Result = (getParser().parseExpression(Res));
1230 while (getLexer().getKind() == AsmToken::RParen)
1233 case AsmToken::Percent:
1234 Result = parseRelocOperand(Res);
1239 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1240 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
1242 const MCExpr *IdVal = 0;
1244 bool isParenExpr = false;
1245 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1246 // First operand is the offset.
1247 S = Parser.getTok().getLoc();
1249 if (getLexer().getKind() == AsmToken::LParen) {
1254 if (getLexer().getKind() != AsmToken::Dollar) {
1255 if (parseMemOffset(IdVal, isParenExpr))
1256 return MatchOperand_ParseFail;
1258 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1259 if (Tok.isNot(AsmToken::LParen)) {
1260 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
1261 if (Mnemonic->getToken() == "la") {
1262 SMLoc E = SMLoc::getFromPointer(
1263 Parser.getTok().getLoc().getPointer() - 1);
1264 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1265 return MatchOperand_Success;
1267 if (Tok.is(AsmToken::EndOfStatement)) {
1268 SMLoc E = SMLoc::getFromPointer(
1269 Parser.getTok().getLoc().getPointer() - 1);
1271 // Zero register assumed, add a memory operand with ZERO as its base.
1272 Operands.push_back(MipsOperand::CreateMem(isMips64() ? Mips::ZERO_64
1275 return MatchOperand_Success;
1277 Error(Parser.getTok().getLoc(), "'(' expected");
1278 return MatchOperand_ParseFail;
1281 Parser.Lex(); // Eat the '(' token.
1284 Res = parseRegs(Operands, isMips64()? (int) MipsOperand::Kind_GPR64:
1285 (int) MipsOperand::Kind_GPR32);
1286 if (Res != MatchOperand_Success)
1289 if (Parser.getTok().isNot(AsmToken::RParen)) {
1290 Error(Parser.getTok().getLoc(), "')' expected");
1291 return MatchOperand_ParseFail;
1294 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1296 Parser.Lex(); // Eat the ')' token.
1299 IdVal = MCConstantExpr::Create(0, getContext());
1301 // Replace the register operand with the memory operand.
1302 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1303 int RegNo = op->getReg();
1304 // Remove the register from the operands.
1305 Operands.pop_back();
1306 // Add the memory operand.
1307 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1309 if (IdVal->EvaluateAsAbsolute(Imm))
1310 IdVal = MCConstantExpr::Create(Imm, getContext());
1311 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1312 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1316 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1318 return MatchOperand_Success;
1322 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1324 // If the first token is not '$' we have an error.
1325 if (Parser.getTok().isNot(AsmToken::Dollar))
1328 SMLoc S = Parser.getTok().getLoc();
1330 AsmToken::TokenKind TkKind = getLexer().getKind();
1333 if (TkKind == AsmToken::Integer) {
1334 Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
1335 regKindToRegClass(RegKind));
1338 } else if (TkKind == AsmToken::Identifier) {
1339 if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
1341 Reg = getReg(regKindToRegClass(RegKind), Reg);
1346 MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
1347 Op->setRegKind((MipsOperand::RegisterKind)RegKind);
1348 Operands.push_back(Op);
1353 MipsAsmParser::OperandMatchResultTy
1354 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1355 MipsOperand::RegisterKind RegKind = isN64() ? MipsOperand::Kind_GPR64 :
1356 MipsOperand::Kind_GPR32;
1358 // Parse index register.
1359 if (!parsePtrReg(Operands, RegKind))
1360 return MatchOperand_NoMatch;
1363 if (Parser.getTok().isNot(AsmToken::LParen))
1364 return MatchOperand_NoMatch;
1366 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1369 // Parse base register.
1370 if (!parsePtrReg(Operands, RegKind))
1371 return MatchOperand_NoMatch;
1374 if (Parser.getTok().isNot(AsmToken::RParen))
1375 return MatchOperand_NoMatch;
1377 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1380 return MatchOperand_Success;
1383 MipsAsmParser::OperandMatchResultTy
1384 MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1386 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1387 if (getLexer().getKind() == AsmToken::Identifier
1388 && !hasConsumedDollar) {
1389 if (searchSymbolAlias(Operands, Kind))
1390 return MatchOperand_Success;
1391 return MatchOperand_NoMatch;
1393 SMLoc S = Parser.getTok().getLoc();
1394 // If the first token is not '$', we have an error.
1395 if (Parser.getTok().isNot(AsmToken::Dollar) && !hasConsumedDollar)
1396 return MatchOperand_NoMatch;
1397 if (!hasConsumedDollar) {
1398 Parser.Lex(); // Eat the '$'
1399 hasConsumedDollar = true;
1401 if (getLexer().getKind() == AsmToken::Identifier) {
1403 std::string RegName = Parser.getTok().getString().lower();
1404 // Match register by name
1406 case MipsOperand::Kind_GPR32:
1407 case MipsOperand::Kind_GPR64:
1408 RegNum = matchCPURegisterName(RegName);
1410 case MipsOperand::Kind_AFGR64Regs:
1411 case MipsOperand::Kind_FGR64Regs:
1412 case MipsOperand::Kind_FGR32Regs:
1413 case MipsOperand::Kind_FGRH32Regs:
1414 RegNum = matchFPURegisterName(RegName);
1415 if (RegKind == MipsOperand::Kind_AFGR64Regs)
1418 case MipsOperand::Kind_FCCRegs:
1419 RegNum = matchFCCRegisterName(RegName);
1421 case MipsOperand::Kind_ACC64DSP:
1422 RegNum = matchACRegisterName(RegName);
1424 default: break; // No match, value is set to -1.
1426 // No match found, return _NoMatch to give a chance to other round.
1428 return MatchOperand_NoMatch;
1430 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1432 return MatchOperand_NoMatch;
1434 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S,
1435 Parser.getTok().getLoc());
1436 Op->setRegKind(Kind);
1437 Operands.push_back(Op);
1438 hasConsumedDollar = false;
1439 Parser.Lex(); // Eat the register name.
1440 if ((RegKind == MipsOperand::Kind_GPR32)
1441 && (getLexer().is(AsmToken::LParen))) {
1442 // Check if it is indexed addressing operand.
1443 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1444 Parser.Lex(); // Eat the parenthesis.
1445 if (parseRegs(Operands,RegKind) != MatchOperand_Success)
1446 return MatchOperand_NoMatch;
1447 if (getLexer().isNot(AsmToken::RParen))
1448 return MatchOperand_NoMatch;
1449 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1452 return MatchOperand_Success;
1453 } else if (getLexer().getKind() == AsmToken::Integer) {
1454 unsigned RegNum = Parser.getTok().getIntVal();
1455 if (Kind == MipsOperand::Kind_HWRegs) {
1457 return MatchOperand_NoMatch;
1458 // Only hwreg 29 is supported, found at index 0.
1461 int Reg = matchRegisterByNumber(RegNum, regKindToRegClass(Kind));
1463 return MatchOperand_NoMatch;
1464 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1465 Op->setRegKind(Kind);
1466 Operands.push_back(Op);
1467 hasConsumedDollar = false;
1468 Parser.Lex(); // Eat the register number.
1469 if ((RegKind == MipsOperand::Kind_GPR32)
1470 && (getLexer().is(AsmToken::LParen))) {
1471 // Check if it is indexed addressing operand.
1472 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1473 Parser.Lex(); // Eat the parenthesis.
1474 if (parseRegs(Operands,RegKind) != MatchOperand_Success)
1475 return MatchOperand_NoMatch;
1476 if (getLexer().isNot(AsmToken::RParen))
1477 return MatchOperand_NoMatch;
1478 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1481 return MatchOperand_Success;
1483 return MatchOperand_NoMatch;
1486 MipsAsmParser::OperandMatchResultTy
1487 MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1490 return MatchOperand_NoMatch;
1491 return parseRegs(Operands, (int) MipsOperand::Kind_GPR64);
1494 MipsAsmParser::OperandMatchResultTy
1495 MipsAsmParser::parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1496 return parseRegs(Operands, (int) MipsOperand::Kind_GPR32);
1499 MipsAsmParser::OperandMatchResultTy
1500 MipsAsmParser::parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1503 return MatchOperand_NoMatch;
1504 return parseRegs(Operands, (int) MipsOperand::Kind_AFGR64Regs);
1507 MipsAsmParser::OperandMatchResultTy
1508 MipsAsmParser::parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1510 return MatchOperand_NoMatch;
1511 return parseRegs(Operands, (int) MipsOperand::Kind_FGR64Regs);
1514 MipsAsmParser::OperandMatchResultTy
1515 MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1516 return parseRegs(Operands, (int) MipsOperand::Kind_FGR32Regs);
1519 MipsAsmParser::OperandMatchResultTy
1520 MipsAsmParser::parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1521 return parseRegs(Operands, (int) MipsOperand::Kind_FGRH32Regs);
1524 MipsAsmParser::OperandMatchResultTy
1525 MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1526 return parseRegs(Operands, (int) MipsOperand::Kind_FCCRegs);
1529 MipsAsmParser::OperandMatchResultTy
1530 MipsAsmParser::parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1531 return parseRegs(Operands, (int) MipsOperand::Kind_ACC64DSP);
1534 MipsAsmParser::OperandMatchResultTy
1535 MipsAsmParser::parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1536 // If the first token is not '$' we have an error.
1537 if (Parser.getTok().isNot(AsmToken::Dollar))
1538 return MatchOperand_NoMatch;
1540 SMLoc S = Parser.getTok().getLoc();
1541 Parser.Lex(); // Eat the '$'
1543 const AsmToken &Tok = Parser.getTok(); // Get next token.
1545 if (Tok.isNot(AsmToken::Identifier))
1546 return MatchOperand_NoMatch;
1548 if (!Tok.getIdentifier().startswith("ac"))
1549 return MatchOperand_NoMatch;
1551 StringRef NumString = Tok.getIdentifier().substr(2);
1554 if (NumString.getAsInteger(10, IntVal))
1555 return MatchOperand_NoMatch;
1557 unsigned Reg = matchRegisterByNumber(IntVal, Mips::LO32DSPRegClassID);
1559 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1560 Op->setRegKind(MipsOperand::Kind_LO32DSP);
1561 Operands.push_back(Op);
1563 Parser.Lex(); // Eat the register number.
1564 return MatchOperand_Success;
1567 MipsAsmParser::OperandMatchResultTy
1568 MipsAsmParser::parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1569 // If the first token is not '$' we have an error.
1570 if (Parser.getTok().isNot(AsmToken::Dollar))
1571 return MatchOperand_NoMatch;
1573 SMLoc S = Parser.getTok().getLoc();
1574 Parser.Lex(); // Eat the '$'
1576 const AsmToken &Tok = Parser.getTok(); // Get next token.
1578 if (Tok.isNot(AsmToken::Identifier))
1579 return MatchOperand_NoMatch;
1581 if (!Tok.getIdentifier().startswith("ac"))
1582 return MatchOperand_NoMatch;
1584 StringRef NumString = Tok.getIdentifier().substr(2);
1587 if (NumString.getAsInteger(10, IntVal))
1588 return MatchOperand_NoMatch;
1590 unsigned Reg = matchRegisterByNumber(IntVal, Mips::HI32DSPRegClassID);
1592 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1593 Op->setRegKind(MipsOperand::Kind_HI32DSP);
1594 Operands.push_back(Op);
1596 Parser.Lex(); // Eat the register number.
1597 return MatchOperand_Success;
1600 bool MipsAsmParser::searchSymbolAlias(
1601 SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {
1603 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1605 SMLoc S = Parser.getTok().getLoc();
1607 if (Sym->isVariable())
1608 Expr = Sym->getVariableValue();
1611 if (Expr->getKind() == MCExpr::SymbolRef) {
1612 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind) RegKind;
1613 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
1614 const StringRef DefSymbol = Ref->getSymbol().getName();
1615 if (DefSymbol.startswith("$")) {
1617 APInt IntVal(32, -1);
1618 if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
1619 RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
1621 ? Mips::GPR64RegClassID
1622 : Mips::GPR32RegClassID);
1624 // Lookup for the register with the corresponding name.
1626 case MipsOperand::Kind_AFGR64Regs:
1627 case MipsOperand::Kind_FGR64Regs:
1628 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1630 case MipsOperand::Kind_FGR32Regs:
1631 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1633 case MipsOperand::Kind_GPR64:
1634 case MipsOperand::Kind_GPR32:
1636 RegNum = matchCPURegisterName(DefSymbol.substr(1));
1640 RegNum = getReg(regKindToRegClass(Kind), RegNum);
1644 MipsOperand *op = MipsOperand::CreateReg(RegNum, S,
1645 Parser.getTok().getLoc());
1646 op->setRegKind(Kind);
1647 Operands.push_back(op);
1651 } else if (Expr->getKind() == MCExpr::Constant) {
1653 const MCConstantExpr *Const = static_cast<const MCConstantExpr*>(Expr);
1654 MipsOperand *op = MipsOperand::CreateImm(Const, S,
1655 Parser.getTok().getLoc());
1656 Operands.push_back(op);
1663 MipsAsmParser::OperandMatchResultTy
1664 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1665 return parseRegs(Operands, (int) MipsOperand::Kind_HWRegs);
1668 MipsAsmParser::OperandMatchResultTy
1669 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1670 return parseRegs(Operands, (int) MipsOperand::Kind_CCRRegs);
1673 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1675 MCSymbolRefExpr::VariantKind VK
1676 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1677 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1678 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1679 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1680 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1681 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1682 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1683 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1684 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1685 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1686 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1687 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1688 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1689 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1690 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1691 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1692 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1693 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1694 .Default(MCSymbolRefExpr::VK_None);
1699 bool MipsAsmParser::
1700 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1701 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1702 // Check if we have valid mnemonic
1703 if (!mnemonicIsValid(Name, 0)) {
1704 Parser.eatToEndOfStatement();
1705 return Error(NameLoc, "Unknown instruction");
1707 // First operand in MCInst is instruction mnemonic.
1708 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
1710 // Read the remaining operands.
1711 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1712 // Read the first operand.
1713 if (ParseOperand(Operands, Name)) {
1714 SMLoc Loc = getLexer().getLoc();
1715 Parser.eatToEndOfStatement();
1716 return Error(Loc, "unexpected token in argument list");
1719 while (getLexer().is(AsmToken::Comma)) {
1720 Parser.Lex(); // Eat the comma.
1721 // Parse and remember the operand.
1722 if (ParseOperand(Operands, Name)) {
1723 SMLoc Loc = getLexer().getLoc();
1724 Parser.eatToEndOfStatement();
1725 return Error(Loc, "unexpected token in argument list");
1729 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1730 SMLoc Loc = getLexer().getLoc();
1731 Parser.eatToEndOfStatement();
1732 return Error(Loc, "unexpected token in argument list");
1734 Parser.Lex(); // Consume the EndOfStatement.
1738 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
1739 SMLoc Loc = getLexer().getLoc();
1740 Parser.eatToEndOfStatement();
1741 return Error(Loc, ErrorMsg);
1744 bool MipsAsmParser::parseSetNoAtDirective() {
1745 // Line should look like: ".set noat".
1747 Options.setATReg(0);
1750 // If this is not the end of the statement, report an error.
1751 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1752 reportParseError("unexpected token in statement");
1755 Parser.Lex(); // Consume the EndOfStatement.
1759 bool MipsAsmParser::parseSetAtDirective() {
1760 // Line can be .set at - defaults to $1
1764 if (getLexer().is(AsmToken::EndOfStatement)) {
1765 Options.setATReg(1);
1766 Parser.Lex(); // Consume the EndOfStatement.
1768 } else if (getLexer().is(AsmToken::Equal)) {
1769 getParser().Lex(); // Eat the '='.
1770 if (getLexer().isNot(AsmToken::Dollar)) {
1771 reportParseError("unexpected token in statement");
1774 Parser.Lex(); // Eat the '$'.
1775 const AsmToken &Reg = Parser.getTok();
1776 if (Reg.is(AsmToken::Identifier)) {
1777 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
1778 } else if (Reg.is(AsmToken::Integer)) {
1779 AtRegNo = Reg.getIntVal();
1781 reportParseError("unexpected token in statement");
1785 if (AtRegNo < 1 || AtRegNo > 31) {
1786 reportParseError("unexpected token in statement");
1790 if (!Options.setATReg(AtRegNo)) {
1791 reportParseError("unexpected token in statement");
1794 getParser().Lex(); // Eat the register.
1796 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1797 reportParseError("unexpected token in statement");
1800 Parser.Lex(); // Consume the EndOfStatement.
1803 reportParseError("unexpected token in statement");
1808 bool MipsAsmParser::parseSetReorderDirective() {
1810 // If this is not the end of the statement, report an error.
1811 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1812 reportParseError("unexpected token in statement");
1815 Options.setReorder();
1816 Parser.Lex(); // Consume the EndOfStatement.
1820 bool MipsAsmParser::parseSetNoReorderDirective() {
1822 // If this is not the end of the statement, report an error.
1823 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1824 reportParseError("unexpected token in statement");
1827 Options.setNoreorder();
1828 Parser.Lex(); // Consume the EndOfStatement.
1832 bool MipsAsmParser::parseSetMacroDirective() {
1834 // If this is not the end of the statement, report an error.
1835 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1836 reportParseError("unexpected token in statement");
1840 Parser.Lex(); // Consume the EndOfStatement.
1844 bool MipsAsmParser::parseSetNoMacroDirective() {
1846 // If this is not the end of the statement, report an error.
1847 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1848 reportParseError("`noreorder' must be set before `nomacro'");
1851 if (Options.isReorder()) {
1852 reportParseError("`noreorder' must be set before `nomacro'");
1855 Options.setNomacro();
1856 Parser.Lex(); // Consume the EndOfStatement.
1860 bool MipsAsmParser::parseSetAssignment() {
1862 const MCExpr *Value;
1864 if (Parser.parseIdentifier(Name))
1865 reportParseError("expected identifier after .set");
1867 if (getLexer().isNot(AsmToken::Comma))
1868 return reportParseError("unexpected token in .set directive");
1871 if (getLexer().is(AsmToken::Dollar)) {
1873 SMLoc DollarLoc = getLexer().getLoc();
1874 // Consume the dollar sign, and check for a following identifier.
1876 // We have a '$' followed by something, make sure they are adjacent.
1877 if (DollarLoc.getPointer() + 1 != getTok().getLoc().getPointer())
1879 StringRef Res = StringRef(DollarLoc.getPointer(),
1880 getTok().getEndLoc().getPointer() - DollarLoc.getPointer());
1881 Symbol = getContext().GetOrCreateSymbol(Res);
1883 Value = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
1885 } else if (Parser.parseExpression(Value))
1886 return reportParseError("expected valid expression after comma");
1888 // Check if the Name already exists as a symbol.
1889 MCSymbol *Sym = getContext().LookupSymbol(Name);
1891 return reportParseError("symbol already defined");
1892 Sym = getContext().GetOrCreateSymbol(Name);
1893 Sym->setVariableValue(Value);
1898 bool MipsAsmParser::parseDirectiveSet() {
1900 // Get the next token.
1901 const AsmToken &Tok = Parser.getTok();
1903 if (Tok.getString() == "noat") {
1904 return parseSetNoAtDirective();
1905 } else if (Tok.getString() == "at") {
1906 return parseSetAtDirective();
1907 } else if (Tok.getString() == "reorder") {
1908 return parseSetReorderDirective();
1909 } else if (Tok.getString() == "noreorder") {
1910 return parseSetNoReorderDirective();
1911 } else if (Tok.getString() == "macro") {
1912 return parseSetMacroDirective();
1913 } else if (Tok.getString() == "nomacro") {
1914 return parseSetNoMacroDirective();
1915 } else if (Tok.getString() == "nomips16") {
1916 // Ignore this directive for now.
1917 Parser.eatToEndOfStatement();
1919 } else if (Tok.getString() == "nomicromips") {
1920 // Ignore this directive for now.
1921 Parser.eatToEndOfStatement();
1924 // It is just an identifier, look for an assignment.
1925 parseSetAssignment();
1932 /// parseDirectiveWord
1933 /// ::= .word [ expression (, expression)* ]
1934 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
1935 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1937 const MCExpr *Value;
1938 if (getParser().parseExpression(Value))
1941 getParser().getStreamer().EmitValue(Value, Size);
1943 if (getLexer().is(AsmToken::EndOfStatement))
1946 // FIXME: Improve diagnostic.
1947 if (getLexer().isNot(AsmToken::Comma))
1948 return Error(L, "unexpected token in directive");
1957 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
1959 StringRef IDVal = DirectiveID.getString();
1961 if (IDVal == ".ent") {
1962 // Ignore this directive for now.
1967 if (IDVal == ".end") {
1968 // Ignore this directive for now.
1973 if (IDVal == ".frame") {
1974 // Ignore this directive for now.
1975 Parser.eatToEndOfStatement();
1979 if (IDVal == ".set") {
1980 return parseDirectiveSet();
1983 if (IDVal == ".fmask") {
1984 // Ignore this directive for now.
1985 Parser.eatToEndOfStatement();
1989 if (IDVal == ".mask") {
1990 // Ignore this directive for now.
1991 Parser.eatToEndOfStatement();
1995 if (IDVal == ".gpword") {
1996 // Ignore this directive for now.
1997 Parser.eatToEndOfStatement();
2001 if (IDVal == ".word") {
2002 parseDirectiveWord(4, DirectiveID.getLoc());
2009 extern "C" void LLVMInitializeMipsAsmParser() {
2010 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2011 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2012 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2013 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2016 #define GET_REGISTER_MATCHER
2017 #define GET_MATCHER_IMPLEMENTATION
2018 #include "MipsGenAsmMatcher.inc"