1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCParser/MCAsmLexer.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/MC/MCTargetAsmParser.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/ADT/APInt.h"
28 class MipsAssemblerOptions {
30 MipsAssemblerOptions():
31 aTReg(1), reorder(true), macro(true) {
34 unsigned getATRegNum() {return aTReg;}
35 bool setATReg(unsigned Reg);
37 bool isReorder() {return reorder;}
38 void setReorder() {reorder = true;}
39 void setNoreorder() {reorder = false;}
41 bool isMacro() {return macro;}
42 void setMacro() {macro = true;}
43 void setNomacro() {macro = false;}
53 class MipsAsmParser : public MCTargetAsmParser {
57 MipsAssemblerOptions Options;
58 bool hasConsumedDollar;
60 #define GET_ASSEMBLER_HEADER
61 #include "MipsGenAsmMatcher.inc"
63 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
64 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
65 MCStreamer &Out, unsigned &ErrorInfo,
66 bool MatchingInlineAsm);
68 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
70 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
72 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
74 bool ParseDirective(AsmToken DirectiveID);
76 MipsAsmParser::OperandMatchResultTy
77 parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
80 MipsAsmParser::OperandMatchResultTy
81 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
83 bool parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands, int RegKind);
85 MipsAsmParser::OperandMatchResultTy
86 parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
88 MipsAsmParser::OperandMatchResultTy
89 parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
91 MipsAsmParser::OperandMatchResultTy
92 parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
94 MipsAsmParser::OperandMatchResultTy
95 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
97 MipsAsmParser::OperandMatchResultTy
98 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
100 MipsAsmParser::OperandMatchResultTy
101 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
103 MipsAsmParser::OperandMatchResultTy
104 parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
106 MipsAsmParser::OperandMatchResultTy
107 parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
109 MipsAsmParser::OperandMatchResultTy
110 parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
112 MipsAsmParser::OperandMatchResultTy
113 parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
115 MipsAsmParser::OperandMatchResultTy
116 parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
118 MipsAsmParser::OperandMatchResultTy
119 parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
121 MipsAsmParser::OperandMatchResultTy
122 parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
124 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
127 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
130 int tryParseRegister(bool is64BitReg);
132 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
135 bool needsExpansion(MCInst &Inst);
137 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
138 SmallVectorImpl<MCInst> &Instructions);
139 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
140 SmallVectorImpl<MCInst> &Instructions);
141 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
142 SmallVectorImpl<MCInst> &Instructions);
143 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
144 SmallVectorImpl<MCInst> &Instructions);
145 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
146 SmallVectorImpl<MCInst> &Instructions,
147 bool isLoad,bool isImmOpnd);
148 bool reportParseError(StringRef ErrorMsg);
150 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
151 bool parseRelocOperand(const MCExpr *&Res);
153 const MCExpr* evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
155 bool isEvaluated(const MCExpr *Expr);
156 bool parseDirectiveSet();
158 bool parseSetAtDirective();
159 bool parseSetNoAtDirective();
160 bool parseSetMacroDirective();
161 bool parseSetNoMacroDirective();
162 bool parseSetReorderDirective();
163 bool parseSetNoReorderDirective();
165 bool parseSetAssignment();
167 bool parseDirectiveWord(unsigned Size, SMLoc L);
169 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
171 bool isMips64() const {
172 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
175 bool isFP64() const {
176 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
180 return STI.getFeatureBits() & Mips::FeatureN64;
183 int matchRegisterName(StringRef Symbol, bool is64BitReg);
185 int matchCPURegisterName(StringRef Symbol);
187 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
189 int matchFPURegisterName(StringRef Name);
191 int matchFCCRegisterName(StringRef Name);
193 int matchACRegisterName(StringRef Name);
195 int regKindToRegClass(int RegKind);
197 unsigned getReg(int RC, int RegNo);
201 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
202 SmallVectorImpl<MCInst> &Instructions);
204 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
205 : MCTargetAsmParser(), STI(sti), Parser(parser), hasConsumedDollar(false) {
206 // Initialize the set of available features.
207 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
210 MCAsmParser &getParser() const { return Parser; }
211 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
218 /// MipsOperand - Instances of this class represent a parsed Mips machine
220 class MipsOperand : public MCParsedAsmOperand {
251 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
279 SMLoc StartLoc, EndLoc;
282 void addRegOperands(MCInst &Inst, unsigned N) const {
283 assert(N == 1 && "Invalid number of operands!");
284 Inst.addOperand(MCOperand::CreateReg(getReg()));
287 void addPtrRegOperands(MCInst &Inst, unsigned N) const {
288 assert(N == 1 && "Invalid number of operands!");
289 Inst.addOperand(MCOperand::CreateReg(getPtrReg()));
292 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
293 // Add as immediate when possible. Null MCExpr = 0.
295 Inst.addOperand(MCOperand::CreateImm(0));
296 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
297 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
299 Inst.addOperand(MCOperand::CreateExpr(Expr));
302 void addImmOperands(MCInst &Inst, unsigned N) const {
303 assert(N == 1 && "Invalid number of operands!");
304 const MCExpr *Expr = getImm();
308 void addMemOperands(MCInst &Inst, unsigned N) const {
309 assert(N == 2 && "Invalid number of operands!");
311 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
313 const MCExpr *Expr = getMemOff();
317 bool isReg() const { return Kind == k_Register; }
318 bool isImm() const { return Kind == k_Immediate; }
319 bool isToken() const { return Kind == k_Token; }
320 bool isMem() const { return Kind == k_Memory; }
321 bool isPtrReg() const { return Kind == k_PtrReg; }
323 StringRef getToken() const {
324 assert(Kind == k_Token && "Invalid access!");
325 return StringRef(Tok.Data, Tok.Length);
328 unsigned getReg() const {
329 assert((Kind == k_Register) && "Invalid access!");
333 unsigned getPtrReg() const {
334 assert((Kind == k_PtrReg) && "Invalid access!");
338 void setRegKind(RegisterKind RegKind) {
339 assert((Kind == k_Register || Kind == k_PtrReg) && "Invalid access!");
343 const MCExpr *getImm() const {
344 assert((Kind == k_Immediate) && "Invalid access!");
348 unsigned getMemBase() const {
349 assert((Kind == k_Memory) && "Invalid access!");
353 const MCExpr *getMemOff() const {
354 assert((Kind == k_Memory) && "Invalid access!");
358 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
359 MipsOperand *Op = new MipsOperand(k_Token);
360 Op->Tok.Data = Str.data();
361 Op->Tok.Length = Str.size();
367 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
368 MipsOperand *Op = new MipsOperand(k_Register);
369 Op->Reg.RegNum = RegNum;
375 static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) {
376 MipsOperand *Op = new MipsOperand(k_PtrReg);
377 Op->Reg.RegNum = RegNum;
383 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
384 MipsOperand *Op = new MipsOperand(k_Immediate);
391 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
393 MipsOperand *Op = new MipsOperand(k_Memory);
401 bool isGPR32Asm() const {
402 return Kind == k_Register && Reg.Kind == Kind_GPR32;
404 void addRegAsmOperands(MCInst &Inst, unsigned N) const {
405 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
408 bool isGPR64Asm() const {
409 return Kind == k_Register && Reg.Kind == Kind_GPR64;
412 bool isHWRegsAsm() const {
413 assert((Kind == k_Register) && "Invalid access!");
414 return Reg.Kind == Kind_HWRegs;
417 bool isCCRAsm() const {
418 assert((Kind == k_Register) && "Invalid access!");
419 return Reg.Kind == Kind_CCRRegs;
422 bool isAFGR64Asm() const {
423 return Kind == k_Register && Reg.Kind == Kind_AFGR64Regs;
426 bool isFGR64Asm() const {
427 return Kind == k_Register && Reg.Kind == Kind_FGR64Regs;
430 bool isFGR32Asm() const {
431 return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
434 bool isFGRH32Asm() const {
435 return (Kind == k_Register) && Reg.Kind == Kind_FGRH32Regs;
438 bool isFCCRegsAsm() const {
439 return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
442 bool isACC64DSPAsm() const {
443 return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
446 bool isLO32DSPAsm() const {
447 return Kind == k_Register && Reg.Kind == Kind_LO32DSP;
450 bool isHI32DSPAsm() const {
451 return Kind == k_Register && Reg.Kind == Kind_HI32DSP;
454 /// getStartLoc - Get the location of the first token of this operand.
455 SMLoc getStartLoc() const {
458 /// getEndLoc - Get the location of the last token of this operand.
459 SMLoc getEndLoc() const {
463 virtual void print(raw_ostream &OS) const {
464 llvm_unreachable("unimplemented!");
466 }; // class MipsOperand
470 extern const MCInstrDesc MipsInsts[];
472 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
473 return MipsInsts[Opcode];
476 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
477 SmallVectorImpl<MCInst> &Instructions) {
478 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
480 if (MCID.hasDelaySlot() && Options.isReorder()) {
481 // If this instruction has a delay slot and .set reorder is active,
482 // emit a NOP after it.
483 Instructions.push_back(Inst);
485 NopInst.setOpcode(Mips::SLL);
486 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
487 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
488 NopInst.addOperand(MCOperand::CreateImm(0));
489 Instructions.push_back(NopInst);
493 if (MCID.mayLoad() || MCID.mayStore()) {
494 // Check the offset of memory operand, if it is a symbol
495 // reference or immediate we may have to expand instructions.
496 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
497 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
498 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY)
499 || (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
500 MCOperand &Op = Inst.getOperand(i);
502 int MemOffset = Op.getImm();
503 if (MemOffset < -32768 || MemOffset > 32767) {
504 // Offset can't exceed 16bit value.
505 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
508 } else if (Op.isExpr()) {
509 const MCExpr *Expr = Op.getExpr();
510 if (Expr->getKind() == MCExpr::SymbolRef) {
511 const MCSymbolRefExpr *SR =
512 static_cast<const MCSymbolRefExpr*>(Expr);
513 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
515 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
518 } else if (!isEvaluated(Expr)) {
519 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
527 if (needsExpansion(Inst))
528 expandInstruction(Inst, IDLoc, Instructions);
530 Instructions.push_back(Inst);
535 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
537 switch (Inst.getOpcode()) {
538 case Mips::LoadImm32Reg:
539 case Mips::LoadAddr32Imm:
540 case Mips::LoadAddr32Reg:
547 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
548 SmallVectorImpl<MCInst> &Instructions) {
549 switch (Inst.getOpcode()) {
550 case Mips::LoadImm32Reg:
551 return expandLoadImm(Inst, IDLoc, Instructions);
552 case Mips::LoadAddr32Imm:
553 return expandLoadAddressImm(Inst, IDLoc, Instructions);
554 case Mips::LoadAddr32Reg:
555 return expandLoadAddressReg(Inst, IDLoc, Instructions);
559 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
560 SmallVectorImpl<MCInst> &Instructions) {
562 const MCOperand &ImmOp = Inst.getOperand(1);
563 assert(ImmOp.isImm() && "expected immediate operand kind");
564 const MCOperand &RegOp = Inst.getOperand(0);
565 assert(RegOp.isReg() && "expected register operand kind");
567 int ImmValue = ImmOp.getImm();
568 tmpInst.setLoc(IDLoc);
569 if (0 <= ImmValue && ImmValue <= 65535) {
570 // For 0 <= j <= 65535.
571 // li d,j => ori d,$zero,j
572 tmpInst.setOpcode(Mips::ORi);
573 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
574 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
575 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
576 Instructions.push_back(tmpInst);
577 } else if (ImmValue < 0 && ImmValue >= -32768) {
578 // For -32768 <= j < 0.
579 // li d,j => addiu d,$zero,j
580 tmpInst.setOpcode(Mips::ADDiu);
581 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
582 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
583 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
584 Instructions.push_back(tmpInst);
586 // For any other value of j that is representable as a 32-bit integer.
587 // li d,j => lui d,hi16(j)
589 tmpInst.setOpcode(Mips::LUi);
590 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
591 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
592 Instructions.push_back(tmpInst);
594 tmpInst.setOpcode(Mips::ORi);
595 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
596 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
597 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
598 tmpInst.setLoc(IDLoc);
599 Instructions.push_back(tmpInst);
603 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
604 SmallVectorImpl<MCInst> &Instructions) {
606 const MCOperand &ImmOp = Inst.getOperand(2);
607 assert(ImmOp.isImm() && "expected immediate operand kind");
608 const MCOperand &SrcRegOp = Inst.getOperand(1);
609 assert(SrcRegOp.isReg() && "expected register operand kind");
610 const MCOperand &DstRegOp = Inst.getOperand(0);
611 assert(DstRegOp.isReg() && "expected register operand kind");
612 int ImmValue = ImmOp.getImm();
613 if (-32768 <= ImmValue && ImmValue <= 65535) {
614 // For -32768 <= j <= 65535.
615 // la d,j(s) => addiu d,s,j
616 tmpInst.setOpcode(Mips::ADDiu);
617 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
618 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
619 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
620 Instructions.push_back(tmpInst);
622 // For any other value of j that is representable as a 32-bit integer.
623 // la d,j(s) => lui d,hi16(j)
626 tmpInst.setOpcode(Mips::LUi);
627 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
628 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
629 Instructions.push_back(tmpInst);
631 tmpInst.setOpcode(Mips::ORi);
632 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
633 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
634 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
635 Instructions.push_back(tmpInst);
637 tmpInst.setOpcode(Mips::ADDu);
638 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
639 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
640 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
641 Instructions.push_back(tmpInst);
645 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
646 SmallVectorImpl<MCInst> &Instructions) {
648 const MCOperand &ImmOp = Inst.getOperand(1);
649 assert(ImmOp.isImm() && "expected immediate operand kind");
650 const MCOperand &RegOp = Inst.getOperand(0);
651 assert(RegOp.isReg() && "expected register operand kind");
652 int ImmValue = ImmOp.getImm();
653 if (-32768 <= ImmValue && ImmValue <= 65535) {
654 // For -32768 <= j <= 65535.
655 // la d,j => addiu d,$zero,j
656 tmpInst.setOpcode(Mips::ADDiu);
657 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
658 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
659 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
660 Instructions.push_back(tmpInst);
662 // For any other value of j that is representable as a 32-bit integer.
663 // la d,j => lui d,hi16(j)
665 tmpInst.setOpcode(Mips::LUi);
666 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
667 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
668 Instructions.push_back(tmpInst);
670 tmpInst.setOpcode(Mips::ORi);
671 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
672 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
673 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
674 Instructions.push_back(tmpInst);
678 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
679 SmallVectorImpl<MCInst> &Instructions, bool isLoad, bool isImmOpnd) {
680 const MCSymbolRefExpr *SR;
682 unsigned ImmOffset, HiOffset, LoOffset;
683 const MCExpr *ExprOffset;
685 unsigned AtRegNum = getReg((isMips64()) ? Mips::GPR64RegClassID
686 : Mips::GPR32RegClassID, getATReg());
687 // 1st operand is either the source or destination register.
688 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
689 unsigned RegOpNum = Inst.getOperand(0).getReg();
690 // 2nd operand is the base register.
691 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
692 unsigned BaseRegNum = Inst.getOperand(1).getReg();
693 // 3rd operand is either an immediate or expression.
695 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
696 ImmOffset = Inst.getOperand(2).getImm();
697 LoOffset = ImmOffset & 0x0000ffff;
698 HiOffset = (ImmOffset & 0xffff0000) >> 16;
699 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
700 if (LoOffset & 0x8000)
703 ExprOffset = Inst.getOperand(2).getExpr();
704 // All instructions will have the same location.
705 TempInst.setLoc(IDLoc);
706 // 1st instruction in expansion is LUi. For load instruction we can use
707 // the dst register as a temporary if base and dst are different,
708 // but for stores we must use $at.
709 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
710 TempInst.setOpcode(Mips::LUi);
711 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
713 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
715 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
716 SR = static_cast<const MCSymbolRefExpr*>(ExprOffset);
717 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
718 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
720 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
722 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
723 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
726 // Add the instruction to the list.
727 Instructions.push_back(TempInst);
728 // Prepare TempInst for next instruction.
730 // Add temp register to base.
731 TempInst.setOpcode(Mips::ADDu);
732 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
733 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
734 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
735 Instructions.push_back(TempInst);
737 // And finaly, create original instruction with low part
738 // of offset and new base.
739 TempInst.setOpcode(Inst.getOpcode());
740 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
741 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
743 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
745 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
746 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
747 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
749 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
751 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
752 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
755 Instructions.push_back(TempInst);
760 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
761 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
762 MCStreamer &Out, unsigned &ErrorInfo,
763 bool MatchingInlineAsm) {
765 SmallVector<MCInst, 8> Instructions;
766 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
769 switch (MatchResult) {
772 case Match_Success: {
773 if (processInstruction(Inst, IDLoc, Instructions))
775 for (unsigned i = 0; i < Instructions.size(); i++)
776 Out.EmitInstruction(Instructions[i]);
779 case Match_MissingFeature:
780 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
782 case Match_InvalidOperand: {
783 SMLoc ErrorLoc = IDLoc;
784 if (ErrorInfo != ~0U) {
785 if (ErrorInfo >= Operands.size())
786 return Error(IDLoc, "too few operands for instruction");
788 ErrorLoc = ((MipsOperand*) Operands[ErrorInfo])->getStartLoc();
789 if (ErrorLoc == SMLoc())
793 return Error(ErrorLoc, "invalid operand for instruction");
795 case Match_MnemonicFail:
796 return Error(IDLoc, "invalid instruction");
801 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
807 CC = StringSwitch<unsigned>(Name)
841 // Although SGI documentation just cuts out t0-t3 for n32/n64,
842 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
843 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
844 if (isMips64() && 8 <= CC && CC <= 11)
847 if (CC == -1 && isMips64())
848 CC = StringSwitch<unsigned>(Name)
861 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
863 if (Name[0] == 'f') {
864 StringRef NumString = Name.substr(1);
866 if (NumString.getAsInteger(10, IntVal))
867 return -1; // This is not an integer.
868 if (IntVal > 31) // Maximum index for fpu register.
875 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
877 if (Name.startswith("fcc")) {
878 StringRef NumString = Name.substr(3);
880 if (NumString.getAsInteger(10, IntVal))
881 return -1; // This is not an integer.
882 if (IntVal > 7) // There are only 8 fcc registers.
889 int MipsAsmParser::matchACRegisterName(StringRef Name) {
891 if (Name.startswith("ac")) {
892 StringRef NumString = Name.substr(2);
894 if (NumString.getAsInteger(10, IntVal))
895 return -1; // This is not an integer.
896 if (IntVal > 3) // There are only 3 acc registers.
903 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
906 CC = matchCPURegisterName(Name);
908 return matchRegisterByNumber(CC, is64BitReg ? Mips::GPR64RegClassID
909 : Mips::GPR32RegClassID);
910 CC= matchFPURegisterName(Name);
911 //TODO: decide about fpu register class
912 return matchRegisterByNumber(CC, isFP64() ? Mips::FGR64RegClassID
913 : Mips::FGR32RegClassID);
916 int MipsAsmParser::regKindToRegClass(int RegKind) {
919 case MipsOperand::Kind_GPR32: return Mips::GPR32RegClassID;
920 case MipsOperand::Kind_GPR64: return Mips::GPR64RegClassID;
921 case MipsOperand::Kind_HWRegs: return Mips::HWRegsRegClassID;
922 case MipsOperand::Kind_FGR32Regs: return Mips::FGR32RegClassID;
923 case MipsOperand::Kind_FGRH32Regs: return Mips::FGRH32RegClassID;
924 case MipsOperand::Kind_FGR64Regs: return Mips::FGR64RegClassID;
925 case MipsOperand::Kind_AFGR64Regs: return Mips::AFGR64RegClassID;
926 case MipsOperand::Kind_CCRRegs: return Mips::CCRRegClassID;
927 case MipsOperand::Kind_ACC64DSP: return Mips::ACC64DSPRegClassID;
928 case MipsOperand::Kind_FCCRegs: return Mips::FCCRegClassID;
934 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
942 int MipsAsmParser::getATReg() {
943 return Options.getATRegNum();
946 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
947 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
950 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
952 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
955 return getReg(RegClass, RegNum);
958 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
959 const AsmToken &Tok = Parser.getTok();
962 if (Tok.is(AsmToken::Identifier)) {
963 std::string lowerCase = Tok.getString().lower();
964 RegNum = matchRegisterName(lowerCase, is64BitReg);
965 } else if (Tok.is(AsmToken::Integer))
966 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
967 is64BitReg ? Mips::GPR64RegClassID : Mips::GPR32RegClassID);
971 bool MipsAsmParser::tryParseRegisterOperand(
972 SmallVectorImpl<MCParsedAsmOperand*> &Operands, bool is64BitReg) {
974 SMLoc S = Parser.getTok().getLoc();
977 RegNo = tryParseRegister(is64BitReg);
981 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
982 Parser.getTok().getLoc()));
983 Parser.Lex(); // Eat register token.
987 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
988 StringRef Mnemonic) {
989 // Check if the current operand has a custom associated parser, if so, try to
990 // custom parse the operand, or fallback to the general approach.
991 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
992 if (ResTy == MatchOperand_Success)
994 // If there wasn't a custom match, try the generic matcher below. Otherwise,
995 // there was a match, but an error occurred, in which case, just return that
996 // the operand parsing failed.
997 if (ResTy == MatchOperand_ParseFail)
1000 switch (getLexer().getKind()) {
1002 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1004 case AsmToken::Dollar: {
1005 // Parse the register.
1006 SMLoc S = Parser.getTok().getLoc();
1007 Parser.Lex(); // Eat dollar token.
1008 // Parse the register operand.
1009 if (!tryParseRegisterOperand(Operands, isMips64())) {
1010 if (getLexer().is(AsmToken::LParen)) {
1011 // Check if it is indexed addressing operand.
1012 Operands.push_back(MipsOperand::CreateToken("(", S));
1013 Parser.Lex(); // Eat the parenthesis.
1014 if (getLexer().isNot(AsmToken::Dollar))
1017 Parser.Lex(); // Eat the dollar
1018 if (tryParseRegisterOperand(Operands, isMips64()))
1021 if (!getLexer().is(AsmToken::RParen))
1024 S = Parser.getTok().getLoc();
1025 Operands.push_back(MipsOperand::CreateToken(")", S));
1030 // Maybe it is a symbol reference.
1031 StringRef Identifier;
1032 if (Parser.parseIdentifier(Identifier))
1035 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1037 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1039 // Otherwise create a symbol reference.
1040 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
1043 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1046 case AsmToken::Identifier:
1047 // Look for the existing symbol, we should check if
1048 // we need to assigne the propper RegisterKind.
1049 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
1051 // Else drop to expression parsing.
1052 case AsmToken::LParen:
1053 case AsmToken::Minus:
1054 case AsmToken::Plus:
1055 case AsmToken::Integer:
1056 case AsmToken::String: {
1057 // Quoted label names.
1058 const MCExpr *IdVal;
1059 SMLoc S = Parser.getTok().getLoc();
1060 if (getParser().parseExpression(IdVal))
1062 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1063 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1066 case AsmToken::Percent: {
1067 // It is a symbol reference or constant expression.
1068 const MCExpr *IdVal;
1069 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1070 if (parseRelocOperand(IdVal))
1073 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1075 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1077 } // case AsmToken::Percent
1078 } // switch(getLexer().getKind())
1082 const MCExpr* MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1083 StringRef RelocStr) {
1085 // Check the type of the expression.
1086 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1087 // It's a constant, evaluate lo or hi value.
1088 if (RelocStr == "lo") {
1089 short Val = MCE->getValue();
1090 Res = MCConstantExpr::Create(Val, getContext());
1091 } else if (RelocStr == "hi") {
1092 int Val = MCE->getValue();
1093 int LoSign = Val & 0x8000;
1094 Val = (Val & 0xffff0000) >> 16;
1095 // Lower part is treated as a signed int, so if it is negative
1096 // we must add 1 to the hi part to compensate.
1099 Res = MCConstantExpr::Create(Val, getContext());
1101 llvm_unreachable("Invalid RelocStr value");
1106 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1107 // It's a symbol, create a symbolic expression from the symbol.
1108 StringRef Symbol = MSRE->getSymbol().getName();
1109 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1110 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1114 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1115 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1116 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1117 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1121 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1122 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1123 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1126 // Just return the original expression.
1130 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1132 switch (Expr->getKind()) {
1133 case MCExpr::Constant:
1135 case MCExpr::SymbolRef:
1136 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1137 case MCExpr::Binary:
1138 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1139 if (!isEvaluated(BE->getLHS()))
1141 return isEvaluated(BE->getRHS());
1144 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1151 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1152 Parser.Lex(); // Eat the % token.
1153 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1154 if (Tok.isNot(AsmToken::Identifier))
1157 std::string Str = Tok.getIdentifier().str();
1159 Parser.Lex(); // Eat the identifier.
1160 // Now make an expression from the rest of the operand.
1161 const MCExpr *IdVal;
1164 if (getLexer().getKind() == AsmToken::LParen) {
1166 Parser.Lex(); // Eat the '(' token.
1167 if (getLexer().getKind() == AsmToken::Percent) {
1168 Parser.Lex(); // Eat the % token.
1169 const AsmToken &nextTok = Parser.getTok();
1170 if (nextTok.isNot(AsmToken::Identifier))
1173 Str += nextTok.getIdentifier();
1174 Parser.Lex(); // Eat the identifier.
1175 if (getLexer().getKind() != AsmToken::LParen)
1180 if (getParser().parseParenExpression(IdVal, EndLoc))
1183 while (getLexer().getKind() == AsmToken::RParen)
1184 Parser.Lex(); // Eat the ')' token.
1187 return true; // Parenthesis must follow the relocation operand.
1189 Res = evaluateRelocExpr(IdVal, Str);
1193 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1195 StartLoc = Parser.getTok().getLoc();
1196 RegNo = tryParseRegister(isMips64());
1197 EndLoc = Parser.getTok().getLoc();
1198 return (RegNo == (unsigned) -1);
1201 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1205 while (getLexer().getKind() == AsmToken::LParen)
1208 switch (getLexer().getKind()) {
1211 case AsmToken::Identifier:
1212 case AsmToken::LParen:
1213 case AsmToken::Integer:
1214 case AsmToken::Minus:
1215 case AsmToken::Plus:
1217 Result = getParser().parseParenExpression(Res, S);
1219 Result = (getParser().parseExpression(Res));
1220 while (getLexer().getKind() == AsmToken::RParen)
1223 case AsmToken::Percent:
1224 Result = parseRelocOperand(Res);
1229 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1230 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
1232 const MCExpr *IdVal = 0;
1234 bool isParenExpr = false;
1235 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1236 // First operand is the offset.
1237 S = Parser.getTok().getLoc();
1239 if (getLexer().getKind() == AsmToken::LParen) {
1244 if (getLexer().getKind() != AsmToken::Dollar) {
1245 if (parseMemOffset(IdVal, isParenExpr))
1246 return MatchOperand_ParseFail;
1248 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1249 if (Tok.isNot(AsmToken::LParen)) {
1250 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
1251 if (Mnemonic->getToken() == "la") {
1252 SMLoc E = SMLoc::getFromPointer(
1253 Parser.getTok().getLoc().getPointer() - 1);
1254 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1255 return MatchOperand_Success;
1257 if (Tok.is(AsmToken::EndOfStatement)) {
1258 SMLoc E = SMLoc::getFromPointer(
1259 Parser.getTok().getLoc().getPointer() - 1);
1261 // Zero register assumed, add a memory operand with ZERO as its base.
1262 Operands.push_back(MipsOperand::CreateMem(isMips64() ? Mips::ZERO_64
1265 return MatchOperand_Success;
1267 Error(Parser.getTok().getLoc(), "'(' expected");
1268 return MatchOperand_ParseFail;
1271 Parser.Lex(); // Eat the '(' token.
1274 Res = parseRegs(Operands, isMips64()? (int) MipsOperand::Kind_GPR64:
1275 (int) MipsOperand::Kind_GPR32);
1276 if (Res != MatchOperand_Success)
1279 if (Parser.getTok().isNot(AsmToken::RParen)) {
1280 Error(Parser.getTok().getLoc(), "')' expected");
1281 return MatchOperand_ParseFail;
1284 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1286 Parser.Lex(); // Eat the ')' token.
1289 IdVal = MCConstantExpr::Create(0, getContext());
1291 // Replace the register operand with the memory operand.
1292 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1293 int RegNo = op->getReg();
1294 // Remove the register from the operands.
1295 Operands.pop_back();
1296 // Add the memory operand.
1297 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1299 if (IdVal->EvaluateAsAbsolute(Imm))
1300 IdVal = MCConstantExpr::Create(Imm, getContext());
1301 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1302 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1306 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1308 return MatchOperand_Success;
1312 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1314 // If the first token is not '$' we have an error.
1315 if (Parser.getTok().isNot(AsmToken::Dollar))
1318 SMLoc S = Parser.getTok().getLoc();
1320 AsmToken::TokenKind TkKind = getLexer().getKind();
1323 if (TkKind == AsmToken::Integer) {
1324 Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
1325 regKindToRegClass(RegKind));
1328 } else if (TkKind == AsmToken::Identifier) {
1329 if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
1331 Reg = getReg(regKindToRegClass(RegKind), Reg);
1336 MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
1337 Op->setRegKind((MipsOperand::RegisterKind)RegKind);
1338 Operands.push_back(Op);
1343 MipsAsmParser::OperandMatchResultTy
1344 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1345 MipsOperand::RegisterKind RegKind = isN64() ? MipsOperand::Kind_GPR64 :
1346 MipsOperand::Kind_GPR32;
1348 // Parse index register.
1349 if (!parsePtrReg(Operands, RegKind))
1350 return MatchOperand_NoMatch;
1353 if (Parser.getTok().isNot(AsmToken::LParen))
1354 return MatchOperand_NoMatch;
1356 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1359 // Parse base register.
1360 if (!parsePtrReg(Operands, RegKind))
1361 return MatchOperand_NoMatch;
1364 if (Parser.getTok().isNot(AsmToken::RParen))
1365 return MatchOperand_NoMatch;
1367 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1370 return MatchOperand_Success;
1373 MipsAsmParser::OperandMatchResultTy
1374 MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1376 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1377 if (getLexer().getKind() == AsmToken::Identifier
1378 && !hasConsumedDollar) {
1379 if (searchSymbolAlias(Operands, Kind))
1380 return MatchOperand_Success;
1381 return MatchOperand_NoMatch;
1383 SMLoc S = Parser.getTok().getLoc();
1384 // If the first token is not '$', we have an error.
1385 if (Parser.getTok().isNot(AsmToken::Dollar) && !hasConsumedDollar)
1386 return MatchOperand_NoMatch;
1387 if (!hasConsumedDollar) {
1388 Parser.Lex(); // Eat the '$'
1389 hasConsumedDollar = true;
1391 if (getLexer().getKind() == AsmToken::Identifier) {
1393 std::string RegName = Parser.getTok().getString().lower();
1394 // Match register by name
1396 case MipsOperand::Kind_GPR32:
1397 case MipsOperand::Kind_GPR64:
1398 RegNum = matchCPURegisterName(RegName);
1400 case MipsOperand::Kind_AFGR64Regs:
1401 case MipsOperand::Kind_FGR64Regs:
1402 case MipsOperand::Kind_FGR32Regs:
1403 case MipsOperand::Kind_FGRH32Regs:
1404 RegNum = matchFPURegisterName(RegName);
1405 if (RegKind == MipsOperand::Kind_AFGR64Regs)
1408 case MipsOperand::Kind_FCCRegs:
1409 RegNum = matchFCCRegisterName(RegName);
1411 case MipsOperand::Kind_ACC64DSP:
1412 RegNum = matchACRegisterName(RegName);
1414 default: break; // No match, value is set to -1.
1416 // No match found, return _NoMatch to give a chance to other round.
1418 return MatchOperand_NoMatch;
1420 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1422 return MatchOperand_NoMatch;
1424 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S,
1425 Parser.getTok().getLoc());
1426 Op->setRegKind(Kind);
1427 Operands.push_back(Op);
1428 hasConsumedDollar = false;
1429 Parser.Lex(); // Eat the register name.
1430 return MatchOperand_Success;
1431 } else if (getLexer().getKind() == AsmToken::Integer) {
1432 unsigned RegNum = Parser.getTok().getIntVal();
1433 if (Kind == MipsOperand::Kind_HWRegs) {
1435 return MatchOperand_NoMatch;
1436 // Only hwreg 29 is supported, found at index 0.
1439 int Reg = matchRegisterByNumber(RegNum, regKindToRegClass(Kind));
1441 return MatchOperand_NoMatch;
1442 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1443 Op->setRegKind(Kind);
1444 Operands.push_back(Op);
1445 hasConsumedDollar = false;
1446 Parser.Lex(); // Eat the register number.
1447 if ((RegKind == MipsOperand::Kind_GPR32)
1448 && (getLexer().is(AsmToken::LParen))) {
1449 // Check if it is indexed addressing operand.
1450 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1451 Parser.Lex(); // Eat the parenthesis.
1452 if (parseRegs(Operands,RegKind) != MatchOperand_Success)
1453 return MatchOperand_NoMatch;
1454 if (getLexer().isNot(AsmToken::RParen))
1455 return MatchOperand_NoMatch;
1456 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1459 return MatchOperand_Success;
1461 return MatchOperand_NoMatch;
1464 MipsAsmParser::OperandMatchResultTy
1465 MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1468 return MatchOperand_NoMatch;
1469 return parseRegs(Operands, (int) MipsOperand::Kind_GPR64);
1472 MipsAsmParser::OperandMatchResultTy
1473 MipsAsmParser::parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1474 return parseRegs(Operands, (int) MipsOperand::Kind_GPR32);
1477 MipsAsmParser::OperandMatchResultTy
1478 MipsAsmParser::parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1481 return MatchOperand_NoMatch;
1482 return parseRegs(Operands, (int) MipsOperand::Kind_AFGR64Regs);
1485 MipsAsmParser::OperandMatchResultTy
1486 MipsAsmParser::parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1488 return MatchOperand_NoMatch;
1489 return parseRegs(Operands, (int) MipsOperand::Kind_FGR64Regs);
1492 MipsAsmParser::OperandMatchResultTy
1493 MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1494 return parseRegs(Operands, (int) MipsOperand::Kind_FGR32Regs);
1497 MipsAsmParser::OperandMatchResultTy
1498 MipsAsmParser::parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1499 return parseRegs(Operands, (int) MipsOperand::Kind_FGRH32Regs);
1502 MipsAsmParser::OperandMatchResultTy
1503 MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1504 return parseRegs(Operands, (int) MipsOperand::Kind_FCCRegs);
1507 MipsAsmParser::OperandMatchResultTy
1508 MipsAsmParser::parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1509 return parseRegs(Operands, (int) MipsOperand::Kind_ACC64DSP);
1512 MipsAsmParser::OperandMatchResultTy
1513 MipsAsmParser::parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1514 // If the first token is not '$' we have an error.
1515 if (Parser.getTok().isNot(AsmToken::Dollar))
1516 return MatchOperand_NoMatch;
1518 SMLoc S = Parser.getTok().getLoc();
1519 Parser.Lex(); // Eat the '$'
1521 const AsmToken &Tok = Parser.getTok(); // Get next token.
1523 if (Tok.isNot(AsmToken::Identifier))
1524 return MatchOperand_NoMatch;
1526 if (!Tok.getIdentifier().startswith("ac"))
1527 return MatchOperand_NoMatch;
1529 StringRef NumString = Tok.getIdentifier().substr(2);
1532 if (NumString.getAsInteger(10, IntVal))
1533 return MatchOperand_NoMatch;
1535 unsigned Reg = matchRegisterByNumber(IntVal, Mips::LO32DSPRegClassID);
1537 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1538 Op->setRegKind(MipsOperand::Kind_LO32DSP);
1539 Operands.push_back(Op);
1541 Parser.Lex(); // Eat the register number.
1542 return MatchOperand_Success;
1545 MipsAsmParser::OperandMatchResultTy
1546 MipsAsmParser::parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1547 // If the first token is not '$' we have an error.
1548 if (Parser.getTok().isNot(AsmToken::Dollar))
1549 return MatchOperand_NoMatch;
1551 SMLoc S = Parser.getTok().getLoc();
1552 Parser.Lex(); // Eat the '$'
1554 const AsmToken &Tok = Parser.getTok(); // Get next token.
1556 if (Tok.isNot(AsmToken::Identifier))
1557 return MatchOperand_NoMatch;
1559 if (!Tok.getIdentifier().startswith("ac"))
1560 return MatchOperand_NoMatch;
1562 StringRef NumString = Tok.getIdentifier().substr(2);
1565 if (NumString.getAsInteger(10, IntVal))
1566 return MatchOperand_NoMatch;
1568 unsigned Reg = matchRegisterByNumber(IntVal, Mips::HI32DSPRegClassID);
1570 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1571 Op->setRegKind(MipsOperand::Kind_HI32DSP);
1572 Operands.push_back(Op);
1574 Parser.Lex(); // Eat the register number.
1575 return MatchOperand_Success;
1578 bool MipsAsmParser::searchSymbolAlias(
1579 SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {
1581 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1583 SMLoc S = Parser.getTok().getLoc();
1585 if (Sym->isVariable())
1586 Expr = Sym->getVariableValue();
1589 if (Expr->getKind() == MCExpr::SymbolRef) {
1590 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind) RegKind;
1591 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
1592 const StringRef DefSymbol = Ref->getSymbol().getName();
1593 if (DefSymbol.startswith("$")) {
1595 APInt IntVal(32, -1);
1596 if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
1597 RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
1599 ? Mips::GPR64RegClassID
1600 : Mips::GPR32RegClassID);
1602 // Lookup for the register with the corresponding name.
1604 case MipsOperand::Kind_AFGR64Regs:
1605 case MipsOperand::Kind_FGR64Regs:
1606 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1608 case MipsOperand::Kind_FGR32Regs:
1609 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1611 case MipsOperand::Kind_GPR64:
1612 case MipsOperand::Kind_GPR32:
1614 RegNum = matchCPURegisterName(DefSymbol.substr(1));
1618 RegNum = getReg(regKindToRegClass(Kind), RegNum);
1622 MipsOperand *op = MipsOperand::CreateReg(RegNum, S,
1623 Parser.getTok().getLoc());
1624 op->setRegKind(Kind);
1625 Operands.push_back(op);
1629 } else if (Expr->getKind() == MCExpr::Constant) {
1631 const MCConstantExpr *Const = static_cast<const MCConstantExpr*>(Expr);
1632 MipsOperand *op = MipsOperand::CreateImm(Const, S,
1633 Parser.getTok().getLoc());
1634 Operands.push_back(op);
1641 MipsAsmParser::OperandMatchResultTy
1642 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1643 return parseRegs(Operands, (int) MipsOperand::Kind_HWRegs);
1646 MipsAsmParser::OperandMatchResultTy
1647 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1648 return parseRegs(Operands, (int) MipsOperand::Kind_CCRRegs);
1651 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1653 MCSymbolRefExpr::VariantKind VK
1654 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1655 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1656 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1657 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1658 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1659 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1660 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1661 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1662 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1663 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1664 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1665 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1666 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1667 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1668 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1669 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1670 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1671 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1672 .Default(MCSymbolRefExpr::VK_None);
1677 bool MipsAsmParser::
1678 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1679 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1680 // Check if we have valid mnemonic
1681 if (!mnemonicIsValid(Name, 0)) {
1682 Parser.eatToEndOfStatement();
1683 return Error(NameLoc, "Unknown instruction");
1685 // First operand in MCInst is instruction mnemonic.
1686 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
1688 // Read the remaining operands.
1689 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1690 // Read the first operand.
1691 if (ParseOperand(Operands, Name)) {
1692 SMLoc Loc = getLexer().getLoc();
1693 Parser.eatToEndOfStatement();
1694 return Error(Loc, "unexpected token in argument list");
1697 while (getLexer().is(AsmToken::Comma)) {
1698 Parser.Lex(); // Eat the comma.
1699 // Parse and remember the operand.
1700 if (ParseOperand(Operands, Name)) {
1701 SMLoc Loc = getLexer().getLoc();
1702 Parser.eatToEndOfStatement();
1703 return Error(Loc, "unexpected token in argument list");
1707 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1708 SMLoc Loc = getLexer().getLoc();
1709 Parser.eatToEndOfStatement();
1710 return Error(Loc, "unexpected token in argument list");
1712 Parser.Lex(); // Consume the EndOfStatement.
1716 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
1717 SMLoc Loc = getLexer().getLoc();
1718 Parser.eatToEndOfStatement();
1719 return Error(Loc, ErrorMsg);
1722 bool MipsAsmParser::parseSetNoAtDirective() {
1723 // Line should look like: ".set noat".
1725 Options.setATReg(0);
1728 // If this is not the end of the statement, report an error.
1729 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1730 reportParseError("unexpected token in statement");
1733 Parser.Lex(); // Consume the EndOfStatement.
1737 bool MipsAsmParser::parseSetAtDirective() {
1738 // Line can be .set at - defaults to $1
1742 if (getLexer().is(AsmToken::EndOfStatement)) {
1743 Options.setATReg(1);
1744 Parser.Lex(); // Consume the EndOfStatement.
1746 } else if (getLexer().is(AsmToken::Equal)) {
1747 getParser().Lex(); // Eat the '='.
1748 if (getLexer().isNot(AsmToken::Dollar)) {
1749 reportParseError("unexpected token in statement");
1752 Parser.Lex(); // Eat the '$'.
1753 const AsmToken &Reg = Parser.getTok();
1754 if (Reg.is(AsmToken::Identifier)) {
1755 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
1756 } else if (Reg.is(AsmToken::Integer)) {
1757 AtRegNo = Reg.getIntVal();
1759 reportParseError("unexpected token in statement");
1763 if (AtRegNo < 1 || AtRegNo > 31) {
1764 reportParseError("unexpected token in statement");
1768 if (!Options.setATReg(AtRegNo)) {
1769 reportParseError("unexpected token in statement");
1772 getParser().Lex(); // Eat the register.
1774 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1775 reportParseError("unexpected token in statement");
1778 Parser.Lex(); // Consume the EndOfStatement.
1781 reportParseError("unexpected token in statement");
1786 bool MipsAsmParser::parseSetReorderDirective() {
1788 // If this is not the end of the statement, report an error.
1789 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1790 reportParseError("unexpected token in statement");
1793 Options.setReorder();
1794 Parser.Lex(); // Consume the EndOfStatement.
1798 bool MipsAsmParser::parseSetNoReorderDirective() {
1800 // If this is not the end of the statement, report an error.
1801 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1802 reportParseError("unexpected token in statement");
1805 Options.setNoreorder();
1806 Parser.Lex(); // Consume the EndOfStatement.
1810 bool MipsAsmParser::parseSetMacroDirective() {
1812 // If this is not the end of the statement, report an error.
1813 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1814 reportParseError("unexpected token in statement");
1818 Parser.Lex(); // Consume the EndOfStatement.
1822 bool MipsAsmParser::parseSetNoMacroDirective() {
1824 // If this is not the end of the statement, report an error.
1825 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1826 reportParseError("`noreorder' must be set before `nomacro'");
1829 if (Options.isReorder()) {
1830 reportParseError("`noreorder' must be set before `nomacro'");
1833 Options.setNomacro();
1834 Parser.Lex(); // Consume the EndOfStatement.
1838 bool MipsAsmParser::parseSetAssignment() {
1840 const MCExpr *Value;
1842 if (Parser.parseIdentifier(Name))
1843 reportParseError("expected identifier after .set");
1845 if (getLexer().isNot(AsmToken::Comma))
1846 return reportParseError("unexpected token in .set directive");
1849 if (getLexer().is(AsmToken::Dollar)) {
1851 SMLoc DollarLoc = getLexer().getLoc();
1852 // Consume the dollar sign, and check for a following identifier.
1854 // We have a '$' followed by something, make sure they are adjacent.
1855 if (DollarLoc.getPointer() + 1 != getTok().getLoc().getPointer())
1857 StringRef Res = StringRef(DollarLoc.getPointer(),
1858 getTok().getEndLoc().getPointer() - DollarLoc.getPointer());
1859 Symbol = getContext().GetOrCreateSymbol(Res);
1861 Value = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
1863 } else if (Parser.parseExpression(Value))
1864 return reportParseError("expected valid expression after comma");
1866 // Check if the Name already exists as a symbol.
1867 MCSymbol *Sym = getContext().LookupSymbol(Name);
1869 return reportParseError("symbol already defined");
1870 Sym = getContext().GetOrCreateSymbol(Name);
1871 Sym->setVariableValue(Value);
1876 bool MipsAsmParser::parseDirectiveSet() {
1878 // Get the next token.
1879 const AsmToken &Tok = Parser.getTok();
1881 if (Tok.getString() == "noat") {
1882 return parseSetNoAtDirective();
1883 } else if (Tok.getString() == "at") {
1884 return parseSetAtDirective();
1885 } else if (Tok.getString() == "reorder") {
1886 return parseSetReorderDirective();
1887 } else if (Tok.getString() == "noreorder") {
1888 return parseSetNoReorderDirective();
1889 } else if (Tok.getString() == "macro") {
1890 return parseSetMacroDirective();
1891 } else if (Tok.getString() == "nomacro") {
1892 return parseSetNoMacroDirective();
1893 } else if (Tok.getString() == "nomips16") {
1894 // Ignore this directive for now.
1895 Parser.eatToEndOfStatement();
1897 } else if (Tok.getString() == "nomicromips") {
1898 // Ignore this directive for now.
1899 Parser.eatToEndOfStatement();
1902 // It is just an identifier, look for an assignment.
1903 parseSetAssignment();
1910 /// parseDirectiveWord
1911 /// ::= .word [ expression (, expression)* ]
1912 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
1913 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1915 const MCExpr *Value;
1916 if (getParser().parseExpression(Value))
1919 getParser().getStreamer().EmitValue(Value, Size);
1921 if (getLexer().is(AsmToken::EndOfStatement))
1924 // FIXME: Improve diagnostic.
1925 if (getLexer().isNot(AsmToken::Comma))
1926 return Error(L, "unexpected token in directive");
1935 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
1937 StringRef IDVal = DirectiveID.getString();
1939 if (IDVal == ".ent") {
1940 // Ignore this directive for now.
1945 if (IDVal == ".end") {
1946 // Ignore this directive for now.
1951 if (IDVal == ".frame") {
1952 // Ignore this directive for now.
1953 Parser.eatToEndOfStatement();
1957 if (IDVal == ".set") {
1958 return parseDirectiveSet();
1961 if (IDVal == ".fmask") {
1962 // Ignore this directive for now.
1963 Parser.eatToEndOfStatement();
1967 if (IDVal == ".mask") {
1968 // Ignore this directive for now.
1969 Parser.eatToEndOfStatement();
1973 if (IDVal == ".gpword") {
1974 // Ignore this directive for now.
1975 Parser.eatToEndOfStatement();
1979 if (IDVal == ".word") {
1980 parseDirectiveWord(4, DirectiveID.getLoc());
1987 extern "C" void LLVMInitializeMipsAsmParser() {
1988 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
1989 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
1990 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
1991 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
1994 #define GET_REGISTER_MATCHER
1995 #define GET_MATCHER_IMPLEMENTATION
1996 #include "MipsGenAsmMatcher.inc"