1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "MipsTargetStreamer.h"
13 #include "llvm/ADT/APInt.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
20 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/MC/MCSymbol.h"
23 #include "llvm/MC/MCTargetAsmParser.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/TargetRegistry.h"
34 class MipsAssemblerOptions {
36 MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {}
38 unsigned getATRegNum() { return aTReg; }
39 bool setATReg(unsigned Reg);
41 bool isReorder() { return reorder; }
42 void setReorder() { reorder = true; }
43 void setNoreorder() { reorder = false; }
45 bool isMacro() { return macro; }
46 void setMacro() { macro = true; }
47 void setNomacro() { macro = false; }
57 class MipsAsmParser : public MCTargetAsmParser {
59 MipsTargetStreamer &getTargetStreamer() {
60 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
61 return static_cast<MipsTargetStreamer &>(TS);
66 MipsAssemblerOptions Options;
67 bool hasConsumedDollar;
69 #define GET_ASSEMBLER_HEADER
70 #include "MipsGenAsmMatcher.inc"
72 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
73 SmallVectorImpl<MCParsedAsmOperand *> &Operands,
74 MCStreamer &Out, unsigned &ErrorInfo,
75 bool MatchingInlineAsm);
77 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
79 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
81 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
83 bool ParseDirective(AsmToken DirectiveID);
85 MipsAsmParser::OperandMatchResultTy
86 parseRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands, int RegKind);
88 MipsAsmParser::OperandMatchResultTy
89 parseMSARegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands, int RegKind);
91 MipsAsmParser::OperandMatchResultTy
92 parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
95 MipsAsmParser::OperandMatchResultTy
96 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
98 bool parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
101 MipsAsmParser::OperandMatchResultTy
102 parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
104 MipsAsmParser::OperandMatchResultTy
105 parseGPR32(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
107 MipsAsmParser::OperandMatchResultTy
108 parseGPR64(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
110 MipsAsmParser::OperandMatchResultTy
111 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
113 MipsAsmParser::OperandMatchResultTy
114 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
116 MipsAsmParser::OperandMatchResultTy
117 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
119 MipsAsmParser::OperandMatchResultTy
120 parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
122 MipsAsmParser::OperandMatchResultTy
123 parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
125 MipsAsmParser::OperandMatchResultTy
126 parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
128 MipsAsmParser::OperandMatchResultTy
129 parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
131 MipsAsmParser::OperandMatchResultTy
132 parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
134 MipsAsmParser::OperandMatchResultTy
135 parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
137 MipsAsmParser::OperandMatchResultTy
138 parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
140 MipsAsmParser::OperandMatchResultTy
141 parseCOP2(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
143 MipsAsmParser::OperandMatchResultTy
144 parseMSA128BRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
146 MipsAsmParser::OperandMatchResultTy
147 parseMSA128HRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
149 MipsAsmParser::OperandMatchResultTy
150 parseMSA128WRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
152 MipsAsmParser::OperandMatchResultTy
153 parseMSA128DRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
155 MipsAsmParser::OperandMatchResultTy
156 parseMSA128CtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
158 MipsAsmParser::OperandMatchResultTy
159 parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
161 MipsAsmParser::OperandMatchResultTy
162 parseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
164 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
167 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &,
170 int tryParseRegister(bool is64BitReg);
172 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
175 bool needsExpansion(MCInst &Inst);
177 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
178 SmallVectorImpl<MCInst> &Instructions);
179 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
180 SmallVectorImpl<MCInst> &Instructions);
181 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
182 SmallVectorImpl<MCInst> &Instructions);
183 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
184 SmallVectorImpl<MCInst> &Instructions);
185 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
186 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
188 bool reportParseError(StringRef ErrorMsg);
190 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
191 bool parseRelocOperand(const MCExpr *&Res);
193 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
195 bool isEvaluated(const MCExpr *Expr);
196 bool parseDirectiveSet();
197 bool parseDirectiveMipsHackELFFlags();
198 bool parseDirectiveOption();
200 bool parseSetAtDirective();
201 bool parseSetNoAtDirective();
202 bool parseSetMacroDirective();
203 bool parseSetNoMacroDirective();
204 bool parseSetReorderDirective();
205 bool parseSetNoReorderDirective();
206 bool parseSetMips16Directive();
207 bool parseSetNoMips16Directive();
209 bool parseSetAssignment();
211 bool parseDirectiveWord(unsigned Size, SMLoc L);
212 bool parseDirectiveGpWord();
214 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
216 bool isMips64() const {
217 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
220 bool isFP64() const {
221 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
224 bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
226 bool isMicroMips() const {
227 return STI.getFeatureBits() & Mips::FeatureMicroMips;
230 int matchRegisterName(StringRef Symbol, bool is64BitReg);
232 int matchCPURegisterName(StringRef Symbol);
234 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
236 int matchFPURegisterName(StringRef Name);
238 int matchFCCRegisterName(StringRef Name);
240 int matchACRegisterName(StringRef Name);
242 int matchMSA128RegisterName(StringRef Name);
244 int matchMSA128CtrlRegisterName(StringRef Name);
246 int regKindToRegClass(int RegKind);
248 unsigned getReg(int RC, int RegNo);
252 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
253 SmallVectorImpl<MCInst> &Instructions);
255 // Helper function that checks if the value of a vector index is within the
256 // boundaries of accepted values for each RegisterKind
257 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
258 bool validateMSAIndex(int Val, int RegKind);
261 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
262 const MCInstrInfo &MII)
263 : MCTargetAsmParser(), STI(sti), Parser(parser),
264 hasConsumedDollar(false) {
265 // Initialize the set of available features.
266 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
269 MCAsmParser &getParser() const { return Parser; }
270 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
276 /// MipsOperand - Instances of this class represent a parsed Mips machine
278 class MipsOperand : public MCParsedAsmOperand {
316 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
344 SMLoc StartLoc, EndLoc;
347 void addRegOperands(MCInst &Inst, unsigned N) const {
348 assert(N == 1 && "Invalid number of operands!");
349 Inst.addOperand(MCOperand::CreateReg(getReg()));
352 void addPtrRegOperands(MCInst &Inst, unsigned N) const {
353 assert(N == 1 && "Invalid number of operands!");
354 Inst.addOperand(MCOperand::CreateReg(getPtrReg()));
357 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
358 // Add as immediate when possible. Null MCExpr = 0.
360 Inst.addOperand(MCOperand::CreateImm(0));
361 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
362 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
364 Inst.addOperand(MCOperand::CreateExpr(Expr));
367 void addImmOperands(MCInst &Inst, unsigned N) const {
368 assert(N == 1 && "Invalid number of operands!");
369 const MCExpr *Expr = getImm();
373 void addMemOperands(MCInst &Inst, unsigned N) const {
374 assert(N == 2 && "Invalid number of operands!");
376 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
378 const MCExpr *Expr = getMemOff();
382 bool isReg() const { return Kind == k_Register; }
383 bool isImm() const { return Kind == k_Immediate; }
384 bool isToken() const { return Kind == k_Token; }
385 bool isMem() const { return Kind == k_Memory; }
386 bool isPtrReg() const { return Kind == k_PtrReg; }
387 bool isInvNum() const { return Kind == k_Immediate; }
388 bool isLSAImm() const { return Kind == k_LSAImm; }
390 StringRef getToken() const {
391 assert(Kind == k_Token && "Invalid access!");
392 return StringRef(Tok.Data, Tok.Length);
395 unsigned getReg() const {
396 assert((Kind == k_Register) && "Invalid access!");
400 unsigned getPtrReg() const {
401 assert((Kind == k_PtrReg) && "Invalid access!");
405 void setRegKind(RegisterKind RegKind) {
406 assert((Kind == k_Register || Kind == k_PtrReg) && "Invalid access!");
410 const MCExpr *getImm() const {
411 assert((Kind == k_Immediate || Kind == k_LSAImm) && "Invalid access!");
415 unsigned getMemBase() const {
416 assert((Kind == k_Memory) && "Invalid access!");
420 const MCExpr *getMemOff() const {
421 assert((Kind == k_Memory) && "Invalid access!");
425 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
426 MipsOperand *Op = new MipsOperand(k_Token);
427 Op->Tok.Data = Str.data();
428 Op->Tok.Length = Str.size();
434 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
435 MipsOperand *Op = new MipsOperand(k_Register);
436 Op->Reg.RegNum = RegNum;
442 static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) {
443 MipsOperand *Op = new MipsOperand(k_PtrReg);
444 Op->Reg.RegNum = RegNum;
450 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
451 MipsOperand *Op = new MipsOperand(k_Immediate);
458 static MipsOperand *CreateLSAImm(const MCExpr *Val, SMLoc S, SMLoc E) {
459 MipsOperand *Op = new MipsOperand(k_LSAImm);
466 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
468 MipsOperand *Op = new MipsOperand(k_Memory);
476 bool isGPR32Asm() const {
477 return Kind == k_Register && Reg.Kind == Kind_GPR32;
479 void addRegAsmOperands(MCInst &Inst, unsigned N) const {
480 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
483 bool isGPR64Asm() const {
484 return Kind == k_Register && Reg.Kind == Kind_GPR64;
487 bool isHWRegsAsm() const {
488 assert((Kind == k_Register) && "Invalid access!");
489 return Reg.Kind == Kind_HWRegs;
492 bool isCCRAsm() const {
493 assert((Kind == k_Register) && "Invalid access!");
494 return Reg.Kind == Kind_CCRRegs;
497 bool isAFGR64Asm() const {
498 return Kind == k_Register && Reg.Kind == Kind_AFGR64Regs;
501 bool isFGR64Asm() const {
502 return Kind == k_Register && Reg.Kind == Kind_FGR64Regs;
505 bool isFGR32Asm() const {
506 return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
509 bool isFGRH32Asm() const {
510 return (Kind == k_Register) && Reg.Kind == Kind_FGRH32Regs;
513 bool isFCCRegsAsm() const {
514 return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
517 bool isACC64DSPAsm() const {
518 return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
521 bool isLO32DSPAsm() const {
522 return Kind == k_Register && Reg.Kind == Kind_LO32DSP;
525 bool isHI32DSPAsm() const {
526 return Kind == k_Register && Reg.Kind == Kind_HI32DSP;
529 bool isCOP2Asm() const { return Kind == k_Register && Reg.Kind == Kind_COP2; }
531 bool isMSA128BAsm() const {
532 return Kind == k_Register && Reg.Kind == Kind_MSA128BRegs;
535 bool isMSA128HAsm() const {
536 return Kind == k_Register && Reg.Kind == Kind_MSA128HRegs;
539 bool isMSA128WAsm() const {
540 return Kind == k_Register && Reg.Kind == Kind_MSA128WRegs;
543 bool isMSA128DAsm() const {
544 return Kind == k_Register && Reg.Kind == Kind_MSA128DRegs;
547 bool isMSA128CRAsm() const {
548 return Kind == k_Register && Reg.Kind == Kind_MSA128CtrlRegs;
551 /// getStartLoc - Get the location of the first token of this operand.
552 SMLoc getStartLoc() const { return StartLoc; }
553 /// getEndLoc - Get the location of the last token of this operand.
554 SMLoc getEndLoc() const { return EndLoc; }
556 virtual void print(raw_ostream &OS) const {
557 llvm_unreachable("unimplemented!");
559 }; // class MipsOperand
563 extern const MCInstrDesc MipsInsts[];
565 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
566 return MipsInsts[Opcode];
569 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
570 SmallVectorImpl<MCInst> &Instructions) {
571 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
574 if (MCID.isBranch() || MCID.isCall()) {
575 const unsigned Opcode = Inst.getOpcode();
583 assert (MCID.getNumOperands() == 3 && "unexpected number of operands");
584 Offset = Inst.getOperand(2);
586 break; // We'll deal with this situation later on when applying fixups.
587 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
588 return Error(IDLoc, "branch target out of range");
589 if (OffsetToAlignment (Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
590 return Error(IDLoc, "branch to misaligned address");
600 assert (MCID.getNumOperands() == 2 && "unexpected number of operands");
601 Offset = Inst.getOperand(1);
603 break; // We'll deal with this situation later on when applying fixups.
604 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
605 return Error(IDLoc, "branch target out of range");
606 if (OffsetToAlignment (Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
607 return Error(IDLoc, "branch to misaligned address");
612 if (MCID.hasDelaySlot() && Options.isReorder()) {
613 // If this instruction has a delay slot and .set reorder is active,
614 // emit a NOP after it.
615 Instructions.push_back(Inst);
617 NopInst.setOpcode(Mips::SLL);
618 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
619 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
620 NopInst.addOperand(MCOperand::CreateImm(0));
621 Instructions.push_back(NopInst);
625 if (MCID.mayLoad() || MCID.mayStore()) {
626 // Check the offset of memory operand, if it is a symbol
627 // reference or immediate we may have to expand instructions.
628 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
629 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
630 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
631 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
632 MCOperand &Op = Inst.getOperand(i);
634 int MemOffset = Op.getImm();
635 if (MemOffset < -32768 || MemOffset > 32767) {
636 // Offset can't exceed 16bit value.
637 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
640 } else if (Op.isExpr()) {
641 const MCExpr *Expr = Op.getExpr();
642 if (Expr->getKind() == MCExpr::SymbolRef) {
643 const MCSymbolRefExpr *SR =
644 static_cast<const MCSymbolRefExpr *>(Expr);
645 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
647 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
650 } else if (!isEvaluated(Expr)) {
651 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
659 if (needsExpansion(Inst))
660 expandInstruction(Inst, IDLoc, Instructions);
662 Instructions.push_back(Inst);
667 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
669 switch (Inst.getOpcode()) {
670 case Mips::LoadImm32Reg:
671 case Mips::LoadAddr32Imm:
672 case Mips::LoadAddr32Reg:
679 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
680 SmallVectorImpl<MCInst> &Instructions) {
681 switch (Inst.getOpcode()) {
682 case Mips::LoadImm32Reg:
683 return expandLoadImm(Inst, IDLoc, Instructions);
684 case Mips::LoadAddr32Imm:
685 return expandLoadAddressImm(Inst, IDLoc, Instructions);
686 case Mips::LoadAddr32Reg:
687 return expandLoadAddressReg(Inst, IDLoc, Instructions);
691 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
692 SmallVectorImpl<MCInst> &Instructions) {
694 const MCOperand &ImmOp = Inst.getOperand(1);
695 assert(ImmOp.isImm() && "expected immediate operand kind");
696 const MCOperand &RegOp = Inst.getOperand(0);
697 assert(RegOp.isReg() && "expected register operand kind");
699 int ImmValue = ImmOp.getImm();
700 tmpInst.setLoc(IDLoc);
701 if (0 <= ImmValue && ImmValue <= 65535) {
702 // For 0 <= j <= 65535.
703 // li d,j => ori d,$zero,j
704 tmpInst.setOpcode(Mips::ORi);
705 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
706 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
707 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
708 Instructions.push_back(tmpInst);
709 } else if (ImmValue < 0 && ImmValue >= -32768) {
710 // For -32768 <= j < 0.
711 // li d,j => addiu d,$zero,j
712 tmpInst.setOpcode(Mips::ADDiu);
713 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
714 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
715 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
716 Instructions.push_back(tmpInst);
718 // For any other value of j that is representable as a 32-bit integer.
719 // li d,j => lui d,hi16(j)
721 tmpInst.setOpcode(Mips::LUi);
722 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
723 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
724 Instructions.push_back(tmpInst);
726 tmpInst.setOpcode(Mips::ORi);
727 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
728 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
729 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
730 tmpInst.setLoc(IDLoc);
731 Instructions.push_back(tmpInst);
736 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
737 SmallVectorImpl<MCInst> &Instructions) {
739 const MCOperand &ImmOp = Inst.getOperand(2);
740 assert(ImmOp.isImm() && "expected immediate operand kind");
741 const MCOperand &SrcRegOp = Inst.getOperand(1);
742 assert(SrcRegOp.isReg() && "expected register operand kind");
743 const MCOperand &DstRegOp = Inst.getOperand(0);
744 assert(DstRegOp.isReg() && "expected register operand kind");
745 int ImmValue = ImmOp.getImm();
746 if (-32768 <= ImmValue && ImmValue <= 65535) {
747 // For -32768 <= j <= 65535.
748 // la d,j(s) => addiu d,s,j
749 tmpInst.setOpcode(Mips::ADDiu);
750 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
751 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
752 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
753 Instructions.push_back(tmpInst);
755 // For any other value of j that is representable as a 32-bit integer.
756 // la d,j(s) => lui d,hi16(j)
759 tmpInst.setOpcode(Mips::LUi);
760 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
761 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
762 Instructions.push_back(tmpInst);
764 tmpInst.setOpcode(Mips::ORi);
765 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
766 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
767 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
768 Instructions.push_back(tmpInst);
770 tmpInst.setOpcode(Mips::ADDu);
771 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
772 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
773 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
774 Instructions.push_back(tmpInst);
779 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
780 SmallVectorImpl<MCInst> &Instructions) {
782 const MCOperand &ImmOp = Inst.getOperand(1);
783 assert(ImmOp.isImm() && "expected immediate operand kind");
784 const MCOperand &RegOp = Inst.getOperand(0);
785 assert(RegOp.isReg() && "expected register operand kind");
786 int ImmValue = ImmOp.getImm();
787 if (-32768 <= ImmValue && ImmValue <= 65535) {
788 // For -32768 <= j <= 65535.
789 // la d,j => addiu d,$zero,j
790 tmpInst.setOpcode(Mips::ADDiu);
791 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
792 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
793 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
794 Instructions.push_back(tmpInst);
796 // For any other value of j that is representable as a 32-bit integer.
797 // la d,j => lui d,hi16(j)
799 tmpInst.setOpcode(Mips::LUi);
800 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
801 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
802 Instructions.push_back(tmpInst);
804 tmpInst.setOpcode(Mips::ORi);
805 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
806 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
807 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
808 Instructions.push_back(tmpInst);
812 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
813 SmallVectorImpl<MCInst> &Instructions,
814 bool isLoad, bool isImmOpnd) {
815 const MCSymbolRefExpr *SR;
817 unsigned ImmOffset, HiOffset, LoOffset;
818 const MCExpr *ExprOffset;
820 unsigned AtRegNum = getReg(
821 (isMips64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
822 // 1st operand is either the source or destination register.
823 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
824 unsigned RegOpNum = Inst.getOperand(0).getReg();
825 // 2nd operand is the base register.
826 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
827 unsigned BaseRegNum = Inst.getOperand(1).getReg();
828 // 3rd operand is either an immediate or expression.
830 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
831 ImmOffset = Inst.getOperand(2).getImm();
832 LoOffset = ImmOffset & 0x0000ffff;
833 HiOffset = (ImmOffset & 0xffff0000) >> 16;
834 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
835 if (LoOffset & 0x8000)
838 ExprOffset = Inst.getOperand(2).getExpr();
839 // All instructions will have the same location.
840 TempInst.setLoc(IDLoc);
841 // 1st instruction in expansion is LUi. For load instruction we can use
842 // the dst register as a temporary if base and dst are different,
843 // but for stores we must use $at.
844 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
845 TempInst.setOpcode(Mips::LUi);
846 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
848 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
850 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
851 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
852 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
853 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
855 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
857 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
858 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
861 // Add the instruction to the list.
862 Instructions.push_back(TempInst);
863 // Prepare TempInst for next instruction.
865 // Add temp register to base.
866 TempInst.setOpcode(Mips::ADDu);
867 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
868 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
869 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
870 Instructions.push_back(TempInst);
872 // And finaly, create original instruction with low part
873 // of offset and new base.
874 TempInst.setOpcode(Inst.getOpcode());
875 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
876 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
878 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
880 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
881 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
882 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
884 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
886 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
887 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
890 Instructions.push_back(TempInst);
894 bool MipsAsmParser::MatchAndEmitInstruction(
895 SMLoc IDLoc, unsigned &Opcode,
896 SmallVectorImpl<MCParsedAsmOperand *> &Operands, MCStreamer &Out,
897 unsigned &ErrorInfo, bool MatchingInlineAsm) {
899 SmallVector<MCInst, 8> Instructions;
900 unsigned MatchResult =
901 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
903 switch (MatchResult) {
906 case Match_Success: {
907 if (processInstruction(Inst, IDLoc, Instructions))
909 for (unsigned i = 0; i < Instructions.size(); i++)
910 Out.EmitInstruction(Instructions[i]);
913 case Match_MissingFeature:
914 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
916 case Match_InvalidOperand: {
917 SMLoc ErrorLoc = IDLoc;
918 if (ErrorInfo != ~0U) {
919 if (ErrorInfo >= Operands.size())
920 return Error(IDLoc, "too few operands for instruction");
922 ErrorLoc = ((MipsOperand *)Operands[ErrorInfo])->getStartLoc();
923 if (ErrorLoc == SMLoc())
927 return Error(ErrorLoc, "invalid operand for instruction");
929 case Match_MnemonicFail:
930 return Error(IDLoc, "invalid instruction");
935 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
941 CC = StringSwitch<unsigned>(Name)
975 // Although SGI documentation just cuts out t0-t3 for n32/n64,
976 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
977 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
978 if (isMips64() && 8 <= CC && CC <= 11)
981 if (CC == -1 && isMips64())
982 CC = StringSwitch<unsigned>(Name)
995 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
997 if (Name[0] == 'f') {
998 StringRef NumString = Name.substr(1);
1000 if (NumString.getAsInteger(10, IntVal))
1001 return -1; // This is not an integer.
1002 if (IntVal > 31) // Maximum index for fpu register.
1009 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
1011 if (Name.startswith("fcc")) {
1012 StringRef NumString = Name.substr(3);
1014 if (NumString.getAsInteger(10, IntVal))
1015 return -1; // This is not an integer.
1016 if (IntVal > 7) // There are only 8 fcc registers.
1023 int MipsAsmParser::matchACRegisterName(StringRef Name) {
1025 if (Name.startswith("ac")) {
1026 StringRef NumString = Name.substr(2);
1028 if (NumString.getAsInteger(10, IntVal))
1029 return -1; // This is not an integer.
1030 if (IntVal > 3) // There are only 3 acc registers.
1037 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
1040 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
1049 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1052 CC = StringSwitch<unsigned>(Name)
1055 .Case("msaaccess", 2)
1057 .Case("msamodify", 4)
1058 .Case("msarequest", 5)
1060 .Case("msaunmap", 7)
1066 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
1069 CC = matchCPURegisterName(Name);
1071 return matchRegisterByNumber(CC, is64BitReg ? Mips::GPR64RegClassID
1072 : Mips::GPR32RegClassID);
1073 CC = matchFPURegisterName(Name);
1074 // TODO: decide about fpu register class
1076 return matchRegisterByNumber(CC, isFP64() ? Mips::FGR64RegClassID
1077 : Mips::FGR32RegClassID);
1078 return matchMSA128RegisterName(Name);
1081 int MipsAsmParser::regKindToRegClass(int RegKind) {
1084 case MipsOperand::Kind_GPR32:
1085 return Mips::GPR32RegClassID;
1086 case MipsOperand::Kind_GPR64:
1087 return Mips::GPR64RegClassID;
1088 case MipsOperand::Kind_HWRegs:
1089 return Mips::HWRegsRegClassID;
1090 case MipsOperand::Kind_FGR32Regs:
1091 return Mips::FGR32RegClassID;
1092 case MipsOperand::Kind_FGRH32Regs:
1093 return Mips::FGRH32RegClassID;
1094 case MipsOperand::Kind_FGR64Regs:
1095 return Mips::FGR64RegClassID;
1096 case MipsOperand::Kind_AFGR64Regs:
1097 return Mips::AFGR64RegClassID;
1098 case MipsOperand::Kind_CCRRegs:
1099 return Mips::CCRRegClassID;
1100 case MipsOperand::Kind_ACC64DSP:
1101 return Mips::ACC64DSPRegClassID;
1102 case MipsOperand::Kind_FCCRegs:
1103 return Mips::FCCRegClassID;
1104 case MipsOperand::Kind_MSA128BRegs:
1105 return Mips::MSA128BRegClassID;
1106 case MipsOperand::Kind_MSA128HRegs:
1107 return Mips::MSA128HRegClassID;
1108 case MipsOperand::Kind_MSA128WRegs:
1109 return Mips::MSA128WRegClassID;
1110 case MipsOperand::Kind_MSA128DRegs:
1111 return Mips::MSA128DRegClassID;
1112 case MipsOperand::Kind_MSA128CtrlRegs:
1113 return Mips::MSACtrlRegClassID;
1119 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1127 int MipsAsmParser::getATReg() { return Options.getATRegNum(); }
1129 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1130 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1133 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1135 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
1138 return getReg(RegClass, RegNum);
1141 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
1142 const AsmToken &Tok = Parser.getTok();
1145 if (Tok.is(AsmToken::Identifier)) {
1146 std::string lowerCase = Tok.getString().lower();
1147 RegNum = matchRegisterName(lowerCase, is64BitReg);
1148 } else if (Tok.is(AsmToken::Integer))
1149 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
1150 is64BitReg ? Mips::GPR64RegClassID
1151 : Mips::GPR32RegClassID);
1155 bool MipsAsmParser::tryParseRegisterOperand(
1156 SmallVectorImpl<MCParsedAsmOperand *> &Operands, bool is64BitReg) {
1158 SMLoc S = Parser.getTok().getLoc();
1161 RegNo = tryParseRegister(is64BitReg);
1166 MipsOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1167 Parser.Lex(); // Eat register token.
1172 MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1173 StringRef Mnemonic) {
1174 // Check if the current operand has a custom associated parser, if so, try to
1175 // custom parse the operand, or fallback to the general approach.
1176 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1177 if (ResTy == MatchOperand_Success)
1179 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1180 // there was a match, but an error occurred, in which case, just return that
1181 // the operand parsing failed.
1182 if (ResTy == MatchOperand_ParseFail)
1185 switch (getLexer().getKind()) {
1187 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1189 case AsmToken::Dollar: {
1190 // Parse the register.
1191 SMLoc S = Parser.getTok().getLoc();
1192 Parser.Lex(); // Eat dollar token.
1193 // Parse the register operand.
1194 if (!tryParseRegisterOperand(Operands, isMips64())) {
1195 if (getLexer().is(AsmToken::LParen)) {
1196 // Check if it is indexed addressing operand.
1197 Operands.push_back(MipsOperand::CreateToken("(", S));
1198 Parser.Lex(); // Eat the parenthesis.
1199 if (getLexer().isNot(AsmToken::Dollar))
1202 Parser.Lex(); // Eat the dollar
1203 if (tryParseRegisterOperand(Operands, isMips64()))
1206 if (!getLexer().is(AsmToken::RParen))
1209 S = Parser.getTok().getLoc();
1210 Operands.push_back(MipsOperand::CreateToken(")", S));
1215 // Maybe it is a symbol reference.
1216 StringRef Identifier;
1217 if (Parser.parseIdentifier(Identifier))
1220 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1221 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1222 // Otherwise create a symbol reference.
1224 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1226 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1229 case AsmToken::Identifier:
1230 // For instruction aliases like "bc1f $Label" dedicated parser will
1231 // eat the '$' sign before failing. So in order to look for appropriate
1232 // label we must check first if we have already consumed '$'.
1233 if (hasConsumedDollar) {
1234 hasConsumedDollar = false;
1235 SMLoc S = Parser.getTok().getLoc();
1236 StringRef Identifier;
1237 if (Parser.parseIdentifier(Identifier))
1240 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1241 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1242 // Create a symbol reference.
1244 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1246 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1249 // Look for the existing symbol, we should check if
1250 // we need to assigne the propper RegisterKind.
1251 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
1253 // Else drop to expression parsing.
1254 case AsmToken::LParen:
1255 case AsmToken::Minus:
1256 case AsmToken::Plus:
1257 case AsmToken::Integer:
1258 case AsmToken::String: {
1259 // Quoted label names.
1260 const MCExpr *IdVal;
1261 SMLoc S = Parser.getTok().getLoc();
1262 if (getParser().parseExpression(IdVal))
1264 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1265 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1268 case AsmToken::Percent: {
1269 // It is a symbol reference or constant expression.
1270 const MCExpr *IdVal;
1271 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1272 if (parseRelocOperand(IdVal))
1275 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1277 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1279 } // case AsmToken::Percent
1280 } // switch(getLexer().getKind())
1284 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1285 StringRef RelocStr) {
1287 // Check the type of the expression.
1288 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1289 // It's a constant, evaluate lo or hi value.
1290 if (RelocStr == "lo") {
1291 short Val = MCE->getValue();
1292 Res = MCConstantExpr::Create(Val, getContext());
1293 } else if (RelocStr == "hi") {
1294 int Val = MCE->getValue();
1295 int LoSign = Val & 0x8000;
1296 Val = (Val & 0xffff0000) >> 16;
1297 // Lower part is treated as a signed int, so if it is negative
1298 // we must add 1 to the hi part to compensate.
1301 Res = MCConstantExpr::Create(Val, getContext());
1303 llvm_unreachable("Invalid RelocStr value");
1308 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1309 // It's a symbol, create a symbolic expression from the symbol.
1310 StringRef Symbol = MSRE->getSymbol().getName();
1311 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1312 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1316 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1317 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1318 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1319 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1323 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1324 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1325 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1328 // Just return the original expression.
1332 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1334 switch (Expr->getKind()) {
1335 case MCExpr::Constant:
1337 case MCExpr::SymbolRef:
1338 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1339 case MCExpr::Binary:
1340 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1341 if (!isEvaluated(BE->getLHS()))
1343 return isEvaluated(BE->getRHS());
1346 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1353 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1354 Parser.Lex(); // Eat the % token.
1355 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1356 if (Tok.isNot(AsmToken::Identifier))
1359 std::string Str = Tok.getIdentifier().str();
1361 Parser.Lex(); // Eat the identifier.
1362 // Now make an expression from the rest of the operand.
1363 const MCExpr *IdVal;
1366 if (getLexer().getKind() == AsmToken::LParen) {
1368 Parser.Lex(); // Eat the '(' token.
1369 if (getLexer().getKind() == AsmToken::Percent) {
1370 Parser.Lex(); // Eat the % token.
1371 const AsmToken &nextTok = Parser.getTok();
1372 if (nextTok.isNot(AsmToken::Identifier))
1375 Str += nextTok.getIdentifier();
1376 Parser.Lex(); // Eat the identifier.
1377 if (getLexer().getKind() != AsmToken::LParen)
1382 if (getParser().parseParenExpression(IdVal, EndLoc))
1385 while (getLexer().getKind() == AsmToken::RParen)
1386 Parser.Lex(); // Eat the ')' token.
1389 return true; // Parenthesis must follow the relocation operand.
1391 Res = evaluateRelocExpr(IdVal, Str);
1395 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1397 StartLoc = Parser.getTok().getLoc();
1398 RegNo = tryParseRegister(isMips64());
1399 EndLoc = Parser.getTok().getLoc();
1400 return (RegNo == (unsigned)-1);
1403 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1407 while (getLexer().getKind() == AsmToken::LParen)
1410 switch (getLexer().getKind()) {
1413 case AsmToken::Identifier:
1414 case AsmToken::LParen:
1415 case AsmToken::Integer:
1416 case AsmToken::Minus:
1417 case AsmToken::Plus:
1419 Result = getParser().parseParenExpression(Res, S);
1421 Result = (getParser().parseExpression(Res));
1422 while (getLexer().getKind() == AsmToken::RParen)
1425 case AsmToken::Percent:
1426 Result = parseRelocOperand(Res);
1431 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1432 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1434 const MCExpr *IdVal = 0;
1436 bool isParenExpr = false;
1437 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1438 // First operand is the offset.
1439 S = Parser.getTok().getLoc();
1441 if (getLexer().getKind() == AsmToken::LParen) {
1446 if (getLexer().getKind() != AsmToken::Dollar) {
1447 if (parseMemOffset(IdVal, isParenExpr))
1448 return MatchOperand_ParseFail;
1450 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1451 if (Tok.isNot(AsmToken::LParen)) {
1452 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1453 if (Mnemonic->getToken() == "la") {
1455 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1456 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1457 return MatchOperand_Success;
1459 if (Tok.is(AsmToken::EndOfStatement)) {
1461 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1463 // Zero register assumed, add a memory operand with ZERO as its base.
1464 Operands.push_back(MipsOperand::CreateMem(
1465 isMips64() ? Mips::ZERO_64 : Mips::ZERO, IdVal, S, E));
1466 return MatchOperand_Success;
1468 Error(Parser.getTok().getLoc(), "'(' expected");
1469 return MatchOperand_ParseFail;
1472 Parser.Lex(); // Eat the '(' token.
1475 Res = parseRegs(Operands, isMips64() ? (int)MipsOperand::Kind_GPR64
1476 : (int)MipsOperand::Kind_GPR32);
1477 if (Res != MatchOperand_Success)
1480 if (Parser.getTok().isNot(AsmToken::RParen)) {
1481 Error(Parser.getTok().getLoc(), "')' expected");
1482 return MatchOperand_ParseFail;
1485 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1487 Parser.Lex(); // Eat the ')' token.
1490 IdVal = MCConstantExpr::Create(0, getContext());
1492 // Replace the register operand with the memory operand.
1493 MipsOperand *op = static_cast<MipsOperand *>(Operands.back());
1494 int RegNo = op->getReg();
1495 // Remove the register from the operands.
1496 Operands.pop_back();
1497 // Add the memory operand.
1498 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1500 if (IdVal->EvaluateAsAbsolute(Imm))
1501 IdVal = MCConstantExpr::Create(Imm, getContext());
1502 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1503 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1507 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1509 return MatchOperand_Success;
1512 bool MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1514 // If the first token is not '$' we have an error.
1515 if (Parser.getTok().isNot(AsmToken::Dollar))
1518 SMLoc S = Parser.getTok().getLoc();
1520 AsmToken::TokenKind TkKind = getLexer().getKind();
1523 if (TkKind == AsmToken::Integer) {
1524 Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
1525 regKindToRegClass(RegKind));
1528 } else if (TkKind == AsmToken::Identifier) {
1529 if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
1531 Reg = getReg(regKindToRegClass(RegKind), Reg);
1536 MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
1537 Op->setRegKind((MipsOperand::RegisterKind)RegKind);
1538 Operands.push_back(Op);
1543 MipsAsmParser::OperandMatchResultTy
1544 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1545 MipsOperand::RegisterKind RegKind =
1546 isN64() ? MipsOperand::Kind_GPR64 : MipsOperand::Kind_GPR32;
1548 // Parse index register.
1549 if (!parsePtrReg(Operands, RegKind))
1550 return MatchOperand_NoMatch;
1553 if (Parser.getTok().isNot(AsmToken::LParen))
1554 return MatchOperand_NoMatch;
1556 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1559 // Parse base register.
1560 if (!parsePtrReg(Operands, RegKind))
1561 return MatchOperand_NoMatch;
1564 if (Parser.getTok().isNot(AsmToken::RParen))
1565 return MatchOperand_NoMatch;
1567 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1570 return MatchOperand_Success;
1573 MipsAsmParser::OperandMatchResultTy
1574 MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1576 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1577 if (getLexer().getKind() == AsmToken::Identifier && !hasConsumedDollar) {
1578 if (searchSymbolAlias(Operands, Kind))
1579 return MatchOperand_Success;
1580 return MatchOperand_NoMatch;
1582 SMLoc S = Parser.getTok().getLoc();
1583 // If the first token is not '$', we have an error.
1584 if (Parser.getTok().isNot(AsmToken::Dollar) && !hasConsumedDollar)
1585 return MatchOperand_NoMatch;
1586 if (!hasConsumedDollar) {
1587 Parser.Lex(); // Eat the '$'
1588 hasConsumedDollar = true;
1590 if (getLexer().getKind() == AsmToken::Identifier) {
1592 std::string RegName = Parser.getTok().getString().lower();
1593 // Match register by name
1595 case MipsOperand::Kind_GPR32:
1596 case MipsOperand::Kind_GPR64:
1597 RegNum = matchCPURegisterName(RegName);
1599 case MipsOperand::Kind_AFGR64Regs:
1600 case MipsOperand::Kind_FGR64Regs:
1601 case MipsOperand::Kind_FGR32Regs:
1602 case MipsOperand::Kind_FGRH32Regs:
1603 RegNum = matchFPURegisterName(RegName);
1604 if (RegKind == MipsOperand::Kind_AFGR64Regs)
1606 else if (RegKind == MipsOperand::Kind_FGRH32Regs && !isFP64())
1607 if (RegNum != -1 && RegNum % 2 != 0)
1608 Warning(S, "Float register should be even.");
1610 case MipsOperand::Kind_FCCRegs:
1611 RegNum = matchFCCRegisterName(RegName);
1613 case MipsOperand::Kind_ACC64DSP:
1614 RegNum = matchACRegisterName(RegName);
1617 break; // No match, value is set to -1.
1619 // No match found, return _NoMatch to give a chance to other round.
1621 return MatchOperand_NoMatch;
1623 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1625 return MatchOperand_NoMatch;
1628 MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1629 Op->setRegKind(Kind);
1630 Operands.push_back(Op);
1631 hasConsumedDollar = false;
1632 Parser.Lex(); // Eat the register name.
1633 return MatchOperand_Success;
1634 } else if (getLexer().getKind() == AsmToken::Integer) {
1635 unsigned RegNum = Parser.getTok().getIntVal();
1636 if (Kind == MipsOperand::Kind_HWRegs) {
1638 return MatchOperand_NoMatch;
1639 // Only hwreg 29 is supported, found at index 0.
1642 int Reg = matchRegisterByNumber(RegNum, regKindToRegClass(Kind));
1644 return MatchOperand_NoMatch;
1645 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1646 Op->setRegKind(Kind);
1647 Operands.push_back(Op);
1648 hasConsumedDollar = false;
1649 Parser.Lex(); // Eat the register number.
1650 if ((RegKind == MipsOperand::Kind_GPR32) &&
1651 (getLexer().is(AsmToken::LParen))) {
1652 // Check if it is indexed addressing operand.
1653 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1654 Parser.Lex(); // Eat the parenthesis.
1655 if (parseRegs(Operands, RegKind) != MatchOperand_Success)
1656 return MatchOperand_NoMatch;
1657 if (getLexer().isNot(AsmToken::RParen))
1658 return MatchOperand_NoMatch;
1659 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1662 return MatchOperand_Success;
1664 return MatchOperand_NoMatch;
1667 bool MipsAsmParser::validateMSAIndex(int Val, int RegKind) {
1668 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1676 case MipsOperand::Kind_MSA128BRegs:
1678 case MipsOperand::Kind_MSA128HRegs:
1680 case MipsOperand::Kind_MSA128WRegs:
1682 case MipsOperand::Kind_MSA128DRegs:
1687 MipsAsmParser::OperandMatchResultTy
1688 MipsAsmParser::parseMSARegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1690 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1691 SMLoc S = Parser.getTok().getLoc();
1692 std::string RegName;
1694 if (Parser.getTok().isNot(AsmToken::Dollar))
1695 return MatchOperand_NoMatch;
1699 return MatchOperand_ParseFail;
1700 case MipsOperand::Kind_MSA128BRegs:
1701 case MipsOperand::Kind_MSA128HRegs:
1702 case MipsOperand::Kind_MSA128WRegs:
1703 case MipsOperand::Kind_MSA128DRegs:
1707 Parser.Lex(); // Eat the '$'.
1708 if (getLexer().getKind() == AsmToken::Identifier)
1709 RegName = Parser.getTok().getString().lower();
1711 return MatchOperand_ParseFail;
1713 int RegNum = matchMSA128RegisterName(RegName);
1715 if (RegNum < 0 || RegNum > 31)
1716 return MatchOperand_ParseFail;
1718 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1720 return MatchOperand_ParseFail;
1722 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1723 Op->setRegKind(Kind);
1724 Operands.push_back(Op);
1726 Parser.Lex(); // Eat the register identifier.
1728 // MSA registers may be suffixed with an index in the form of:
1729 // 1) Immediate expression.
1730 // 2) General Purpose Register.
1732 // 1) copy_s.b $29,$w0[0]
1733 // 2) sld.b $w0,$w1[$1]
1735 if (Parser.getTok().isNot(AsmToken::LBrac))
1736 return MatchOperand_Success;
1738 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1740 Operands.push_back(MipsOperand::CreateToken("[", Parser.getTok().getLoc()));
1741 Parser.Lex(); // Parse the '[' token.
1743 if (Parser.getTok().is(AsmToken::Dollar)) {
1744 // This must be a GPR.
1746 SMLoc VIdx = Parser.getTok().getLoc();
1747 Parser.Lex(); // Parse the '$' token.
1749 // GPR have aliases and we must account for that. Example: $30 == $fp
1750 if (getLexer().getKind() == AsmToken::Integer) {
1751 unsigned RegNum = Parser.getTok().getIntVal();
1752 int Reg = matchRegisterByNumber(
1753 RegNum, regKindToRegClass(MipsOperand::Kind_GPR32));
1755 Error(VIdx, "invalid general purpose register");
1756 return MatchOperand_ParseFail;
1759 RegOp = MipsOperand::CreateReg(Reg, VIdx, Parser.getTok().getLoc());
1760 } else if (getLexer().getKind() == AsmToken::Identifier) {
1762 std::string RegName = Parser.getTok().getString().lower();
1764 RegNum = matchCPURegisterName(RegName);
1766 Error(VIdx, "general purpose register expected");
1767 return MatchOperand_ParseFail;
1769 RegNum = getReg(regKindToRegClass(MipsOperand::Kind_GPR32), RegNum);
1770 RegOp = MipsOperand::CreateReg(RegNum, VIdx, Parser.getTok().getLoc());
1772 return MatchOperand_ParseFail;
1774 RegOp->setRegKind(MipsOperand::Kind_GPR32);
1775 Operands.push_back(RegOp);
1776 Parser.Lex(); // Eat the register identifier.
1778 if (Parser.getTok().isNot(AsmToken::RBrac))
1779 return MatchOperand_ParseFail;
1781 Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
1782 Parser.Lex(); // Parse the ']' token.
1784 return MatchOperand_Success;
1787 // The index must be a constant expression then.
1788 SMLoc VIdx = Parser.getTok().getLoc();
1789 const MCExpr *ImmVal;
1791 if (getParser().parseExpression(ImmVal))
1792 return MatchOperand_ParseFail;
1794 const MCConstantExpr *expr = dyn_cast<MCConstantExpr>(ImmVal);
1795 if (!expr || !validateMSAIndex((int)expr->getValue(), Kind)) {
1796 Error(VIdx, "invalid immediate value");
1797 return MatchOperand_ParseFail;
1800 SMLoc E = Parser.getTok().getEndLoc();
1802 if (Parser.getTok().isNot(AsmToken::RBrac))
1803 return MatchOperand_ParseFail;
1806 Mnemonic->getToken() == "insve.b" || Mnemonic->getToken() == "insve.h" ||
1807 Mnemonic->getToken() == "insve.w" || Mnemonic->getToken() == "insve.d";
1809 // The second vector index of insve instructions is always 0.
1810 if (insve && Operands.size() > 6) {
1811 if (expr->getValue() != 0) {
1812 Error(VIdx, "immediate value must be 0");
1813 return MatchOperand_ParseFail;
1815 Operands.push_back(MipsOperand::CreateToken("0", VIdx));
1817 Operands.push_back(MipsOperand::CreateImm(expr, VIdx, E));
1819 Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
1821 Parser.Lex(); // Parse the ']' token.
1823 return MatchOperand_Success;
1826 MipsAsmParser::OperandMatchResultTy
1827 MipsAsmParser::parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1829 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1831 if (Kind != MipsOperand::Kind_MSA128CtrlRegs)
1832 return MatchOperand_NoMatch;
1834 if (Parser.getTok().isNot(AsmToken::Dollar))
1835 return MatchOperand_ParseFail;
1837 SMLoc S = Parser.getTok().getLoc();
1839 Parser.Lex(); // Eat the '$' symbol.
1842 if (getLexer().getKind() == AsmToken::Identifier)
1843 RegNum = matchMSA128CtrlRegisterName(Parser.getTok().getString().lower());
1844 else if (getLexer().getKind() == AsmToken::Integer)
1845 RegNum = Parser.getTok().getIntVal();
1847 return MatchOperand_ParseFail;
1849 if (RegNum < 0 || RegNum > 7)
1850 return MatchOperand_ParseFail;
1852 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1854 return MatchOperand_ParseFail;
1856 MipsOperand *RegOp =
1857 MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1858 RegOp->setRegKind(MipsOperand::Kind_MSA128CtrlRegs);
1859 Operands.push_back(RegOp);
1860 Parser.Lex(); // Eat the register identifier.
1862 return MatchOperand_Success;
1865 MipsAsmParser::OperandMatchResultTy
1866 MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1869 return MatchOperand_NoMatch;
1870 return parseRegs(Operands, (int)MipsOperand::Kind_GPR64);
1873 MipsAsmParser::OperandMatchResultTy
1874 MipsAsmParser::parseGPR32(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1875 return parseRegs(Operands, (int)MipsOperand::Kind_GPR32);
1878 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseAFGR64Regs(
1879 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1882 return MatchOperand_NoMatch;
1883 return parseRegs(Operands, (int)MipsOperand::Kind_AFGR64Regs);
1886 MipsAsmParser::OperandMatchResultTy
1887 MipsAsmParser::parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1889 return MatchOperand_NoMatch;
1890 return parseRegs(Operands, (int)MipsOperand::Kind_FGR64Regs);
1893 MipsAsmParser::OperandMatchResultTy
1894 MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1895 return parseRegs(Operands, (int)MipsOperand::Kind_FGR32Regs);
1898 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseFGRH32Regs(
1899 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1900 return parseRegs(Operands, (int)MipsOperand::Kind_FGRH32Regs);
1903 MipsAsmParser::OperandMatchResultTy
1904 MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1905 return parseRegs(Operands, (int)MipsOperand::Kind_FCCRegs);
1908 MipsAsmParser::OperandMatchResultTy
1909 MipsAsmParser::parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1910 return parseRegs(Operands, (int)MipsOperand::Kind_ACC64DSP);
1913 MipsAsmParser::OperandMatchResultTy
1914 MipsAsmParser::parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1915 // If the first token is not '$' we have an error.
1916 if (Parser.getTok().isNot(AsmToken::Dollar))
1917 return MatchOperand_NoMatch;
1919 SMLoc S = Parser.getTok().getLoc();
1920 Parser.Lex(); // Eat the '$'
1922 const AsmToken &Tok = Parser.getTok(); // Get next token.
1924 if (Tok.isNot(AsmToken::Identifier))
1925 return MatchOperand_NoMatch;
1927 if (!Tok.getIdentifier().startswith("ac"))
1928 return MatchOperand_NoMatch;
1930 StringRef NumString = Tok.getIdentifier().substr(2);
1933 if (NumString.getAsInteger(10, IntVal))
1934 return MatchOperand_NoMatch;
1936 unsigned Reg = matchRegisterByNumber(IntVal, Mips::LO32DSPRegClassID);
1938 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1939 Op->setRegKind(MipsOperand::Kind_LO32DSP);
1940 Operands.push_back(Op);
1942 Parser.Lex(); // Eat the register number.
1943 return MatchOperand_Success;
1946 MipsAsmParser::OperandMatchResultTy
1947 MipsAsmParser::parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1948 // If the first token is not '$' we have an error.
1949 if (Parser.getTok().isNot(AsmToken::Dollar))
1950 return MatchOperand_NoMatch;
1952 SMLoc S = Parser.getTok().getLoc();
1953 Parser.Lex(); // Eat the '$'
1955 const AsmToken &Tok = Parser.getTok(); // Get next token.
1957 if (Tok.isNot(AsmToken::Identifier))
1958 return MatchOperand_NoMatch;
1960 if (!Tok.getIdentifier().startswith("ac"))
1961 return MatchOperand_NoMatch;
1963 StringRef NumString = Tok.getIdentifier().substr(2);
1966 if (NumString.getAsInteger(10, IntVal))
1967 return MatchOperand_NoMatch;
1969 unsigned Reg = matchRegisterByNumber(IntVal, Mips::HI32DSPRegClassID);
1971 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1972 Op->setRegKind(MipsOperand::Kind_HI32DSP);
1973 Operands.push_back(Op);
1975 Parser.Lex(); // Eat the register number.
1976 return MatchOperand_Success;
1979 MipsAsmParser::OperandMatchResultTy
1980 MipsAsmParser::parseCOP2(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1981 // If the first token is not '$' we have an error.
1982 if (Parser.getTok().isNot(AsmToken::Dollar))
1983 return MatchOperand_NoMatch;
1985 SMLoc S = Parser.getTok().getLoc();
1986 Parser.Lex(); // Eat the '$'
1988 const AsmToken &Tok = Parser.getTok(); // Get next token.
1990 if (Tok.isNot(AsmToken::Integer))
1991 return MatchOperand_NoMatch;
1993 unsigned IntVal = Tok.getIntVal();
1995 unsigned Reg = matchRegisterByNumber(IntVal, Mips::COP2RegClassID);
1997 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1998 Op->setRegKind(MipsOperand::Kind_COP2);
1999 Operands.push_back(Op);
2001 Parser.Lex(); // Eat the register number.
2002 return MatchOperand_Success;
2005 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128BRegs(
2006 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2007 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128BRegs);
2010 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128HRegs(
2011 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2012 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128HRegs);
2015 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128WRegs(
2016 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2017 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128WRegs);
2020 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128DRegs(
2021 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2022 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128DRegs);
2025 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128CtrlRegs(
2026 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2027 return parseMSACtrlRegs(Operands, (int)MipsOperand::Kind_MSA128CtrlRegs);
2030 bool MipsAsmParser::searchSymbolAlias(
2031 SmallVectorImpl<MCParsedAsmOperand *> &Operands, unsigned RegKind) {
2033 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
2035 SMLoc S = Parser.getTok().getLoc();
2037 if (Sym->isVariable())
2038 Expr = Sym->getVariableValue();
2041 if (Expr->getKind() == MCExpr::SymbolRef) {
2042 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
2043 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
2044 const StringRef DefSymbol = Ref->getSymbol().getName();
2045 if (DefSymbol.startswith("$")) {
2047 APInt IntVal(32, -1);
2048 if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
2049 RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
2050 isMips64() ? Mips::GPR64RegClassID
2051 : Mips::GPR32RegClassID);
2053 // Lookup for the register with the corresponding name.
2055 case MipsOperand::Kind_AFGR64Regs:
2056 case MipsOperand::Kind_FGR64Regs:
2057 RegNum = matchFPURegisterName(DefSymbol.substr(1));
2059 case MipsOperand::Kind_FGR32Regs:
2060 RegNum = matchFPURegisterName(DefSymbol.substr(1));
2062 case MipsOperand::Kind_GPR64:
2063 case MipsOperand::Kind_GPR32:
2065 RegNum = matchCPURegisterName(DefSymbol.substr(1));
2069 RegNum = getReg(regKindToRegClass(Kind), RegNum);
2074 MipsOperand::CreateReg(RegNum, S, Parser.getTok().getLoc());
2075 op->setRegKind(Kind);
2076 Operands.push_back(op);
2080 } else if (Expr->getKind() == MCExpr::Constant) {
2082 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
2084 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc());
2085 Operands.push_back(op);
2092 MipsAsmParser::OperandMatchResultTy
2093 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2094 return parseRegs(Operands, (int)MipsOperand::Kind_HWRegs);
2097 MipsAsmParser::OperandMatchResultTy
2098 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2099 return parseRegs(Operands, (int)MipsOperand::Kind_CCRRegs);
2102 MipsAsmParser::OperandMatchResultTy
2103 MipsAsmParser::parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2104 const MCExpr *IdVal;
2105 // If the first token is '$' we may have register operand.
2106 if (Parser.getTok().is(AsmToken::Dollar))
2107 return MatchOperand_NoMatch;
2108 SMLoc S = Parser.getTok().getLoc();
2109 if (getParser().parseExpression(IdVal))
2110 return MatchOperand_ParseFail;
2111 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
2112 assert(MCE && "Unexpected MCExpr type.");
2113 int64_t Val = MCE->getValue();
2114 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2115 Operands.push_back(MipsOperand::CreateImm(
2116 MCConstantExpr::Create(0 - Val, getContext()), S, E));
2117 return MatchOperand_Success;
2120 MipsAsmParser::OperandMatchResultTy
2121 MipsAsmParser::parseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2122 switch (getLexer().getKind()) {
2124 return MatchOperand_NoMatch;
2125 case AsmToken::LParen:
2126 case AsmToken::Plus:
2127 case AsmToken::Minus:
2128 case AsmToken::Integer:
2133 SMLoc S = Parser.getTok().getLoc();
2135 if (getParser().parseExpression(Expr))
2136 return MatchOperand_ParseFail;
2139 if (!Expr->EvaluateAsAbsolute(Val)) {
2140 Error(S, "expected immediate value");
2141 return MatchOperand_ParseFail;
2144 // The LSA instruction allows a 2-bit unsigned immediate. For this reason
2145 // and because the CPU always adds one to the immediate field, the allowed
2146 // range becomes 1..4. We'll only check the range here and will deal
2147 // with the addition/subtraction when actually decoding/encoding
2149 if (Val < 1 || Val > 4) {
2150 Error(S, "immediate not in range (1..4)");
2151 return MatchOperand_ParseFail;
2154 Operands.push_back(MipsOperand::CreateLSAImm(Expr, S,
2155 Parser.getTok().getLoc()));
2156 return MatchOperand_Success;
2159 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
2161 MCSymbolRefExpr::VariantKind VK =
2162 StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
2163 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
2164 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
2165 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
2166 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
2167 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
2168 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
2169 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
2170 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
2171 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
2172 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
2173 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
2174 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
2175 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
2176 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
2177 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
2178 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
2179 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
2180 .Default(MCSymbolRefExpr::VK_None);
2185 bool MipsAsmParser::ParseInstruction(
2186 ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2187 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2188 // Check if we have valid mnemonic
2189 if (!mnemonicIsValid(Name, 0)) {
2190 Parser.eatToEndOfStatement();
2191 return Error(NameLoc, "Unknown instruction");
2193 // First operand in MCInst is instruction mnemonic.
2194 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
2196 // Read the remaining operands.
2197 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2198 // Read the first operand.
2199 if (ParseOperand(Operands, Name)) {
2200 SMLoc Loc = getLexer().getLoc();
2201 Parser.eatToEndOfStatement();
2202 return Error(Loc, "unexpected token in argument list");
2205 while (getLexer().is(AsmToken::Comma)) {
2206 Parser.Lex(); // Eat the comma.
2207 // Parse and remember the operand.
2208 if (ParseOperand(Operands, Name)) {
2209 SMLoc Loc = getLexer().getLoc();
2210 Parser.eatToEndOfStatement();
2211 return Error(Loc, "unexpected token in argument list");
2215 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2216 SMLoc Loc = getLexer().getLoc();
2217 Parser.eatToEndOfStatement();
2218 return Error(Loc, "unexpected token in argument list");
2220 Parser.Lex(); // Consume the EndOfStatement.
2224 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2225 SMLoc Loc = getLexer().getLoc();
2226 Parser.eatToEndOfStatement();
2227 return Error(Loc, ErrorMsg);
2230 bool MipsAsmParser::parseSetNoAtDirective() {
2231 // Line should look like: ".set noat".
2233 Options.setATReg(0);
2236 // If this is not the end of the statement, report an error.
2237 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2238 reportParseError("unexpected token in statement");
2241 Parser.Lex(); // Consume the EndOfStatement.
2245 bool MipsAsmParser::parseSetAtDirective() {
2246 // Line can be .set at - defaults to $1
2250 if (getLexer().is(AsmToken::EndOfStatement)) {
2251 Options.setATReg(1);
2252 Parser.Lex(); // Consume the EndOfStatement.
2254 } else if (getLexer().is(AsmToken::Equal)) {
2255 getParser().Lex(); // Eat the '='.
2256 if (getLexer().isNot(AsmToken::Dollar)) {
2257 reportParseError("unexpected token in statement");
2260 Parser.Lex(); // Eat the '$'.
2261 const AsmToken &Reg = Parser.getTok();
2262 if (Reg.is(AsmToken::Identifier)) {
2263 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2264 } else if (Reg.is(AsmToken::Integer)) {
2265 AtRegNo = Reg.getIntVal();
2267 reportParseError("unexpected token in statement");
2271 if (AtRegNo < 1 || AtRegNo > 31) {
2272 reportParseError("unexpected token in statement");
2276 if (!Options.setATReg(AtRegNo)) {
2277 reportParseError("unexpected token in statement");
2280 getParser().Lex(); // Eat the register.
2282 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2283 reportParseError("unexpected token in statement");
2286 Parser.Lex(); // Consume the EndOfStatement.
2289 reportParseError("unexpected token in statement");
2294 bool MipsAsmParser::parseSetReorderDirective() {
2296 // If this is not the end of the statement, report an error.
2297 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2298 reportParseError("unexpected token in statement");
2301 Options.setReorder();
2302 Parser.Lex(); // Consume the EndOfStatement.
2306 bool MipsAsmParser::parseSetNoReorderDirective() {
2308 // If this is not the end of the statement, report an error.
2309 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2310 reportParseError("unexpected token in statement");
2313 Options.setNoreorder();
2314 Parser.Lex(); // Consume the EndOfStatement.
2318 bool MipsAsmParser::parseSetMacroDirective() {
2320 // If this is not the end of the statement, report an error.
2321 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2322 reportParseError("unexpected token in statement");
2326 Parser.Lex(); // Consume the EndOfStatement.
2330 bool MipsAsmParser::parseSetNoMacroDirective() {
2332 // If this is not the end of the statement, report an error.
2333 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2334 reportParseError("`noreorder' must be set before `nomacro'");
2337 if (Options.isReorder()) {
2338 reportParseError("`noreorder' must be set before `nomacro'");
2341 Options.setNomacro();
2342 Parser.Lex(); // Consume the EndOfStatement.
2346 bool MipsAsmParser::parseSetMips16Directive() {
2348 // If this is not the end of the statement, report an error.
2349 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2350 reportParseError("unexpected token in statement");
2353 getTargetStreamer().emitDirectiveSetMips16(true);
2354 Parser.Lex(); // Consume the EndOfStatement.
2358 bool MipsAsmParser::parseSetNoMips16Directive() {
2360 // If this is not the end of the statement, report an error.
2361 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2362 reportParseError("unexpected token in statement");
2365 // For now do nothing.
2366 Parser.Lex(); // Consume the EndOfStatement.
2370 bool MipsAsmParser::parseSetAssignment() {
2372 const MCExpr *Value;
2374 if (Parser.parseIdentifier(Name))
2375 reportParseError("expected identifier after .set");
2377 if (getLexer().isNot(AsmToken::Comma))
2378 return reportParseError("unexpected token in .set directive");
2381 if (Parser.parseExpression(Value))
2382 return reportParseError("expected valid expression after comma");
2384 // Check if the Name already exists as a symbol.
2385 MCSymbol *Sym = getContext().LookupSymbol(Name);
2387 return reportParseError("symbol already defined");
2388 Sym = getContext().GetOrCreateSymbol(Name);
2389 Sym->setVariableValue(Value);
2394 bool MipsAsmParser::parseDirectiveSet() {
2396 // Get the next token.
2397 const AsmToken &Tok = Parser.getTok();
2399 if (Tok.getString() == "noat") {
2400 return parseSetNoAtDirective();
2401 } else if (Tok.getString() == "at") {
2402 return parseSetAtDirective();
2403 } else if (Tok.getString() == "reorder") {
2404 return parseSetReorderDirective();
2405 } else if (Tok.getString() == "noreorder") {
2406 return parseSetNoReorderDirective();
2407 } else if (Tok.getString() == "macro") {
2408 return parseSetMacroDirective();
2409 } else if (Tok.getString() == "nomacro") {
2410 return parseSetNoMacroDirective();
2411 } else if (Tok.getString() == "mips16") {
2412 return parseSetMips16Directive();
2413 } else if (Tok.getString() == "nomips16") {
2414 return parseSetNoMips16Directive();
2415 } else if (Tok.getString() == "nomicromips") {
2416 getTargetStreamer().emitDirectiveSetNoMicroMips();
2417 Parser.eatToEndOfStatement();
2419 } else if (Tok.getString() == "micromips") {
2420 getTargetStreamer().emitDirectiveSetMicroMips();
2421 Parser.eatToEndOfStatement();
2424 // It is just an identifier, look for an assignment.
2425 parseSetAssignment();
2432 bool MipsAsmParser::parseDirectiveMipsHackELFFlags() {
2434 if (Parser.parseAbsoluteExpression(Flags)) {
2435 TokError("unexpected token");
2439 getTargetStreamer().emitMipsHackELFFlags(Flags);
2443 /// parseDirectiveWord
2444 /// ::= .word [ expression (, expression)* ]
2445 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
2446 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2448 const MCExpr *Value;
2449 if (getParser().parseExpression(Value))
2452 getParser().getStreamer().EmitValue(Value, Size);
2454 if (getLexer().is(AsmToken::EndOfStatement))
2457 // FIXME: Improve diagnostic.
2458 if (getLexer().isNot(AsmToken::Comma))
2459 return Error(L, "unexpected token in directive");
2468 /// parseDirectiveGpWord
2469 /// ::= .gpword local_sym
2470 bool MipsAsmParser::parseDirectiveGpWord() {
2471 const MCExpr *Value;
2472 // EmitGPRel32Value requires an expression, so we are using base class
2473 // method to evaluate the expression.
2474 if (getParser().parseExpression(Value))
2476 getParser().getStreamer().EmitGPRel32Value(Value);
2478 if (getLexer().isNot(AsmToken::EndOfStatement))
2479 return Error(getLexer().getLoc(), "unexpected token in directive");
2480 Parser.Lex(); // Eat EndOfStatement token.
2484 bool MipsAsmParser::parseDirectiveOption() {
2485 // Get the option token.
2486 AsmToken Tok = Parser.getTok();
2487 // At the moment only identifiers are supported.
2488 if (Tok.isNot(AsmToken::Identifier)) {
2489 Error(Parser.getTok().getLoc(), "unexpected token in .option directive");
2490 Parser.eatToEndOfStatement();
2494 StringRef Option = Tok.getIdentifier();
2496 if (Option == "pic0") {
2497 getTargetStreamer().emitDirectiveOptionPic0();
2499 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2500 Error(Parser.getTok().getLoc(),
2501 "unexpected token in .option pic0 directive");
2502 Parser.eatToEndOfStatement();
2508 Warning(Parser.getTok().getLoc(), "unknown option in .option directive");
2509 Parser.eatToEndOfStatement();
2513 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2514 StringRef IDVal = DirectiveID.getString();
2516 if (IDVal == ".ent") {
2517 // Ignore this directive for now.
2522 if (IDVal == ".end") {
2523 // Ignore this directive for now.
2528 if (IDVal == ".frame") {
2529 // Ignore this directive for now.
2530 Parser.eatToEndOfStatement();
2534 if (IDVal == ".set") {
2535 return parseDirectiveSet();
2538 if (IDVal == ".fmask") {
2539 // Ignore this directive for now.
2540 Parser.eatToEndOfStatement();
2544 if (IDVal == ".mask") {
2545 // Ignore this directive for now.
2546 Parser.eatToEndOfStatement();
2550 if (IDVal == ".gpword") {
2551 // Ignore this directive for now.
2552 parseDirectiveGpWord();
2556 if (IDVal == ".word") {
2557 parseDirectiveWord(4, DirectiveID.getLoc());
2561 if (IDVal == ".mips_hack_elf_flags")
2562 return parseDirectiveMipsHackELFFlags();
2564 if (IDVal == ".option")
2565 return parseDirectiveOption();
2567 if (IDVal == ".abicalls") {
2568 getTargetStreamer().emitDirectiveAbiCalls();
2569 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2570 Error(Parser.getTok().getLoc(), "unexpected token in directive");
2572 Parser.eatToEndOfStatement();
2580 extern "C" void LLVMInitializeMipsAsmParser() {
2581 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2582 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2583 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2584 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2587 #define GET_REGISTER_MATCHER
2588 #define GET_MATCHER_IMPLEMENTATION
2589 #include "MipsGenAsmMatcher.inc"