1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCParser/MCAsmLexer.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/MC/MCTargetAsmParser.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/ADT/APInt.h"
32 class MipsAssemblerOptions {
34 MipsAssemblerOptions():
35 aTReg(1), reorder(true), macro(true) {
38 unsigned getATRegNum() {return aTReg;}
39 bool setATReg(unsigned Reg);
41 bool isReorder() {return reorder;}
42 void setReorder() {reorder = true;}
43 void setNoreorder() {reorder = false;}
45 bool isMacro() {return macro;}
46 void setMacro() {macro = true;}
47 void setNomacro() {macro = false;}
57 class MipsAsmParser : public MCTargetAsmParser {
61 MipsAssemblerOptions Options;
62 bool hasConsumedDollar;
64 #define GET_ASSEMBLER_HEADER
65 #include "MipsGenAsmMatcher.inc"
67 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
68 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
69 MCStreamer &Out, unsigned &ErrorInfo,
70 bool MatchingInlineAsm);
72 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
74 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
76 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
78 bool ParseDirective(AsmToken DirectiveID);
80 MipsAsmParser::OperandMatchResultTy
81 parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
84 MipsAsmParser::OperandMatchResultTy
85 parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
88 MipsAsmParser::OperandMatchResultTy
89 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
91 bool parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands, int RegKind);
93 MipsAsmParser::OperandMatchResultTy
94 parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
96 MipsAsmParser::OperandMatchResultTy
97 parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
99 MipsAsmParser::OperandMatchResultTy
100 parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
102 MipsAsmParser::OperandMatchResultTy
103 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
105 MipsAsmParser::OperandMatchResultTy
106 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
108 MipsAsmParser::OperandMatchResultTy
109 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
111 MipsAsmParser::OperandMatchResultTy
112 parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
114 MipsAsmParser::OperandMatchResultTy
115 parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
117 MipsAsmParser::OperandMatchResultTy
118 parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
120 MipsAsmParser::OperandMatchResultTy
121 parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
123 MipsAsmParser::OperandMatchResultTy
124 parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
126 MipsAsmParser::OperandMatchResultTy
127 parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
129 MipsAsmParser::OperandMatchResultTy
130 parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
132 MipsAsmParser::OperandMatchResultTy
133 parseCOP2(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
135 MipsAsmParser::OperandMatchResultTy
136 parseMSA128BRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
138 MipsAsmParser::OperandMatchResultTy
139 parseMSA128HRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
141 MipsAsmParser::OperandMatchResultTy
142 parseMSA128WRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
144 MipsAsmParser::OperandMatchResultTy
145 parseMSA128DRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
147 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
150 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
153 int tryParseRegister(bool is64BitReg);
155 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
158 bool needsExpansion(MCInst &Inst);
160 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
161 SmallVectorImpl<MCInst> &Instructions);
162 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
163 SmallVectorImpl<MCInst> &Instructions);
164 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
165 SmallVectorImpl<MCInst> &Instructions);
166 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
167 SmallVectorImpl<MCInst> &Instructions);
168 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
169 SmallVectorImpl<MCInst> &Instructions,
170 bool isLoad,bool isImmOpnd);
171 bool reportParseError(StringRef ErrorMsg);
173 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
174 bool parseRelocOperand(const MCExpr *&Res);
176 const MCExpr* evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
178 bool isEvaluated(const MCExpr *Expr);
179 bool parseDirectiveSet();
181 bool parseSetAtDirective();
182 bool parseSetNoAtDirective();
183 bool parseSetMacroDirective();
184 bool parseSetNoMacroDirective();
185 bool parseSetReorderDirective();
186 bool parseSetNoReorderDirective();
188 bool parseSetAssignment();
190 bool parseDirectiveWord(unsigned Size, SMLoc L);
192 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
194 bool isMips64() const {
195 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
198 bool isFP64() const {
199 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
203 return STI.getFeatureBits() & Mips::FeatureN64;
206 int matchRegisterName(StringRef Symbol, bool is64BitReg);
208 int matchCPURegisterName(StringRef Symbol);
210 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
212 int matchFPURegisterName(StringRef Name);
214 int matchFCCRegisterName(StringRef Name);
216 int matchACRegisterName(StringRef Name);
218 int matchMSA128RegisterName(StringRef Name);
220 int regKindToRegClass(int RegKind);
222 unsigned getReg(int RC, int RegNo);
226 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
227 SmallVectorImpl<MCInst> &Instructions);
229 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
230 const MCInstrInfo &MII)
231 : MCTargetAsmParser(), STI(sti), Parser(parser),
232 hasConsumedDollar(false) {
233 // Initialize the set of available features.
234 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
237 MCAsmParser &getParser() const { return Parser; }
238 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
245 /// MipsOperand - Instances of this class represent a parsed Mips machine
247 class MipsOperand : public MCParsedAsmOperand {
283 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
311 SMLoc StartLoc, EndLoc;
314 void addRegOperands(MCInst &Inst, unsigned N) const {
315 assert(N == 1 && "Invalid number of operands!");
316 Inst.addOperand(MCOperand::CreateReg(getReg()));
319 void addPtrRegOperands(MCInst &Inst, unsigned N) const {
320 assert(N == 1 && "Invalid number of operands!");
321 Inst.addOperand(MCOperand::CreateReg(getPtrReg()));
324 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
325 // Add as immediate when possible. Null MCExpr = 0.
327 Inst.addOperand(MCOperand::CreateImm(0));
328 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
329 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
331 Inst.addOperand(MCOperand::CreateExpr(Expr));
334 void addImmOperands(MCInst &Inst, unsigned N) const {
335 assert(N == 1 && "Invalid number of operands!");
336 const MCExpr *Expr = getImm();
340 void addMemOperands(MCInst &Inst, unsigned N) const {
341 assert(N == 2 && "Invalid number of operands!");
343 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
345 const MCExpr *Expr = getMemOff();
349 bool isReg() const { return Kind == k_Register; }
350 bool isImm() const { return Kind == k_Immediate; }
351 bool isToken() const { return Kind == k_Token; }
352 bool isMem() const { return Kind == k_Memory; }
353 bool isPtrReg() const { return Kind == k_PtrReg; }
355 StringRef getToken() const {
356 assert(Kind == k_Token && "Invalid access!");
357 return StringRef(Tok.Data, Tok.Length);
360 unsigned getReg() const {
361 assert((Kind == k_Register) && "Invalid access!");
365 unsigned getPtrReg() const {
366 assert((Kind == k_PtrReg) && "Invalid access!");
370 void setRegKind(RegisterKind RegKind) {
371 assert((Kind == k_Register || Kind == k_PtrReg) && "Invalid access!");
375 const MCExpr *getImm() const {
376 assert((Kind == k_Immediate) && "Invalid access!");
380 unsigned getMemBase() const {
381 assert((Kind == k_Memory) && "Invalid access!");
385 const MCExpr *getMemOff() const {
386 assert((Kind == k_Memory) && "Invalid access!");
390 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
391 MipsOperand *Op = new MipsOperand(k_Token);
392 Op->Tok.Data = Str.data();
393 Op->Tok.Length = Str.size();
399 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
400 MipsOperand *Op = new MipsOperand(k_Register);
401 Op->Reg.RegNum = RegNum;
407 static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) {
408 MipsOperand *Op = new MipsOperand(k_PtrReg);
409 Op->Reg.RegNum = RegNum;
415 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
416 MipsOperand *Op = new MipsOperand(k_Immediate);
423 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
425 MipsOperand *Op = new MipsOperand(k_Memory);
433 bool isGPR32Asm() const {
434 return Kind == k_Register && Reg.Kind == Kind_GPR32;
436 void addRegAsmOperands(MCInst &Inst, unsigned N) const {
437 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
440 bool isGPR64Asm() const {
441 return Kind == k_Register && Reg.Kind == Kind_GPR64;
444 bool isHWRegsAsm() const {
445 assert((Kind == k_Register) && "Invalid access!");
446 return Reg.Kind == Kind_HWRegs;
449 bool isCCRAsm() const {
450 assert((Kind == k_Register) && "Invalid access!");
451 return Reg.Kind == Kind_CCRRegs;
454 bool isAFGR64Asm() const {
455 return Kind == k_Register && Reg.Kind == Kind_AFGR64Regs;
458 bool isFGR64Asm() const {
459 return Kind == k_Register && Reg.Kind == Kind_FGR64Regs;
462 bool isFGR32Asm() const {
463 return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
466 bool isFGRH32Asm() const {
467 return (Kind == k_Register) && Reg.Kind == Kind_FGRH32Regs;
470 bool isFCCRegsAsm() const {
471 return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
474 bool isACC64DSPAsm() const {
475 return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
478 bool isLO32DSPAsm() const {
479 return Kind == k_Register && Reg.Kind == Kind_LO32DSP;
482 bool isHI32DSPAsm() const {
483 return Kind == k_Register && Reg.Kind == Kind_HI32DSP;
486 bool isCOP2Asm() const {
487 return Kind == k_Register && Reg.Kind == Kind_COP2;
490 bool isMSA128BAsm() const {
491 return Kind == k_Register && Reg.Kind == Kind_MSA128BRegs;
494 bool isMSA128HAsm() const {
495 return Kind == k_Register && Reg.Kind == Kind_MSA128HRegs;
498 bool isMSA128WAsm() const {
499 return Kind == k_Register && Reg.Kind == Kind_MSA128WRegs;
502 bool isMSA128DAsm() const {
503 return Kind == k_Register && Reg.Kind == Kind_MSA128DRegs;
506 /// getStartLoc - Get the location of the first token of this operand.
507 SMLoc getStartLoc() const {
510 /// getEndLoc - Get the location of the last token of this operand.
511 SMLoc getEndLoc() const {
515 virtual void print(raw_ostream &OS) const {
516 llvm_unreachable("unimplemented!");
518 }; // class MipsOperand
522 extern const MCInstrDesc MipsInsts[];
524 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
525 return MipsInsts[Opcode];
528 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
529 SmallVectorImpl<MCInst> &Instructions) {
530 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
532 if (MCID.hasDelaySlot() && Options.isReorder()) {
533 // If this instruction has a delay slot and .set reorder is active,
534 // emit a NOP after it.
535 Instructions.push_back(Inst);
537 NopInst.setOpcode(Mips::SLL);
538 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
539 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
540 NopInst.addOperand(MCOperand::CreateImm(0));
541 Instructions.push_back(NopInst);
545 if (MCID.mayLoad() || MCID.mayStore()) {
546 // Check the offset of memory operand, if it is a symbol
547 // reference or immediate we may have to expand instructions.
548 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
549 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
550 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY)
551 || (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
552 MCOperand &Op = Inst.getOperand(i);
554 int MemOffset = Op.getImm();
555 if (MemOffset < -32768 || MemOffset > 32767) {
556 // Offset can't exceed 16bit value.
557 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
560 } else if (Op.isExpr()) {
561 const MCExpr *Expr = Op.getExpr();
562 if (Expr->getKind() == MCExpr::SymbolRef) {
563 const MCSymbolRefExpr *SR =
564 static_cast<const MCSymbolRefExpr*>(Expr);
565 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
567 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
570 } else if (!isEvaluated(Expr)) {
571 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
579 if (needsExpansion(Inst))
580 expandInstruction(Inst, IDLoc, Instructions);
582 Instructions.push_back(Inst);
587 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
589 switch (Inst.getOpcode()) {
590 case Mips::LoadImm32Reg:
591 case Mips::LoadAddr32Imm:
592 case Mips::LoadAddr32Reg:
599 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
600 SmallVectorImpl<MCInst> &Instructions) {
601 switch (Inst.getOpcode()) {
602 case Mips::LoadImm32Reg:
603 return expandLoadImm(Inst, IDLoc, Instructions);
604 case Mips::LoadAddr32Imm:
605 return expandLoadAddressImm(Inst, IDLoc, Instructions);
606 case Mips::LoadAddr32Reg:
607 return expandLoadAddressReg(Inst, IDLoc, Instructions);
611 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
612 SmallVectorImpl<MCInst> &Instructions) {
614 const MCOperand &ImmOp = Inst.getOperand(1);
615 assert(ImmOp.isImm() && "expected immediate operand kind");
616 const MCOperand &RegOp = Inst.getOperand(0);
617 assert(RegOp.isReg() && "expected register operand kind");
619 int ImmValue = ImmOp.getImm();
620 tmpInst.setLoc(IDLoc);
621 if (0 <= ImmValue && ImmValue <= 65535) {
622 // For 0 <= j <= 65535.
623 // li d,j => ori d,$zero,j
624 tmpInst.setOpcode(Mips::ORi);
625 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
626 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
627 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
628 Instructions.push_back(tmpInst);
629 } else if (ImmValue < 0 && ImmValue >= -32768) {
630 // For -32768 <= j < 0.
631 // li d,j => addiu d,$zero,j
632 tmpInst.setOpcode(Mips::ADDiu);
633 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
634 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
635 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
636 Instructions.push_back(tmpInst);
638 // For any other value of j that is representable as a 32-bit integer.
639 // li d,j => lui d,hi16(j)
641 tmpInst.setOpcode(Mips::LUi);
642 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
643 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
644 Instructions.push_back(tmpInst);
646 tmpInst.setOpcode(Mips::ORi);
647 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
648 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
649 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
650 tmpInst.setLoc(IDLoc);
651 Instructions.push_back(tmpInst);
655 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
656 SmallVectorImpl<MCInst> &Instructions) {
658 const MCOperand &ImmOp = Inst.getOperand(2);
659 assert(ImmOp.isImm() && "expected immediate operand kind");
660 const MCOperand &SrcRegOp = Inst.getOperand(1);
661 assert(SrcRegOp.isReg() && "expected register operand kind");
662 const MCOperand &DstRegOp = Inst.getOperand(0);
663 assert(DstRegOp.isReg() && "expected register operand kind");
664 int ImmValue = ImmOp.getImm();
665 if (-32768 <= ImmValue && ImmValue <= 65535) {
666 // For -32768 <= j <= 65535.
667 // la d,j(s) => addiu d,s,j
668 tmpInst.setOpcode(Mips::ADDiu);
669 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
670 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
671 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
672 Instructions.push_back(tmpInst);
674 // For any other value of j that is representable as a 32-bit integer.
675 // la d,j(s) => lui d,hi16(j)
678 tmpInst.setOpcode(Mips::LUi);
679 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
680 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
681 Instructions.push_back(tmpInst);
683 tmpInst.setOpcode(Mips::ORi);
684 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
685 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
686 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
687 Instructions.push_back(tmpInst);
689 tmpInst.setOpcode(Mips::ADDu);
690 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
691 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
692 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
693 Instructions.push_back(tmpInst);
697 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
698 SmallVectorImpl<MCInst> &Instructions) {
700 const MCOperand &ImmOp = Inst.getOperand(1);
701 assert(ImmOp.isImm() && "expected immediate operand kind");
702 const MCOperand &RegOp = Inst.getOperand(0);
703 assert(RegOp.isReg() && "expected register operand kind");
704 int ImmValue = ImmOp.getImm();
705 if (-32768 <= ImmValue && ImmValue <= 65535) {
706 // For -32768 <= j <= 65535.
707 // la d,j => addiu d,$zero,j
708 tmpInst.setOpcode(Mips::ADDiu);
709 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
710 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
711 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
712 Instructions.push_back(tmpInst);
714 // For any other value of j that is representable as a 32-bit integer.
715 // la d,j => lui d,hi16(j)
717 tmpInst.setOpcode(Mips::LUi);
718 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
719 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
720 Instructions.push_back(tmpInst);
722 tmpInst.setOpcode(Mips::ORi);
723 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
724 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
725 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
726 Instructions.push_back(tmpInst);
730 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
731 SmallVectorImpl<MCInst> &Instructions, bool isLoad, bool isImmOpnd) {
732 const MCSymbolRefExpr *SR;
734 unsigned ImmOffset, HiOffset, LoOffset;
735 const MCExpr *ExprOffset;
737 unsigned AtRegNum = getReg((isMips64()) ? Mips::GPR64RegClassID
738 : Mips::GPR32RegClassID, getATReg());
739 // 1st operand is either the source or destination register.
740 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
741 unsigned RegOpNum = Inst.getOperand(0).getReg();
742 // 2nd operand is the base register.
743 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
744 unsigned BaseRegNum = Inst.getOperand(1).getReg();
745 // 3rd operand is either an immediate or expression.
747 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
748 ImmOffset = Inst.getOperand(2).getImm();
749 LoOffset = ImmOffset & 0x0000ffff;
750 HiOffset = (ImmOffset & 0xffff0000) >> 16;
751 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
752 if (LoOffset & 0x8000)
755 ExprOffset = Inst.getOperand(2).getExpr();
756 // All instructions will have the same location.
757 TempInst.setLoc(IDLoc);
758 // 1st instruction in expansion is LUi. For load instruction we can use
759 // the dst register as a temporary if base and dst are different,
760 // but for stores we must use $at.
761 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
762 TempInst.setOpcode(Mips::LUi);
763 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
765 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
767 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
768 SR = static_cast<const MCSymbolRefExpr*>(ExprOffset);
769 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
770 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
772 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
774 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
775 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
778 // Add the instruction to the list.
779 Instructions.push_back(TempInst);
780 // Prepare TempInst for next instruction.
782 // Add temp register to base.
783 TempInst.setOpcode(Mips::ADDu);
784 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
785 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
786 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
787 Instructions.push_back(TempInst);
789 // And finaly, create original instruction with low part
790 // of offset and new base.
791 TempInst.setOpcode(Inst.getOpcode());
792 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
793 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
795 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
797 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
798 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
799 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
801 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
803 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
804 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
807 Instructions.push_back(TempInst);
812 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
813 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
814 MCStreamer &Out, unsigned &ErrorInfo,
815 bool MatchingInlineAsm) {
817 SmallVector<MCInst, 8> Instructions;
818 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
821 switch (MatchResult) {
824 case Match_Success: {
825 if (processInstruction(Inst, IDLoc, Instructions))
827 for (unsigned i = 0; i < Instructions.size(); i++)
828 Out.EmitInstruction(Instructions[i]);
831 case Match_MissingFeature:
832 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
834 case Match_InvalidOperand: {
835 SMLoc ErrorLoc = IDLoc;
836 if (ErrorInfo != ~0U) {
837 if (ErrorInfo >= Operands.size())
838 return Error(IDLoc, "too few operands for instruction");
840 ErrorLoc = ((MipsOperand*) Operands[ErrorInfo])->getStartLoc();
841 if (ErrorLoc == SMLoc())
845 return Error(ErrorLoc, "invalid operand for instruction");
847 case Match_MnemonicFail:
848 return Error(IDLoc, "invalid instruction");
853 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
859 CC = StringSwitch<unsigned>(Name)
893 // Although SGI documentation just cuts out t0-t3 for n32/n64,
894 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
895 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
896 if (isMips64() && 8 <= CC && CC <= 11)
899 if (CC == -1 && isMips64())
900 CC = StringSwitch<unsigned>(Name)
913 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
915 if (Name[0] == 'f') {
916 StringRef NumString = Name.substr(1);
918 if (NumString.getAsInteger(10, IntVal))
919 return -1; // This is not an integer.
920 if (IntVal > 31) // Maximum index for fpu register.
927 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
929 if (Name.startswith("fcc")) {
930 StringRef NumString = Name.substr(3);
932 if (NumString.getAsInteger(10, IntVal))
933 return -1; // This is not an integer.
934 if (IntVal > 7) // There are only 8 fcc registers.
941 int MipsAsmParser::matchACRegisterName(StringRef Name) {
943 if (Name.startswith("ac")) {
944 StringRef NumString = Name.substr(2);
946 if (NumString.getAsInteger(10, IntVal))
947 return -1; // This is not an integer.
948 if (IntVal > 3) // There are only 3 acc registers.
955 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
958 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
967 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
970 CC = matchCPURegisterName(Name);
972 return matchRegisterByNumber(CC, is64BitReg ? Mips::GPR64RegClassID
973 : Mips::GPR32RegClassID);
974 CC = matchFPURegisterName(Name);
975 //TODO: decide about fpu register class
977 return matchRegisterByNumber(CC, isFP64() ? Mips::FGR64RegClassID
978 : Mips::FGR32RegClassID);
979 return matchMSA128RegisterName(Name);
982 int MipsAsmParser::regKindToRegClass(int RegKind) {
985 case MipsOperand::Kind_GPR32: return Mips::GPR32RegClassID;
986 case MipsOperand::Kind_GPR64: return Mips::GPR64RegClassID;
987 case MipsOperand::Kind_HWRegs: return Mips::HWRegsRegClassID;
988 case MipsOperand::Kind_FGR32Regs: return Mips::FGR32RegClassID;
989 case MipsOperand::Kind_FGRH32Regs: return Mips::FGRH32RegClassID;
990 case MipsOperand::Kind_FGR64Regs: return Mips::FGR64RegClassID;
991 case MipsOperand::Kind_AFGR64Regs: return Mips::AFGR64RegClassID;
992 case MipsOperand::Kind_CCRRegs: return Mips::CCRRegClassID;
993 case MipsOperand::Kind_ACC64DSP: return Mips::ACC64DSPRegClassID;
994 case MipsOperand::Kind_FCCRegs: return Mips::FCCRegClassID;
995 case MipsOperand::Kind_MSA128BRegs: return Mips::MSA128BRegClassID;
996 case MipsOperand::Kind_MSA128HRegs: return Mips::MSA128HRegClassID;
997 case MipsOperand::Kind_MSA128WRegs: return Mips::MSA128WRegClassID;
998 case MipsOperand::Kind_MSA128DRegs: return Mips::MSA128DRegClassID;
1004 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1012 int MipsAsmParser::getATReg() {
1013 return Options.getATRegNum();
1016 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1017 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1020 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1022 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
1025 return getReg(RegClass, RegNum);
1028 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
1029 const AsmToken &Tok = Parser.getTok();
1032 if (Tok.is(AsmToken::Identifier)) {
1033 std::string lowerCase = Tok.getString().lower();
1034 RegNum = matchRegisterName(lowerCase, is64BitReg);
1035 } else if (Tok.is(AsmToken::Integer))
1036 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
1037 is64BitReg ? Mips::GPR64RegClassID : Mips::GPR32RegClassID);
1041 bool MipsAsmParser::tryParseRegisterOperand(
1042 SmallVectorImpl<MCParsedAsmOperand*> &Operands, bool is64BitReg) {
1044 SMLoc S = Parser.getTok().getLoc();
1047 RegNo = tryParseRegister(is64BitReg);
1051 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
1052 Parser.getTok().getLoc()));
1053 Parser.Lex(); // Eat register token.
1057 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
1058 StringRef Mnemonic) {
1059 // Check if the current operand has a custom associated parser, if so, try to
1060 // custom parse the operand, or fallback to the general approach.
1061 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1062 if (ResTy == MatchOperand_Success)
1064 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1065 // there was a match, but an error occurred, in which case, just return that
1066 // the operand parsing failed.
1067 if (ResTy == MatchOperand_ParseFail)
1070 switch (getLexer().getKind()) {
1072 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1074 case AsmToken::Dollar: {
1075 // Parse the register.
1076 SMLoc S = Parser.getTok().getLoc();
1077 Parser.Lex(); // Eat dollar token.
1078 // Parse the register operand.
1079 if (!tryParseRegisterOperand(Operands, isMips64())) {
1080 if (getLexer().is(AsmToken::LParen)) {
1081 // Check if it is indexed addressing operand.
1082 Operands.push_back(MipsOperand::CreateToken("(", S));
1083 Parser.Lex(); // Eat the parenthesis.
1084 if (getLexer().isNot(AsmToken::Dollar))
1087 Parser.Lex(); // Eat the dollar
1088 if (tryParseRegisterOperand(Operands, isMips64()))
1091 if (!getLexer().is(AsmToken::RParen))
1094 S = Parser.getTok().getLoc();
1095 Operands.push_back(MipsOperand::CreateToken(")", S));
1100 // Maybe it is a symbol reference.
1101 StringRef Identifier;
1102 if (Parser.parseIdentifier(Identifier))
1105 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1107 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1109 // Otherwise create a symbol reference.
1110 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
1113 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1116 case AsmToken::Identifier:
1117 // Look for the existing symbol, we should check if
1118 // we need to assigne the propper RegisterKind.
1119 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
1121 // Else drop to expression parsing.
1122 case AsmToken::LParen:
1123 case AsmToken::Minus:
1124 case AsmToken::Plus:
1125 case AsmToken::Integer:
1126 case AsmToken::String: {
1127 // Quoted label names.
1128 const MCExpr *IdVal;
1129 SMLoc S = Parser.getTok().getLoc();
1130 if (getParser().parseExpression(IdVal))
1132 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1133 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1136 case AsmToken::Percent: {
1137 // It is a symbol reference or constant expression.
1138 const MCExpr *IdVal;
1139 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1140 if (parseRelocOperand(IdVal))
1143 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1145 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1147 } // case AsmToken::Percent
1148 } // switch(getLexer().getKind())
1152 const MCExpr* MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1153 StringRef RelocStr) {
1155 // Check the type of the expression.
1156 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1157 // It's a constant, evaluate lo or hi value.
1158 if (RelocStr == "lo") {
1159 short Val = MCE->getValue();
1160 Res = MCConstantExpr::Create(Val, getContext());
1161 } else if (RelocStr == "hi") {
1162 int Val = MCE->getValue();
1163 int LoSign = Val & 0x8000;
1164 Val = (Val & 0xffff0000) >> 16;
1165 // Lower part is treated as a signed int, so if it is negative
1166 // we must add 1 to the hi part to compensate.
1169 Res = MCConstantExpr::Create(Val, getContext());
1171 llvm_unreachable("Invalid RelocStr value");
1176 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1177 // It's a symbol, create a symbolic expression from the symbol.
1178 StringRef Symbol = MSRE->getSymbol().getName();
1179 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1180 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1184 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1185 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1186 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1187 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1191 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1192 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1193 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1196 // Just return the original expression.
1200 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1202 switch (Expr->getKind()) {
1203 case MCExpr::Constant:
1205 case MCExpr::SymbolRef:
1206 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1207 case MCExpr::Binary:
1208 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1209 if (!isEvaluated(BE->getLHS()))
1211 return isEvaluated(BE->getRHS());
1214 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1221 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1222 Parser.Lex(); // Eat the % token.
1223 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1224 if (Tok.isNot(AsmToken::Identifier))
1227 std::string Str = Tok.getIdentifier().str();
1229 Parser.Lex(); // Eat the identifier.
1230 // Now make an expression from the rest of the operand.
1231 const MCExpr *IdVal;
1234 if (getLexer().getKind() == AsmToken::LParen) {
1236 Parser.Lex(); // Eat the '(' token.
1237 if (getLexer().getKind() == AsmToken::Percent) {
1238 Parser.Lex(); // Eat the % token.
1239 const AsmToken &nextTok = Parser.getTok();
1240 if (nextTok.isNot(AsmToken::Identifier))
1243 Str += nextTok.getIdentifier();
1244 Parser.Lex(); // Eat the identifier.
1245 if (getLexer().getKind() != AsmToken::LParen)
1250 if (getParser().parseParenExpression(IdVal, EndLoc))
1253 while (getLexer().getKind() == AsmToken::RParen)
1254 Parser.Lex(); // Eat the ')' token.
1257 return true; // Parenthesis must follow the relocation operand.
1259 Res = evaluateRelocExpr(IdVal, Str);
1263 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1265 StartLoc = Parser.getTok().getLoc();
1266 RegNo = tryParseRegister(isMips64());
1267 EndLoc = Parser.getTok().getLoc();
1268 return (RegNo == (unsigned) -1);
1271 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1275 while (getLexer().getKind() == AsmToken::LParen)
1278 switch (getLexer().getKind()) {
1281 case AsmToken::Identifier:
1282 case AsmToken::LParen:
1283 case AsmToken::Integer:
1284 case AsmToken::Minus:
1285 case AsmToken::Plus:
1287 Result = getParser().parseParenExpression(Res, S);
1289 Result = (getParser().parseExpression(Res));
1290 while (getLexer().getKind() == AsmToken::RParen)
1293 case AsmToken::Percent:
1294 Result = parseRelocOperand(Res);
1299 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1300 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
1302 const MCExpr *IdVal = 0;
1304 bool isParenExpr = false;
1305 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1306 // First operand is the offset.
1307 S = Parser.getTok().getLoc();
1309 if (getLexer().getKind() == AsmToken::LParen) {
1314 if (getLexer().getKind() != AsmToken::Dollar) {
1315 if (parseMemOffset(IdVal, isParenExpr))
1316 return MatchOperand_ParseFail;
1318 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1319 if (Tok.isNot(AsmToken::LParen)) {
1320 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
1321 if (Mnemonic->getToken() == "la") {
1322 SMLoc E = SMLoc::getFromPointer(
1323 Parser.getTok().getLoc().getPointer() - 1);
1324 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1325 return MatchOperand_Success;
1327 if (Tok.is(AsmToken::EndOfStatement)) {
1328 SMLoc E = SMLoc::getFromPointer(
1329 Parser.getTok().getLoc().getPointer() - 1);
1331 // Zero register assumed, add a memory operand with ZERO as its base.
1332 Operands.push_back(MipsOperand::CreateMem(isMips64() ? Mips::ZERO_64
1335 return MatchOperand_Success;
1337 Error(Parser.getTok().getLoc(), "'(' expected");
1338 return MatchOperand_ParseFail;
1341 Parser.Lex(); // Eat the '(' token.
1344 Res = parseRegs(Operands, isMips64()? (int) MipsOperand::Kind_GPR64:
1345 (int) MipsOperand::Kind_GPR32);
1346 if (Res != MatchOperand_Success)
1349 if (Parser.getTok().isNot(AsmToken::RParen)) {
1350 Error(Parser.getTok().getLoc(), "')' expected");
1351 return MatchOperand_ParseFail;
1354 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1356 Parser.Lex(); // Eat the ')' token.
1359 IdVal = MCConstantExpr::Create(0, getContext());
1361 // Replace the register operand with the memory operand.
1362 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1363 int RegNo = op->getReg();
1364 // Remove the register from the operands.
1365 Operands.pop_back();
1366 // Add the memory operand.
1367 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1369 if (IdVal->EvaluateAsAbsolute(Imm))
1370 IdVal = MCConstantExpr::Create(Imm, getContext());
1371 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1372 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1376 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1378 return MatchOperand_Success;
1382 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1384 // If the first token is not '$' we have an error.
1385 if (Parser.getTok().isNot(AsmToken::Dollar))
1388 SMLoc S = Parser.getTok().getLoc();
1390 AsmToken::TokenKind TkKind = getLexer().getKind();
1393 if (TkKind == AsmToken::Integer) {
1394 Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
1395 regKindToRegClass(RegKind));
1398 } else if (TkKind == AsmToken::Identifier) {
1399 if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
1401 Reg = getReg(regKindToRegClass(RegKind), Reg);
1406 MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
1407 Op->setRegKind((MipsOperand::RegisterKind)RegKind);
1408 Operands.push_back(Op);
1413 MipsAsmParser::OperandMatchResultTy
1414 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1415 MipsOperand::RegisterKind RegKind = isN64() ? MipsOperand::Kind_GPR64 :
1416 MipsOperand::Kind_GPR32;
1418 // Parse index register.
1419 if (!parsePtrReg(Operands, RegKind))
1420 return MatchOperand_NoMatch;
1423 if (Parser.getTok().isNot(AsmToken::LParen))
1424 return MatchOperand_NoMatch;
1426 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1429 // Parse base register.
1430 if (!parsePtrReg(Operands, RegKind))
1431 return MatchOperand_NoMatch;
1434 if (Parser.getTok().isNot(AsmToken::RParen))
1435 return MatchOperand_NoMatch;
1437 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1440 return MatchOperand_Success;
1443 MipsAsmParser::OperandMatchResultTy
1444 MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1446 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1447 if (getLexer().getKind() == AsmToken::Identifier
1448 && !hasConsumedDollar) {
1449 if (searchSymbolAlias(Operands, Kind))
1450 return MatchOperand_Success;
1451 return MatchOperand_NoMatch;
1453 SMLoc S = Parser.getTok().getLoc();
1454 // If the first token is not '$', we have an error.
1455 if (Parser.getTok().isNot(AsmToken::Dollar) && !hasConsumedDollar)
1456 return MatchOperand_NoMatch;
1457 if (!hasConsumedDollar) {
1458 Parser.Lex(); // Eat the '$'
1459 hasConsumedDollar = true;
1461 if (getLexer().getKind() == AsmToken::Identifier) {
1463 std::string RegName = Parser.getTok().getString().lower();
1464 // Match register by name
1466 case MipsOperand::Kind_GPR32:
1467 case MipsOperand::Kind_GPR64:
1468 RegNum = matchCPURegisterName(RegName);
1470 case MipsOperand::Kind_AFGR64Regs:
1471 case MipsOperand::Kind_FGR64Regs:
1472 case MipsOperand::Kind_FGR32Regs:
1473 case MipsOperand::Kind_FGRH32Regs:
1474 RegNum = matchFPURegisterName(RegName);
1475 if (RegKind == MipsOperand::Kind_AFGR64Regs)
1477 else if (RegKind == MipsOperand::Kind_FGRH32Regs
1479 if (RegNum != -1 && RegNum %2 != 0)
1480 Warning(S, "Float register should be even.");
1482 case MipsOperand::Kind_FCCRegs:
1483 RegNum = matchFCCRegisterName(RegName);
1485 case MipsOperand::Kind_ACC64DSP:
1486 RegNum = matchACRegisterName(RegName);
1488 default: break; // No match, value is set to -1.
1490 // No match found, return _NoMatch to give a chance to other round.
1492 return MatchOperand_NoMatch;
1494 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1496 return MatchOperand_NoMatch;
1498 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S,
1499 Parser.getTok().getLoc());
1500 Op->setRegKind(Kind);
1501 Operands.push_back(Op);
1502 hasConsumedDollar = false;
1503 Parser.Lex(); // Eat the register name.
1504 return MatchOperand_Success;
1505 } else if (getLexer().getKind() == AsmToken::Integer) {
1506 unsigned RegNum = Parser.getTok().getIntVal();
1507 if (Kind == MipsOperand::Kind_HWRegs) {
1509 return MatchOperand_NoMatch;
1510 // Only hwreg 29 is supported, found at index 0.
1513 int Reg = matchRegisterByNumber(RegNum, regKindToRegClass(Kind));
1515 return MatchOperand_NoMatch;
1516 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1517 Op->setRegKind(Kind);
1518 Operands.push_back(Op);
1519 hasConsumedDollar = false;
1520 Parser.Lex(); // Eat the register number.
1521 if ((RegKind == MipsOperand::Kind_GPR32)
1522 && (getLexer().is(AsmToken::LParen))) {
1523 // Check if it is indexed addressing operand.
1524 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1525 Parser.Lex(); // Eat the parenthesis.
1526 if (parseRegs(Operands,RegKind) != MatchOperand_Success)
1527 return MatchOperand_NoMatch;
1528 if (getLexer().isNot(AsmToken::RParen))
1529 return MatchOperand_NoMatch;
1530 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1533 return MatchOperand_Success;
1535 return MatchOperand_NoMatch;
1538 MipsAsmParser::OperandMatchResultTy
1539 MipsAsmParser::parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1541 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1542 SMLoc S = Parser.getTok().getLoc();
1543 std::string RegName;
1545 if (Parser.getTok().isNot(AsmToken::Dollar))
1546 return MatchOperand_NoMatch;
1550 return MatchOperand_ParseFail;
1551 case MipsOperand::Kind_MSA128BRegs:
1552 case MipsOperand::Kind_MSA128HRegs:
1553 case MipsOperand::Kind_MSA128WRegs:
1554 case MipsOperand::Kind_MSA128DRegs:
1558 Parser.Lex(); // Eat the '$'.
1559 if (getLexer().getKind() == AsmToken::Identifier)
1560 RegName = Parser.getTok().getString().lower();
1562 return MatchOperand_ParseFail;
1564 int RegNum = matchMSA128RegisterName(RegName);
1566 if (RegNum < 0 || RegNum > 31)
1567 return MatchOperand_ParseFail;
1569 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1571 return MatchOperand_ParseFail;
1573 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S,
1574 Parser.getTok().getLoc());
1575 Op->setRegKind(Kind);
1576 Operands.push_back(Op);
1578 Parser.Lex(); // Eat the register identifier.
1580 return MatchOperand_Success;
1583 MipsAsmParser::OperandMatchResultTy
1584 MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1587 return MatchOperand_NoMatch;
1588 return parseRegs(Operands, (int) MipsOperand::Kind_GPR64);
1591 MipsAsmParser::OperandMatchResultTy
1592 MipsAsmParser::parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1593 return parseRegs(Operands, (int) MipsOperand::Kind_GPR32);
1596 MipsAsmParser::OperandMatchResultTy
1597 MipsAsmParser::parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1600 return MatchOperand_NoMatch;
1601 return parseRegs(Operands, (int) MipsOperand::Kind_AFGR64Regs);
1604 MipsAsmParser::OperandMatchResultTy
1605 MipsAsmParser::parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1607 return MatchOperand_NoMatch;
1608 return parseRegs(Operands, (int) MipsOperand::Kind_FGR64Regs);
1611 MipsAsmParser::OperandMatchResultTy
1612 MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1613 return parseRegs(Operands, (int) MipsOperand::Kind_FGR32Regs);
1616 MipsAsmParser::OperandMatchResultTy
1617 MipsAsmParser::parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1618 return parseRegs(Operands, (int) MipsOperand::Kind_FGRH32Regs);
1621 MipsAsmParser::OperandMatchResultTy
1622 MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1623 return parseRegs(Operands, (int) MipsOperand::Kind_FCCRegs);
1626 MipsAsmParser::OperandMatchResultTy
1627 MipsAsmParser::parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1628 return parseRegs(Operands, (int) MipsOperand::Kind_ACC64DSP);
1631 MipsAsmParser::OperandMatchResultTy
1632 MipsAsmParser::parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1633 // If the first token is not '$' we have an error.
1634 if (Parser.getTok().isNot(AsmToken::Dollar))
1635 return MatchOperand_NoMatch;
1637 SMLoc S = Parser.getTok().getLoc();
1638 Parser.Lex(); // Eat the '$'
1640 const AsmToken &Tok = Parser.getTok(); // Get next token.
1642 if (Tok.isNot(AsmToken::Identifier))
1643 return MatchOperand_NoMatch;
1645 if (!Tok.getIdentifier().startswith("ac"))
1646 return MatchOperand_NoMatch;
1648 StringRef NumString = Tok.getIdentifier().substr(2);
1651 if (NumString.getAsInteger(10, IntVal))
1652 return MatchOperand_NoMatch;
1654 unsigned Reg = matchRegisterByNumber(IntVal, Mips::LO32DSPRegClassID);
1656 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1657 Op->setRegKind(MipsOperand::Kind_LO32DSP);
1658 Operands.push_back(Op);
1660 Parser.Lex(); // Eat the register number.
1661 return MatchOperand_Success;
1664 MipsAsmParser::OperandMatchResultTy
1665 MipsAsmParser::parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1666 // If the first token is not '$' we have an error.
1667 if (Parser.getTok().isNot(AsmToken::Dollar))
1668 return MatchOperand_NoMatch;
1670 SMLoc S = Parser.getTok().getLoc();
1671 Parser.Lex(); // Eat the '$'
1673 const AsmToken &Tok = Parser.getTok(); // Get next token.
1675 if (Tok.isNot(AsmToken::Identifier))
1676 return MatchOperand_NoMatch;
1678 if (!Tok.getIdentifier().startswith("ac"))
1679 return MatchOperand_NoMatch;
1681 StringRef NumString = Tok.getIdentifier().substr(2);
1684 if (NumString.getAsInteger(10, IntVal))
1685 return MatchOperand_NoMatch;
1687 unsigned Reg = matchRegisterByNumber(IntVal, Mips::HI32DSPRegClassID);
1689 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1690 Op->setRegKind(MipsOperand::Kind_HI32DSP);
1691 Operands.push_back(Op);
1693 Parser.Lex(); // Eat the register number.
1694 return MatchOperand_Success;
1697 MipsAsmParser::OperandMatchResultTy
1698 MipsAsmParser::parseCOP2(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1699 // If the first token is not '$' we have an error.
1700 if (Parser.getTok().isNot(AsmToken::Dollar))
1701 return MatchOperand_NoMatch;
1703 SMLoc S = Parser.getTok().getLoc();
1704 Parser.Lex(); // Eat the '$'
1706 const AsmToken &Tok = Parser.getTok(); // Get next token.
1708 if (Tok.isNot(AsmToken::Integer))
1709 return MatchOperand_NoMatch;
1711 unsigned IntVal = Tok.getIntVal();
1713 unsigned Reg = matchRegisterByNumber(IntVal, Mips::COP2RegClassID);
1715 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1716 Op->setRegKind(MipsOperand::Kind_COP2);
1717 Operands.push_back(Op);
1719 Parser.Lex(); // Eat the register number.
1720 return MatchOperand_Success;
1723 MipsAsmParser::OperandMatchResultTy
1724 MipsAsmParser::parseMSA128BRegs(
1725 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1726 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128BRegs);
1729 MipsAsmParser::OperandMatchResultTy
1730 MipsAsmParser::parseMSA128HRegs(
1731 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1732 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128HRegs);
1735 MipsAsmParser::OperandMatchResultTy
1736 MipsAsmParser::parseMSA128WRegs(
1737 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1738 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128WRegs);
1741 MipsAsmParser::OperandMatchResultTy
1742 MipsAsmParser::parseMSA128DRegs(
1743 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1744 return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128DRegs);
1747 bool MipsAsmParser::searchSymbolAlias(
1748 SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {
1750 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1752 SMLoc S = Parser.getTok().getLoc();
1754 if (Sym->isVariable())
1755 Expr = Sym->getVariableValue();
1758 if (Expr->getKind() == MCExpr::SymbolRef) {
1759 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind) RegKind;
1760 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
1761 const StringRef DefSymbol = Ref->getSymbol().getName();
1762 if (DefSymbol.startswith("$")) {
1764 APInt IntVal(32, -1);
1765 if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
1766 RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
1768 ? Mips::GPR64RegClassID
1769 : Mips::GPR32RegClassID);
1771 // Lookup for the register with the corresponding name.
1773 case MipsOperand::Kind_AFGR64Regs:
1774 case MipsOperand::Kind_FGR64Regs:
1775 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1777 case MipsOperand::Kind_FGR32Regs:
1778 RegNum = matchFPURegisterName(DefSymbol.substr(1));
1780 case MipsOperand::Kind_GPR64:
1781 case MipsOperand::Kind_GPR32:
1783 RegNum = matchCPURegisterName(DefSymbol.substr(1));
1787 RegNum = getReg(regKindToRegClass(Kind), RegNum);
1791 MipsOperand *op = MipsOperand::CreateReg(RegNum, S,
1792 Parser.getTok().getLoc());
1793 op->setRegKind(Kind);
1794 Operands.push_back(op);
1798 } else if (Expr->getKind() == MCExpr::Constant) {
1800 const MCConstantExpr *Const = static_cast<const MCConstantExpr*>(Expr);
1801 MipsOperand *op = MipsOperand::CreateImm(Const, S,
1802 Parser.getTok().getLoc());
1803 Operands.push_back(op);
1810 MipsAsmParser::OperandMatchResultTy
1811 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1812 return parseRegs(Operands, (int) MipsOperand::Kind_HWRegs);
1815 MipsAsmParser::OperandMatchResultTy
1816 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1817 return parseRegs(Operands, (int) MipsOperand::Kind_CCRRegs);
1820 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1822 MCSymbolRefExpr::VariantKind VK
1823 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1824 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1825 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1826 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1827 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1828 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1829 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1830 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1831 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1832 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1833 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1834 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1835 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1836 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1837 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1838 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1839 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1840 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1841 .Default(MCSymbolRefExpr::VK_None);
1846 bool MipsAsmParser::
1847 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1848 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1849 // Check if we have valid mnemonic
1850 if (!mnemonicIsValid(Name, 0)) {
1851 Parser.eatToEndOfStatement();
1852 return Error(NameLoc, "Unknown instruction");
1854 // First operand in MCInst is instruction mnemonic.
1855 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
1857 // Read the remaining operands.
1858 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1859 // Read the first operand.
1860 if (ParseOperand(Operands, Name)) {
1861 SMLoc Loc = getLexer().getLoc();
1862 Parser.eatToEndOfStatement();
1863 return Error(Loc, "unexpected token in argument list");
1866 while (getLexer().is(AsmToken::Comma)) {
1867 Parser.Lex(); // Eat the comma.
1868 // Parse and remember the operand.
1869 if (ParseOperand(Operands, Name)) {
1870 SMLoc Loc = getLexer().getLoc();
1871 Parser.eatToEndOfStatement();
1872 return Error(Loc, "unexpected token in argument list");
1876 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1877 SMLoc Loc = getLexer().getLoc();
1878 Parser.eatToEndOfStatement();
1879 return Error(Loc, "unexpected token in argument list");
1881 Parser.Lex(); // Consume the EndOfStatement.
1885 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
1886 SMLoc Loc = getLexer().getLoc();
1887 Parser.eatToEndOfStatement();
1888 return Error(Loc, ErrorMsg);
1891 bool MipsAsmParser::parseSetNoAtDirective() {
1892 // Line should look like: ".set noat".
1894 Options.setATReg(0);
1897 // If this is not the end of the statement, report an error.
1898 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1899 reportParseError("unexpected token in statement");
1902 Parser.Lex(); // Consume the EndOfStatement.
1906 bool MipsAsmParser::parseSetAtDirective() {
1907 // Line can be .set at - defaults to $1
1911 if (getLexer().is(AsmToken::EndOfStatement)) {
1912 Options.setATReg(1);
1913 Parser.Lex(); // Consume the EndOfStatement.
1915 } else if (getLexer().is(AsmToken::Equal)) {
1916 getParser().Lex(); // Eat the '='.
1917 if (getLexer().isNot(AsmToken::Dollar)) {
1918 reportParseError("unexpected token in statement");
1921 Parser.Lex(); // Eat the '$'.
1922 const AsmToken &Reg = Parser.getTok();
1923 if (Reg.is(AsmToken::Identifier)) {
1924 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
1925 } else if (Reg.is(AsmToken::Integer)) {
1926 AtRegNo = Reg.getIntVal();
1928 reportParseError("unexpected token in statement");
1932 if (AtRegNo < 1 || AtRegNo > 31) {
1933 reportParseError("unexpected token in statement");
1937 if (!Options.setATReg(AtRegNo)) {
1938 reportParseError("unexpected token in statement");
1941 getParser().Lex(); // Eat the register.
1943 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1944 reportParseError("unexpected token in statement");
1947 Parser.Lex(); // Consume the EndOfStatement.
1950 reportParseError("unexpected token in statement");
1955 bool MipsAsmParser::parseSetReorderDirective() {
1957 // If this is not the end of the statement, report an error.
1958 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1959 reportParseError("unexpected token in statement");
1962 Options.setReorder();
1963 Parser.Lex(); // Consume the EndOfStatement.
1967 bool MipsAsmParser::parseSetNoReorderDirective() {
1969 // If this is not the end of the statement, report an error.
1970 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1971 reportParseError("unexpected token in statement");
1974 Options.setNoreorder();
1975 Parser.Lex(); // Consume the EndOfStatement.
1979 bool MipsAsmParser::parseSetMacroDirective() {
1981 // If this is not the end of the statement, report an error.
1982 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1983 reportParseError("unexpected token in statement");
1987 Parser.Lex(); // Consume the EndOfStatement.
1991 bool MipsAsmParser::parseSetNoMacroDirective() {
1993 // If this is not the end of the statement, report an error.
1994 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1995 reportParseError("`noreorder' must be set before `nomacro'");
1998 if (Options.isReorder()) {
1999 reportParseError("`noreorder' must be set before `nomacro'");
2002 Options.setNomacro();
2003 Parser.Lex(); // Consume the EndOfStatement.
2007 bool MipsAsmParser::parseSetAssignment() {
2009 const MCExpr *Value;
2011 if (Parser.parseIdentifier(Name))
2012 reportParseError("expected identifier after .set");
2014 if (getLexer().isNot(AsmToken::Comma))
2015 return reportParseError("unexpected token in .set directive");
2018 if (getLexer().is(AsmToken::Dollar)) {
2020 SMLoc DollarLoc = getLexer().getLoc();
2021 // Consume the dollar sign, and check for a following identifier.
2023 // We have a '$' followed by something, make sure they are adjacent.
2024 if (DollarLoc.getPointer() + 1 != getTok().getLoc().getPointer())
2026 StringRef Res = StringRef(DollarLoc.getPointer(),
2027 getTok().getEndLoc().getPointer() - DollarLoc.getPointer());
2028 Symbol = getContext().GetOrCreateSymbol(Res);
2030 Value = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
2032 } else if (Parser.parseExpression(Value))
2033 return reportParseError("expected valid expression after comma");
2035 // Check if the Name already exists as a symbol.
2036 MCSymbol *Sym = getContext().LookupSymbol(Name);
2038 return reportParseError("symbol already defined");
2039 Sym = getContext().GetOrCreateSymbol(Name);
2040 Sym->setVariableValue(Value);
2045 bool MipsAsmParser::parseDirectiveSet() {
2047 // Get the next token.
2048 const AsmToken &Tok = Parser.getTok();
2050 if (Tok.getString() == "noat") {
2051 return parseSetNoAtDirective();
2052 } else if (Tok.getString() == "at") {
2053 return parseSetAtDirective();
2054 } else if (Tok.getString() == "reorder") {
2055 return parseSetReorderDirective();
2056 } else if (Tok.getString() == "noreorder") {
2057 return parseSetNoReorderDirective();
2058 } else if (Tok.getString() == "macro") {
2059 return parseSetMacroDirective();
2060 } else if (Tok.getString() == "nomacro") {
2061 return parseSetNoMacroDirective();
2062 } else if (Tok.getString() == "nomips16") {
2063 // Ignore this directive for now.
2064 Parser.eatToEndOfStatement();
2066 } else if (Tok.getString() == "nomicromips") {
2067 // Ignore this directive for now.
2068 Parser.eatToEndOfStatement();
2071 // It is just an identifier, look for an assignment.
2072 parseSetAssignment();
2079 /// parseDirectiveWord
2080 /// ::= .word [ expression (, expression)* ]
2081 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
2082 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2084 const MCExpr *Value;
2085 if (getParser().parseExpression(Value))
2088 getParser().getStreamer().EmitValue(Value, Size);
2090 if (getLexer().is(AsmToken::EndOfStatement))
2093 // FIXME: Improve diagnostic.
2094 if (getLexer().isNot(AsmToken::Comma))
2095 return Error(L, "unexpected token in directive");
2104 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2106 StringRef IDVal = DirectiveID.getString();
2108 if (IDVal == ".ent") {
2109 // Ignore this directive for now.
2114 if (IDVal == ".end") {
2115 // Ignore this directive for now.
2120 if (IDVal == ".frame") {
2121 // Ignore this directive for now.
2122 Parser.eatToEndOfStatement();
2126 if (IDVal == ".set") {
2127 return parseDirectiveSet();
2130 if (IDVal == ".fmask") {
2131 // Ignore this directive for now.
2132 Parser.eatToEndOfStatement();
2136 if (IDVal == ".mask") {
2137 // Ignore this directive for now.
2138 Parser.eatToEndOfStatement();
2142 if (IDVal == ".gpword") {
2143 // Ignore this directive for now.
2144 Parser.eatToEndOfStatement();
2148 if (IDVal == ".word") {
2149 parseDirectiveWord(4, DirectiveID.getLoc());
2156 extern "C" void LLVMInitializeMipsAsmParser() {
2157 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2158 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2159 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2160 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2163 #define GET_REGISTER_MATCHER
2164 #define GET_MATCHER_IMPLEMENTATION
2165 #include "MipsGenAsmMatcher.inc"