1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCParser/MCAsmLexer.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/MC/MCTargetAsmParser.h"
22 #include "llvm/Support/TargetRegistry.h"
27 class MipsAssemblerOptions {
29 MipsAssemblerOptions():
30 aTReg(1), reorder(true), macro(true) {
33 unsigned getATRegNum() {return aTReg;}
34 bool setATReg(unsigned Reg);
36 bool isReorder() {return reorder;}
37 void setReorder() {reorder = true;}
38 void setNoreorder() {reorder = false;}
40 bool isMacro() {return macro;}
41 void setMacro() {macro = true;}
42 void setNomacro() {macro = false;}
52 class MipsAsmParser : public MCTargetAsmParser {
64 MipsAssemblerOptions Options;
67 #define GET_ASSEMBLER_HEADER
68 #include "MipsGenAsmMatcher.inc"
70 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
71 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
72 MCStreamer &Out, unsigned &ErrorInfo,
73 bool MatchingInlineAsm);
75 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
77 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
79 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
81 bool parseMathOperation(StringRef Name, SMLoc NameLoc,
82 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
84 bool ParseDirective(AsmToken DirectiveID);
86 MipsAsmParser::OperandMatchResultTy
87 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
89 MipsAsmParser::OperandMatchResultTy
90 parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
92 MipsAsmParser::OperandMatchResultTy
93 parseCPU64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
95 MipsAsmParser::OperandMatchResultTy
96 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
98 MipsAsmParser::OperandMatchResultTy
99 parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
101 MipsAsmParser::OperandMatchResultTy
102 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
104 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
107 int tryParseRegister(bool is64BitReg);
109 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
112 bool needsExpansion(MCInst &Inst);
114 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
115 SmallVectorImpl<MCInst> &Instructions);
116 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
117 SmallVectorImpl<MCInst> &Instructions);
118 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
119 SmallVectorImpl<MCInst> &Instructions);
120 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
121 SmallVectorImpl<MCInst> &Instructions);
122 bool reportParseError(StringRef ErrorMsg);
124 bool parseMemOffset(const MCExpr *&Res);
125 bool parseRelocOperand(const MCExpr *&Res);
127 bool parseDirectiveSet();
129 bool parseSetAtDirective();
130 bool parseSetNoAtDirective();
131 bool parseSetMacroDirective();
132 bool parseSetNoMacroDirective();
133 bool parseSetReorderDirective();
134 bool parseSetNoReorderDirective();
136 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
138 bool isMips64() const {
139 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
142 bool isFP64() const {
143 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
146 int matchRegisterName(StringRef Symbol, bool is64BitReg);
148 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
150 void setFpFormat(FpFormatTy Format) {
154 void setDefaultFpFormat();
156 void setFpFormat(StringRef Format);
158 FpFormatTy getFpFormat() {return FpFormat;}
160 bool requestsDoubleOperand(StringRef Mnemonic);
162 unsigned getReg(int RC,int RegNo);
166 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
167 : MCTargetAsmParser(), STI(sti), Parser(parser) {
168 // Initialize the set of available features.
169 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
172 MCAsmParser &getParser() const { return Parser; }
173 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
180 /// MipsOperand - Instances of this class represent a parsed Mips machine
182 class MipsOperand : public MCParsedAsmOperand {
208 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
231 SMLoc StartLoc, EndLoc;
234 void addRegOperands(MCInst &Inst, unsigned N) const {
235 assert(N == 1 && "Invalid number of operands!");
236 Inst.addOperand(MCOperand::CreateReg(getReg()));
239 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
240 // Add as immediate when possible. Null MCExpr = 0.
242 Inst.addOperand(MCOperand::CreateImm(0));
243 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
244 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
246 Inst.addOperand(MCOperand::CreateExpr(Expr));
249 void addImmOperands(MCInst &Inst, unsigned N) const {
250 assert(N == 1 && "Invalid number of operands!");
251 const MCExpr *Expr = getImm();
255 void addMemOperands(MCInst &Inst, unsigned N) const {
256 assert(N == 2 && "Invalid number of operands!");
258 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
260 const MCExpr *Expr = getMemOff();
264 bool isReg() const { return Kind == k_Register; }
265 bool isImm() const { return Kind == k_Immediate; }
266 bool isToken() const { return Kind == k_Token; }
267 bool isMem() const { return Kind == k_Memory; }
269 StringRef getToken() const {
270 assert(Kind == k_Token && "Invalid access!");
271 return StringRef(Tok.Data, Tok.Length);
274 unsigned getReg() const {
275 assert((Kind == k_Register) && "Invalid access!");
279 void setRegKind(RegisterKind RegKind) {
280 assert((Kind == k_Register) && "Invalid access!");
284 const MCExpr *getImm() const {
285 assert((Kind == k_Immediate) && "Invalid access!");
289 unsigned getMemBase() const {
290 assert((Kind == k_Memory) && "Invalid access!");
294 const MCExpr *getMemOff() const {
295 assert((Kind == k_Memory) && "Invalid access!");
299 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
300 MipsOperand *Op = new MipsOperand(k_Token);
301 Op->Tok.Data = Str.data();
302 Op->Tok.Length = Str.size();
308 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
309 MipsOperand *Op = new MipsOperand(k_Register);
310 Op->Reg.RegNum = RegNum;
316 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
317 MipsOperand *Op = new MipsOperand(k_Immediate);
324 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
326 MipsOperand *Op = new MipsOperand(k_Memory);
334 bool isCPURegsAsm() const {
335 return Kind == k_Register && Reg.Kind == Kind_CPURegs;
337 void addCPURegsAsmOperands(MCInst &Inst, unsigned N) const {
338 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
341 bool isCPU64RegsAsm() const {
342 return Kind == k_Register && Reg.Kind == Kind_CPU64Regs;
344 void addCPU64RegsAsmOperands(MCInst &Inst, unsigned N) const {
345 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
348 bool isHWRegsAsm() const {
349 assert((Kind == k_Register) && "Invalid access!");
350 return Reg.Kind == Kind_HWRegs;
352 void addHWRegsAsmOperands(MCInst &Inst, unsigned N) const {
353 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
356 bool isHW64RegsAsm() const {
357 assert((Kind == k_Register) && "Invalid access!");
358 return Reg.Kind == Kind_HW64Regs;
360 void addHW64RegsAsmOperands(MCInst &Inst, unsigned N) const {
361 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
364 void addCCRAsmOperands(MCInst &Inst, unsigned N) const {
365 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
368 bool isCCRAsm() const {
369 assert((Kind == k_Register) && "Invalid access!");
370 return Reg.Kind == Kind_CCRRegs;
373 /// getStartLoc - Get the location of the first token of this operand.
374 SMLoc getStartLoc() const { return StartLoc; }
375 /// getEndLoc - Get the location of the last token of this operand.
376 SMLoc getEndLoc() const { return EndLoc; }
378 virtual void print(raw_ostream &OS) const {
379 llvm_unreachable("unimplemented!");
384 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
386 switch(Inst.getOpcode()) {
387 case Mips::LoadImm32Reg:
388 case Mips::LoadAddr32Imm:
389 case Mips::LoadAddr32Reg:
396 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
397 SmallVectorImpl<MCInst> &Instructions){
398 switch(Inst.getOpcode()) {
399 case Mips::LoadImm32Reg:
400 return expandLoadImm(Inst, IDLoc, Instructions);
401 case Mips::LoadAddr32Imm:
402 return expandLoadAddressImm(Inst,IDLoc,Instructions);
403 case Mips::LoadAddr32Reg:
404 return expandLoadAddressReg(Inst,IDLoc,Instructions);
408 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
409 SmallVectorImpl<MCInst> &Instructions){
411 const MCOperand &ImmOp = Inst.getOperand(1);
412 assert(ImmOp.isImm() && "expected immediate operand kind");
413 const MCOperand &RegOp = Inst.getOperand(0);
414 assert(RegOp.isReg() && "expected register operand kind");
416 int ImmValue = ImmOp.getImm();
417 tmpInst.setLoc(IDLoc);
418 if ( 0 <= ImmValue && ImmValue <= 65535) {
419 // for 0 <= j <= 65535.
420 // li d,j => ori d,$zero,j
421 tmpInst.setOpcode(Mips::ORi);
422 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
424 MCOperand::CreateReg(Mips::ZERO));
425 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
426 Instructions.push_back(tmpInst);
427 } else if ( ImmValue < 0 && ImmValue >= -32768) {
428 // for -32768 <= j < 0.
429 // li d,j => addiu d,$zero,j
430 tmpInst.setOpcode(Mips::ADDiu);
431 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
433 MCOperand::CreateReg(Mips::ZERO));
434 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
435 Instructions.push_back(tmpInst);
437 // for any other value of j that is representable as a 32-bit integer.
438 // li d,j => lui d,hi16(j)
440 tmpInst.setOpcode(Mips::LUi);
441 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
442 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
443 Instructions.push_back(tmpInst);
445 tmpInst.setOpcode(Mips::ORi);
446 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
447 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
448 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
449 tmpInst.setLoc(IDLoc);
450 Instructions.push_back(tmpInst);
454 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
455 SmallVectorImpl<MCInst> &Instructions){
457 const MCOperand &ImmOp = Inst.getOperand(2);
458 assert(ImmOp.isImm() && "expected immediate operand kind");
459 const MCOperand &SrcRegOp = Inst.getOperand(1);
460 assert(SrcRegOp.isReg() && "expected register operand kind");
461 const MCOperand &DstRegOp = Inst.getOperand(0);
462 assert(DstRegOp.isReg() && "expected register operand kind");
463 int ImmValue = ImmOp.getImm();
464 if ( -32768 <= ImmValue && ImmValue <= 65535) {
465 //for -32768 <= j <= 65535.
466 //la d,j(s) => addiu d,s,j
467 tmpInst.setOpcode(Mips::ADDiu);
468 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
469 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
470 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
471 Instructions.push_back(tmpInst);
473 //for any other value of j that is representable as a 32-bit integer.
474 //la d,j(s) => lui d,hi16(j)
477 tmpInst.setOpcode(Mips::LUi);
478 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
479 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
480 Instructions.push_back(tmpInst);
482 tmpInst.setOpcode(Mips::ORi);
483 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
484 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
485 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
486 Instructions.push_back(tmpInst);
488 tmpInst.setOpcode(Mips::ADDu);
489 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
490 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
491 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
492 Instructions.push_back(tmpInst);
496 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
497 SmallVectorImpl<MCInst> &Instructions){
499 const MCOperand &ImmOp = Inst.getOperand(1);
500 assert(ImmOp.isImm() && "expected immediate operand kind");
501 const MCOperand &RegOp = Inst.getOperand(0);
502 assert(RegOp.isReg() && "expected register operand kind");
503 int ImmValue = ImmOp.getImm();
504 if ( -32768 <= ImmValue && ImmValue <= 65535) {
505 //for -32768 <= j <= 65535.
506 //la d,j => addiu d,$zero,j
507 tmpInst.setOpcode(Mips::ADDiu);
508 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
510 MCOperand::CreateReg(Mips::ZERO));
511 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
512 Instructions.push_back(tmpInst);
514 //for any other value of j that is representable as a 32-bit integer.
515 //la d,j => lui d,hi16(j)
517 tmpInst.setOpcode(Mips::LUi);
518 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
519 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
520 Instructions.push_back(tmpInst);
522 tmpInst.setOpcode(Mips::ORi);
523 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
524 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
525 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
526 Instructions.push_back(tmpInst);
531 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
532 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
533 MCStreamer &Out, unsigned &ErrorInfo,
534 bool MatchingInlineAsm) {
536 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
539 switch (MatchResult) {
541 case Match_Success: {
542 if (needsExpansion(Inst)) {
543 SmallVector<MCInst, 4> Instructions;
544 expandInstruction(Inst, IDLoc, Instructions);
545 for(unsigned i =0; i < Instructions.size(); i++){
546 Out.EmitInstruction(Instructions[i]);
550 Out.EmitInstruction(Inst);
554 case Match_MissingFeature:
555 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
557 case Match_InvalidOperand: {
558 SMLoc ErrorLoc = IDLoc;
559 if (ErrorInfo != ~0U) {
560 if (ErrorInfo >= Operands.size())
561 return Error(IDLoc, "too few operands for instruction");
563 ErrorLoc = ((MipsOperand*)Operands[ErrorInfo])->getStartLoc();
564 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
567 return Error(ErrorLoc, "invalid operand for instruction");
569 case Match_MnemonicFail:
570 return Error(IDLoc, "invalid instruction");
575 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
579 CC = StringSwitch<unsigned>(Name)
580 .Case("zero", Mips::ZERO)
581 .Case("a0", Mips::A0)
582 .Case("a1", Mips::A1)
583 .Case("a2", Mips::A2)
584 .Case("a3", Mips::A3)
585 .Case("v0", Mips::V0)
586 .Case("v1", Mips::V1)
587 .Case("s0", Mips::S0)
588 .Case("s1", Mips::S1)
589 .Case("s2", Mips::S2)
590 .Case("s3", Mips::S3)
591 .Case("s4", Mips::S4)
592 .Case("s5", Mips::S5)
593 .Case("s6", Mips::S6)
594 .Case("s7", Mips::S7)
595 .Case("k0", Mips::K0)
596 .Case("k1", Mips::K1)
597 .Case("sp", Mips::SP)
598 .Case("fp", Mips::FP)
599 .Case("gp", Mips::GP)
600 .Case("ra", Mips::RA)
601 .Case("t0", Mips::T0)
602 .Case("t1", Mips::T1)
603 .Case("t2", Mips::T2)
604 .Case("t3", Mips::T3)
605 .Case("t4", Mips::T4)
606 .Case("t5", Mips::T5)
607 .Case("t6", Mips::T6)
608 .Case("t7", Mips::T7)
609 .Case("t8", Mips::T8)
610 .Case("t9", Mips::T9)
611 .Case("at", Mips::AT)
612 .Case("fcc0", Mips::FCC0)
615 CC = StringSwitch<unsigned>(Name)
616 .Case("zero", Mips::ZERO_64)
617 .Case("at", Mips::AT_64)
618 .Case("v0", Mips::V0_64)
619 .Case("v1", Mips::V1_64)
620 .Case("a0", Mips::A0_64)
621 .Case("a1", Mips::A1_64)
622 .Case("a2", Mips::A2_64)
623 .Case("a3", Mips::A3_64)
624 .Case("a4", Mips::T0_64)
625 .Case("a5", Mips::T1_64)
626 .Case("a6", Mips::T2_64)
627 .Case("a7", Mips::T3_64)
628 .Case("t4", Mips::T4_64)
629 .Case("t5", Mips::T5_64)
630 .Case("t6", Mips::T6_64)
631 .Case("t7", Mips::T7_64)
632 .Case("s0", Mips::S0_64)
633 .Case("s1", Mips::S1_64)
634 .Case("s2", Mips::S2_64)
635 .Case("s3", Mips::S3_64)
636 .Case("s4", Mips::S4_64)
637 .Case("s5", Mips::S5_64)
638 .Case("s6", Mips::S6_64)
639 .Case("s7", Mips::S7_64)
640 .Case("t8", Mips::T8_64)
641 .Case("t9", Mips::T9_64)
642 .Case("kt0", Mips::K0_64)
643 .Case("kt1", Mips::K1_64)
644 .Case("gp", Mips::GP_64)
645 .Case("sp", Mips::SP_64)
646 .Case("fp", Mips::FP_64)
647 .Case("s8", Mips::FP_64)
648 .Case("ra", Mips::RA_64)
654 if (Name[0] == 'f') {
655 StringRef NumString = Name.substr(1);
657 if( NumString.getAsInteger(10, IntVal))
658 return -1; // not integer
662 FpFormatTy Format = getFpFormat();
664 if (Format == FP_FORMAT_S || Format == FP_FORMAT_W)
665 return getReg(Mips::FGR32RegClassID, IntVal);
666 if (Format == FP_FORMAT_D) {
668 return getReg(Mips::FGR64RegClassID, IntVal);
670 // only even numbers available as register pairs
671 if (( IntVal > 31) || (IntVal%2 != 0))
673 return getReg(Mips::AFGR64RegClassID, IntVal/2);
679 void MipsAsmParser::setDefaultFpFormat() {
681 if (isMips64() || isFP64())
682 FpFormat = FP_FORMAT_D;
684 FpFormat = FP_FORMAT_S;
687 bool MipsAsmParser::requestsDoubleOperand(StringRef Mnemonic){
689 bool IsDouble = StringSwitch<bool>(Mnemonic.lower())
698 void MipsAsmParser::setFpFormat(StringRef Format) {
700 FpFormat = StringSwitch<FpFormatTy>(Format.lower())
701 .Case(".s", FP_FORMAT_S)
702 .Case(".d", FP_FORMAT_D)
703 .Case(".l", FP_FORMAT_L)
704 .Case(".w", FP_FORMAT_W)
705 .Default(FP_FORMAT_NONE);
708 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
716 unsigned MipsAsmParser::getATReg() {
717 unsigned Reg = Options.getATRegNum();
719 return getReg(Mips::CPU64RegsRegClassID,Reg);
721 return getReg(Mips::CPURegsRegClassID,Reg);
724 unsigned MipsAsmParser::getReg(int RC,int RegNo) {
725 return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
728 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
733 return getReg(RegClass, RegNum);
736 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
737 const AsmToken &Tok = Parser.getTok();
740 if (Tok.is(AsmToken::Identifier)) {
741 std::string lowerCase = Tok.getString().lower();
742 RegNum = matchRegisterName(lowerCase, is64BitReg);
743 } else if (Tok.is(AsmToken::Integer))
744 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
745 is64BitReg ? Mips::CPU64RegsRegClassID
746 : Mips::CPURegsRegClassID);
751 tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
754 SMLoc S = Parser.getTok().getLoc();
757 RegNo = tryParseRegister(is64BitReg);
761 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
762 Parser.getTok().getLoc()));
763 Parser.Lex(); // Eat register token.
767 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
768 StringRef Mnemonic) {
769 // Check if the current operand has a custom associated parser, if so, try to
770 // custom parse the operand, or fallback to the general approach.
771 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
772 if (ResTy == MatchOperand_Success)
774 // If there wasn't a custom match, try the generic matcher below. Otherwise,
775 // there was a match, but an error occurred, in which case, just return that
776 // the operand parsing failed.
777 if (ResTy == MatchOperand_ParseFail)
780 switch (getLexer().getKind()) {
782 Error(Parser.getTok().getLoc(), "unexpected token in operand");
784 case AsmToken::Dollar: {
786 SMLoc S = Parser.getTok().getLoc();
787 Parser.Lex(); // Eat dollar token.
788 // parse register operand
789 if (!tryParseRegisterOperand(Operands, isMips64())) {
790 if (getLexer().is(AsmToken::LParen)) {
791 // check if it is indexed addressing operand
792 Operands.push_back(MipsOperand::CreateToken("(", S));
793 Parser.Lex(); // eat parenthesis
794 if (getLexer().isNot(AsmToken::Dollar))
797 Parser.Lex(); // eat dollar
798 if (tryParseRegisterOperand(Operands, isMips64()))
801 if (!getLexer().is(AsmToken::RParen))
804 S = Parser.getTok().getLoc();
805 Operands.push_back(MipsOperand::CreateToken(")", S));
810 // maybe it is a symbol reference
811 StringRef Identifier;
812 if (Parser.ParseIdentifier(Identifier))
815 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
817 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
819 // Otherwise create a symbol ref.
820 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
823 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
826 case AsmToken::Identifier:
827 case AsmToken::LParen:
828 case AsmToken::Minus:
830 case AsmToken::Integer:
831 case AsmToken::String: {
832 // quoted label names
834 SMLoc S = Parser.getTok().getLoc();
835 if (getParser().ParseExpression(IdVal))
837 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
838 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
841 case AsmToken::Percent: {
842 // it is a symbol reference or constant expression
844 SMLoc S = Parser.getTok().getLoc(); // start location of the operand
845 if (parseRelocOperand(IdVal))
848 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
850 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
852 } // case AsmToken::Percent
853 } // switch(getLexer().getKind())
857 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
859 Parser.Lex(); // eat % token
860 const AsmToken &Tok = Parser.getTok(); // get next token, operation
861 if (Tok.isNot(AsmToken::Identifier))
864 std::string Str = Tok.getIdentifier().str();
866 Parser.Lex(); // eat identifier
867 // now make expression from the rest of the operand
871 if (getLexer().getKind() == AsmToken::LParen) {
873 Parser.Lex(); // eat '(' token
874 if (getLexer().getKind() == AsmToken::Percent) {
875 Parser.Lex(); // eat % token
876 const AsmToken &nextTok = Parser.getTok();
877 if (nextTok.isNot(AsmToken::Identifier))
880 Str += nextTok.getIdentifier();
881 Parser.Lex(); // eat identifier
882 if (getLexer().getKind() != AsmToken::LParen)
887 if (getParser().ParseParenExpression(IdVal,EndLoc))
890 while (getLexer().getKind() == AsmToken::RParen)
891 Parser.Lex(); // eat ')' token
894 return true; // parenthesis must follow reloc operand
896 // Check the type of the expression
897 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal)) {
898 // it's a constant, evaluate lo or hi value
899 int Val = MCE->getValue();
902 } else if (Str == "hi") {
903 Val = (Val & 0xffff0000) >> 16;
905 Res = MCConstantExpr::Create(Val, getContext());
909 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(IdVal)) {
910 // it's a symbol, create symbolic expression from symbol
911 StringRef Symbol = MSRE->getSymbol().getName();
912 MCSymbolRefExpr::VariantKind VK = getVariantKind(Str);
913 Res = MCSymbolRefExpr::Create(Symbol,VK,getContext());
919 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
922 StartLoc = Parser.getTok().getLoc();
923 RegNo = tryParseRegister(isMips64());
924 EndLoc = Parser.getTok().getLoc();
925 return (RegNo == (unsigned)-1);
928 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res) {
932 switch(getLexer().getKind()) {
935 case AsmToken::Integer:
936 case AsmToken::Minus:
938 return (getParser().ParseExpression(Res));
939 case AsmToken::Percent:
940 return parseRelocOperand(Res);
941 case AsmToken::LParen:
942 return false; // it's probably assuming 0
947 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
948 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
950 const MCExpr *IdVal = 0;
952 // first operand is the offset
953 S = Parser.getTok().getLoc();
955 if (parseMemOffset(IdVal))
956 return MatchOperand_ParseFail;
958 const AsmToken &Tok = Parser.getTok(); // get next token
959 if (Tok.isNot(AsmToken::LParen)) {
960 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
961 if (Mnemonic->getToken() == "la") {
962 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() -1);
963 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
964 return MatchOperand_Success;
966 Error(Parser.getTok().getLoc(), "'(' expected");
967 return MatchOperand_ParseFail;
970 Parser.Lex(); // Eat '(' token.
972 const AsmToken &Tok1 = Parser.getTok(); // get next token
973 if (Tok1.is(AsmToken::Dollar)) {
974 Parser.Lex(); // Eat '$' token.
975 if (tryParseRegisterOperand(Operands, isMips64())) {
976 Error(Parser.getTok().getLoc(), "unexpected token in operand");
977 return MatchOperand_ParseFail;
981 Error(Parser.getTok().getLoc(), "unexpected token in operand");
982 return MatchOperand_ParseFail;
985 const AsmToken &Tok2 = Parser.getTok(); // get next token
986 if (Tok2.isNot(AsmToken::RParen)) {
987 Error(Parser.getTok().getLoc(), "')' expected");
988 return MatchOperand_ParseFail;
991 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
993 Parser.Lex(); // Eat ')' token.
996 IdVal = MCConstantExpr::Create(0, getContext());
998 // now replace register operand with the mem operand
999 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1000 int RegNo = op->getReg();
1001 // remove register from operands
1002 Operands.pop_back();
1003 // and add memory operand
1004 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1006 return MatchOperand_Success;
1009 MipsAsmParser::OperandMatchResultTy
1010 MipsAsmParser::parseCPU64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1013 return MatchOperand_NoMatch;
1014 // if the first token is not '$' we have an error
1015 if (Parser.getTok().isNot(AsmToken::Dollar))
1016 return MatchOperand_NoMatch;
1018 Parser.Lex(); // Eat $
1019 if(!tryParseRegisterOperand(Operands, true)) {
1020 // set the proper register kind
1021 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1022 op->setRegKind(MipsOperand::Kind_CPU64Regs);
1023 return MatchOperand_Success;
1025 return MatchOperand_NoMatch;
1028 MipsAsmParser::OperandMatchResultTy
1029 MipsAsmParser::parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1031 // if the first token is not '$' we have an error
1032 if (Parser.getTok().isNot(AsmToken::Dollar))
1033 return MatchOperand_NoMatch;
1035 Parser.Lex(); // Eat $
1036 if(!tryParseRegisterOperand(Operands, false)) {
1037 // set the propper register kind
1038 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1039 op->setRegKind(MipsOperand::Kind_CPURegs);
1040 return MatchOperand_Success;
1042 return MatchOperand_NoMatch;
1045 MipsAsmParser::OperandMatchResultTy
1046 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1048 // if the first token is not '$' we have error
1049 if (Parser.getTok().isNot(AsmToken::Dollar))
1050 return MatchOperand_NoMatch;
1051 SMLoc S = Parser.getTok().getLoc();
1052 Parser.Lex(); // Eat $
1054 const AsmToken &Tok = Parser.getTok(); // get next token
1055 if (Tok.isNot(AsmToken::Integer))
1056 return MatchOperand_NoMatch;
1058 unsigned RegNum = Tok.getIntVal();
1059 // at the moment only hwreg29 is supported
1061 return MatchOperand_ParseFail;
1063 MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29, S,
1064 Parser.getTok().getLoc());
1065 op->setRegKind(MipsOperand::Kind_HWRegs);
1066 Operands.push_back(op);
1068 Parser.Lex(); // Eat reg number
1069 return MatchOperand_Success;
1072 MipsAsmParser::OperandMatchResultTy
1073 MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1074 //if the first token is not '$' we have error
1075 if (Parser.getTok().isNot(AsmToken::Dollar))
1076 return MatchOperand_NoMatch;
1077 SMLoc S = Parser.getTok().getLoc();
1078 Parser.Lex(); // Eat $
1080 const AsmToken &Tok = Parser.getTok(); // get next token
1081 if (Tok.isNot(AsmToken::Integer))
1082 return MatchOperand_NoMatch;
1084 unsigned RegNum = Tok.getIntVal();
1085 // at the moment only hwreg29 is supported
1087 return MatchOperand_ParseFail;
1089 MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
1090 Parser.getTok().getLoc());
1091 op->setRegKind(MipsOperand::Kind_HWRegs);
1092 Operands.push_back(op);
1094 Parser.Lex(); // Eat reg number
1095 return MatchOperand_Success;
1098 MipsAsmParser::OperandMatchResultTy
1099 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1101 //if the first token is not '$' we have error
1102 if (Parser.getTok().isNot(AsmToken::Dollar))
1103 return MatchOperand_NoMatch;
1104 SMLoc S = Parser.getTok().getLoc();
1105 Parser.Lex(); // Eat $
1107 const AsmToken &Tok = Parser.getTok(); // get next token
1108 if (Tok.is(AsmToken::Integer)) {
1109 RegNum = Tok.getIntVal();
1110 // at the moment only fcc0 is supported
1112 return MatchOperand_ParseFail;
1113 } else if (Tok.is(AsmToken::Identifier)) {
1114 // at the moment only fcc0 is supported
1115 if (Tok.getIdentifier() != "fcc0")
1116 return MatchOperand_ParseFail;
1118 return MatchOperand_NoMatch;
1120 MipsOperand *op = MipsOperand::CreateReg(Mips::FCC0, S,
1121 Parser.getTok().getLoc());
1122 op->setRegKind(MipsOperand::Kind_CCRRegs);
1123 Operands.push_back(op);
1125 Parser.Lex(); // Eat reg number
1126 return MatchOperand_Success;
1129 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1131 MCSymbolRefExpr::VariantKind VK
1132 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1133 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1134 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1135 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1136 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1137 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1138 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1139 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1140 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1141 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1142 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1143 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1144 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1145 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1146 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1147 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1148 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1149 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1150 .Default(MCSymbolRefExpr::VK_None);
1155 static int ConvertCcString(StringRef CondString) {
1156 int CC = StringSwitch<unsigned>(CondString)
1178 bool MipsAsmParser::
1179 parseMathOperation(StringRef Name, SMLoc NameLoc,
1180 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1182 size_t Start = Name.find('.'), Next = Name.rfind('.');
1183 StringRef Format1 = Name.slice(Start, Next);
1184 // and add the first format to the operands
1185 Operands.push_back(MipsOperand::CreateToken(Format1, NameLoc));
1186 // now for the second format
1187 StringRef Format2 = Name.slice(Next, StringRef::npos);
1188 Operands.push_back(MipsOperand::CreateToken(Format2, NameLoc));
1190 // set the format for the first register
1191 setFpFormat(Format1);
1193 // Read the remaining operands.
1194 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1195 // Read the first operand.
1196 if (ParseOperand(Operands, Name)) {
1197 SMLoc Loc = getLexer().getLoc();
1198 Parser.EatToEndOfStatement();
1199 return Error(Loc, "unexpected token in argument list");
1202 if (getLexer().isNot(AsmToken::Comma)) {
1203 SMLoc Loc = getLexer().getLoc();
1204 Parser.EatToEndOfStatement();
1205 return Error(Loc, "unexpected token in argument list");
1208 Parser.Lex(); // Eat the comma.
1210 //set the format for the first register
1211 setFpFormat(Format2);
1213 // Parse and remember the operand.
1214 if (ParseOperand(Operands, Name)) {
1215 SMLoc Loc = getLexer().getLoc();
1216 Parser.EatToEndOfStatement();
1217 return Error(Loc, "unexpected token in argument list");
1221 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1222 SMLoc Loc = getLexer().getLoc();
1223 Parser.EatToEndOfStatement();
1224 return Error(Loc, "unexpected token in argument list");
1227 Parser.Lex(); // Consume the EndOfStatement
1231 bool MipsAsmParser::
1232 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1233 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1234 // floating point instructions: should register be treated as double?
1235 if (requestsDoubleOperand(Name)) {
1236 setFpFormat(FP_FORMAT_D);
1237 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
1240 setDefaultFpFormat();
1241 // Create the leading tokens for the mnemonic, split by '.' characters.
1242 size_t Start = 0, Next = Name.find('.');
1243 StringRef Mnemonic = Name.slice(Start, Next);
1245 Operands.push_back(MipsOperand::CreateToken(Mnemonic, NameLoc));
1247 if (Next != StringRef::npos) {
1248 // there is a format token in mnemonic
1249 // StringRef Rest = Name.slice(Next, StringRef::npos);
1250 size_t Dot = Name.find('.', Next+1);
1251 StringRef Format = Name.slice(Next, Dot);
1252 if (Dot == StringRef::npos) //only one '.' in a string, it's a format
1253 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1255 if (Name.startswith("c.")){
1256 // floating point compare, add '.' and immediate represent for cc
1257 Operands.push_back(MipsOperand::CreateToken(".", NameLoc));
1258 int Cc = ConvertCcString(Format);
1260 return Error(NameLoc, "Invalid conditional code");
1262 SMLoc E = SMLoc::getFromPointer(
1263 Parser.getTok().getLoc().getPointer() -1 );
1264 Operands.push_back(MipsOperand::CreateImm(
1265 MCConstantExpr::Create(Cc, getContext()), NameLoc, E));
1267 // trunc, ceil, floor ...
1268 return parseMathOperation(Name, NameLoc, Operands);
1271 // the rest is a format
1272 Format = Name.slice(Dot, StringRef::npos);
1273 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1276 setFpFormat(Format);
1280 // Read the remaining operands.
1281 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1282 // Read the first operand.
1283 if (ParseOperand(Operands, Name)) {
1284 SMLoc Loc = getLexer().getLoc();
1285 Parser.EatToEndOfStatement();
1286 return Error(Loc, "unexpected token in argument list");
1289 while (getLexer().is(AsmToken::Comma) ) {
1290 Parser.Lex(); // Eat the comma.
1292 // Parse and remember the operand.
1293 if (ParseOperand(Operands, Name)) {
1294 SMLoc Loc = getLexer().getLoc();
1295 Parser.EatToEndOfStatement();
1296 return Error(Loc, "unexpected token in argument list");
1301 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1302 SMLoc Loc = getLexer().getLoc();
1303 Parser.EatToEndOfStatement();
1304 return Error(Loc, "unexpected token in argument list");
1307 Parser.Lex(); // Consume the EndOfStatement
1311 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
1312 SMLoc Loc = getLexer().getLoc();
1313 Parser.EatToEndOfStatement();
1314 return Error(Loc, ErrorMsg);
1317 bool MipsAsmParser::parseSetNoAtDirective() {
1318 // line should look like:
1321 Options.setATReg(0);
1324 // if this is not the end of the statement, report error
1325 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1326 reportParseError("unexpected token in statement");
1329 Parser.Lex(); // Consume the EndOfStatement
1332 bool MipsAsmParser::parseSetAtDirective() {
1334 // .set at - defaults to $1
1337 if (getLexer().is(AsmToken::EndOfStatement)) {
1338 Options.setATReg(1);
1339 Parser.Lex(); // Consume the EndOfStatement
1341 } else if (getLexer().is(AsmToken::Equal)) {
1342 getParser().Lex(); //eat '='
1343 if (getLexer().isNot(AsmToken::Dollar)) {
1344 reportParseError("unexpected token in statement");
1347 Parser.Lex(); // eat '$'
1348 if (getLexer().isNot(AsmToken::Integer)) {
1349 reportParseError("unexpected token in statement");
1352 const AsmToken &Reg = Parser.getTok();
1353 if (!Options.setATReg(Reg.getIntVal())) {
1354 reportParseError("unexpected token in statement");
1357 getParser().Lex(); //eat reg
1359 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1360 reportParseError("unexpected token in statement");
1363 Parser.Lex(); // Consume the EndOfStatement
1366 reportParseError("unexpected token in statement");
1371 bool MipsAsmParser::parseSetReorderDirective() {
1373 // if this is not the end of the statement, report error
1374 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1375 reportParseError("unexpected token in statement");
1378 Options.setReorder();
1379 Parser.Lex(); // Consume the EndOfStatement
1383 bool MipsAsmParser::parseSetNoReorderDirective() {
1385 // if this is not the end of the statement, report error
1386 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1387 reportParseError("unexpected token in statement");
1390 Options.setNoreorder();
1391 Parser.Lex(); // Consume the EndOfStatement
1395 bool MipsAsmParser::parseSetMacroDirective() {
1397 // if this is not the end of the statement, report error
1398 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1399 reportParseError("unexpected token in statement");
1403 Parser.Lex(); // Consume the EndOfStatement
1407 bool MipsAsmParser::parseSetNoMacroDirective() {
1409 // if this is not the end of the statement, report error
1410 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1411 reportParseError("`noreorder' must be set before `nomacro'");
1414 if (Options.isReorder()) {
1415 reportParseError("`noreorder' must be set before `nomacro'");
1418 Options.setNomacro();
1419 Parser.Lex(); // Consume the EndOfStatement
1422 bool MipsAsmParser::parseDirectiveSet() {
1425 const AsmToken &Tok = Parser.getTok();
1427 if (Tok.getString() == "noat") {
1428 return parseSetNoAtDirective();
1429 } else if (Tok.getString() == "at") {
1430 return parseSetAtDirective();
1431 } else if (Tok.getString() == "reorder") {
1432 return parseSetReorderDirective();
1433 } else if (Tok.getString() == "noreorder") {
1434 return parseSetNoReorderDirective();
1435 } else if (Tok.getString() == "macro") {
1436 return parseSetMacroDirective();
1437 } else if (Tok.getString() == "nomacro") {
1438 return parseSetNoMacroDirective();
1439 } else if (Tok.getString() == "nomips16") {
1440 // ignore this directive for now
1441 Parser.EatToEndOfStatement();
1443 } else if (Tok.getString() == "nomicromips") {
1444 // ignore this directive for now
1445 Parser.EatToEndOfStatement();
1451 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
1453 if (DirectiveID.getString() == ".ent") {
1454 // ignore this directive for now
1459 if (DirectiveID.getString() == ".end") {
1460 // ignore this directive for now
1465 if (DirectiveID.getString() == ".frame") {
1466 // ignore this directive for now
1467 Parser.EatToEndOfStatement();
1471 if (DirectiveID.getString() == ".set") {
1472 return parseDirectiveSet();
1475 if (DirectiveID.getString() == ".fmask") {
1476 // ignore this directive for now
1477 Parser.EatToEndOfStatement();
1481 if (DirectiveID.getString() == ".mask") {
1482 // ignore this directive for now
1483 Parser.EatToEndOfStatement();
1487 if (DirectiveID.getString() == ".gpword") {
1488 // ignore this directive for now
1489 Parser.EatToEndOfStatement();
1496 extern "C" void LLVMInitializeMipsAsmParser() {
1497 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
1498 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
1499 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
1500 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
1503 #define GET_REGISTER_MATCHER
1504 #define GET_MATCHER_IMPLEMENTATION
1505 #include "MipsGenAsmMatcher.inc"