1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCExpr.h"
11 #include "MCTargetDesc/MipsMCTargetDesc.h"
12 #include "MipsRegisterInfo.h"
13 #include "MipsTargetStreamer.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstBuilder.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/TargetRegistry.h"
32 #define DEBUG_TYPE "mips-asm-parser"
39 class MipsAssemblerOptions {
41 MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {}
43 unsigned getATRegNum() { return aTReg; }
44 bool setATReg(unsigned Reg);
46 bool isReorder() { return reorder; }
47 void setReorder() { reorder = true; }
48 void setNoreorder() { reorder = false; }
50 bool isMacro() { return macro; }
51 void setMacro() { macro = true; }
52 void setNomacro() { macro = false; }
62 class MipsAsmParser : public MCTargetAsmParser {
63 MipsTargetStreamer &getTargetStreamer() {
64 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
65 return static_cast<MipsTargetStreamer &>(TS);
70 MipsAssemblerOptions Options;
72 #define GET_ASSEMBLER_HEADER
73 #include "MipsGenAsmMatcher.inc"
75 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
77 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
78 OperandVector &Operands, MCStreamer &Out,
80 bool MatchingInlineAsm) override;
82 /// Parse a register as used in CFI directives
83 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
85 bool ParseParenSuffix(StringRef Name, OperandVector &Operands);
87 bool ParseBracketSuffix(StringRef Name, OperandVector &Operands);
89 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
90 SMLoc NameLoc, OperandVector &Operands) override;
92 bool ParseDirective(AsmToken DirectiveID) override;
94 MipsAsmParser::OperandMatchResultTy parseMemOperand(OperandVector &Operands);
96 MipsAsmParser::OperandMatchResultTy
97 MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
98 StringRef Identifier, SMLoc S);
100 MipsAsmParser::OperandMatchResultTy
101 MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S);
103 MipsAsmParser::OperandMatchResultTy ParseAnyRegister(OperandVector &Operands);
105 MipsAsmParser::OperandMatchResultTy ParseImm(OperandVector &Operands);
107 MipsAsmParser::OperandMatchResultTy ParseJumpTarget(OperandVector &Operands);
109 MipsAsmParser::OperandMatchResultTy parseInvNum(OperandVector &Operands);
111 MipsAsmParser::OperandMatchResultTy ParseLSAImm(OperandVector &Operands);
113 bool searchSymbolAlias(OperandVector &Operands);
115 bool ParseOperand(OperandVector &, StringRef Mnemonic);
117 bool needsExpansion(MCInst &Inst);
119 // Expands assembly pseudo instructions.
120 // Returns false on success, true otherwise.
121 bool expandInstruction(MCInst &Inst, SMLoc IDLoc,
122 SmallVectorImpl<MCInst> &Instructions);
124 bool expandLoadImm(MCInst &Inst, SMLoc IDLoc,
125 SmallVectorImpl<MCInst> &Instructions);
127 bool expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
128 SmallVectorImpl<MCInst> &Instructions);
130 bool expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
131 SmallVectorImpl<MCInst> &Instructions);
133 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
134 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
136 bool reportParseError(Twine ErrorMsg);
137 bool reportParseError(SMLoc Loc, Twine ErrorMsg);
139 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
140 bool parseRelocOperand(const MCExpr *&Res);
142 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
144 bool isEvaluated(const MCExpr *Expr);
145 bool parseSetFeature(uint64_t Feature);
146 bool parseDirectiveCPLoad(SMLoc Loc);
147 bool parseDirectiveCPSetup();
148 bool parseDirectiveNaN();
149 bool parseDirectiveSet();
150 bool parseDirectiveOption();
152 bool parseSetAtDirective();
153 bool parseSetNoAtDirective();
154 bool parseSetMacroDirective();
155 bool parseSetNoMacroDirective();
156 bool parseSetReorderDirective();
157 bool parseSetNoReorderDirective();
158 bool parseSetNoMips16Directive();
159 bool parseSetFpDirective();
161 bool parseSetAssignment();
163 bool parseDataDirective(unsigned Size, SMLoc L);
164 bool parseDirectiveGpWord();
165 bool parseDirectiveGpDWord();
166 bool parseDirectiveModule();
167 bool parseDirectiveModuleFP();
168 bool parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
169 StringRef Directive);
171 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
173 bool eatComma(StringRef ErrorStr);
175 int matchCPURegisterName(StringRef Symbol);
177 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
179 int matchFPURegisterName(StringRef Name);
181 int matchFCCRegisterName(StringRef Name);
183 int matchACRegisterName(StringRef Name);
185 int matchMSA128RegisterName(StringRef Name);
187 int matchMSA128CtrlRegisterName(StringRef Name);
189 unsigned getReg(int RC, int RegNo);
191 unsigned getGPR(int RegNo);
193 int getATReg(SMLoc Loc);
195 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
196 SmallVectorImpl<MCInst> &Instructions);
198 // Helper function that checks if the value of a vector index is within the
199 // boundaries of accepted values for each RegisterKind
200 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
201 bool validateMSAIndex(int Val, int RegKind);
203 void setFeatureBits(unsigned Feature, StringRef FeatureString) {
204 if (!(STI.getFeatureBits() & Feature)) {
205 setAvailableFeatures(
206 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
210 void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
211 if (STI.getFeatureBits() & Feature) {
212 setAvailableFeatures(
213 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
218 enum MipsMatchResultTy {
219 Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY
220 #define GET_OPERAND_DIAGNOSTIC_TYPES
221 #include "MipsGenAsmMatcher.inc"
222 #undef GET_OPERAND_DIAGNOSTIC_TYPES
226 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
227 const MCInstrInfo &MII, const MCTargetOptions &Options)
228 : MCTargetAsmParser(), STI(sti), Parser(parser) {
229 // Initialize the set of available features.
230 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
232 getTargetStreamer().updateABIInfo(*this);
234 // Assert exactly one ABI was chosen.
235 assert((((STI.getFeatureBits() & Mips::FeatureO32) != 0) +
236 ((STI.getFeatureBits() & Mips::FeatureEABI) != 0) +
237 ((STI.getFeatureBits() & Mips::FeatureN32) != 0) +
238 ((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
240 if (!isABI_O32() && !useOddSPReg() != 0)
241 report_fatal_error("-mno-odd-spreg requires the O32 ABI");
244 MCAsmParser &getParser() const { return Parser; }
245 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
247 /// True if all of $fcc0 - $fcc7 exist for the current ISA.
248 bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
250 bool isGP64bit() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
251 bool isFP64bit() const { return STI.getFeatureBits() & Mips::FeatureFP64Bit; }
252 bool isABI_N32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
253 bool isABI_N64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
254 bool isABI_O32() const { return STI.getFeatureBits() & Mips::FeatureO32; }
255 bool isABI_FPXX() const { return STI.getFeatureBits() & Mips::FeatureFPXX; }
257 bool useOddSPReg() const {
258 return !(STI.getFeatureBits() & Mips::FeatureNoOddSPReg);
261 bool inMicroMipsMode() const {
262 return STI.getFeatureBits() & Mips::FeatureMicroMips;
264 bool hasMips1() const { return STI.getFeatureBits() & Mips::FeatureMips1; }
265 bool hasMips2() const { return STI.getFeatureBits() & Mips::FeatureMips2; }
266 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
267 bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4; }
268 bool hasMips5() const { return STI.getFeatureBits() & Mips::FeatureMips5; }
269 bool hasMips32() const {
270 return (STI.getFeatureBits() & Mips::FeatureMips32);
272 bool hasMips64() const {
273 return (STI.getFeatureBits() & Mips::FeatureMips64);
275 bool hasMips32r2() const {
276 return (STI.getFeatureBits() & Mips::FeatureMips32r2);
278 bool hasMips64r2() const {
279 return (STI.getFeatureBits() & Mips::FeatureMips64r2);
281 bool hasMips32r6() const {
282 return (STI.getFeatureBits() & Mips::FeatureMips32r6);
284 bool hasMips64r6() const {
285 return (STI.getFeatureBits() & Mips::FeatureMips64r6);
287 bool hasDSP() const { return (STI.getFeatureBits() & Mips::FeatureDSP); }
288 bool hasDSPR2() const { return (STI.getFeatureBits() & Mips::FeatureDSPR2); }
289 bool hasMSA() const { return (STI.getFeatureBits() & Mips::FeatureMSA); }
291 bool inMips16Mode() const {
292 return STI.getFeatureBits() & Mips::FeatureMips16;
294 // TODO: see how can we get this info.
295 bool abiUsesSoftFloat() const { return false; }
297 /// Warn if RegNo is the current assembler temporary.
298 void WarnIfAssemblerTemporary(int RegNo, SMLoc Loc);
304 /// MipsOperand - Instances of this class represent a parsed Mips machine
306 class MipsOperand : public MCParsedAsmOperand {
308 /// Broad categories of register classes
309 /// The exact class is finalized by the render method.
311 RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64bit())
312 RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and
314 RegKind_FCC = 4, /// FCC
315 RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which)
316 RegKind_MSACtrl = 16, /// MSA control registers
317 RegKind_COP2 = 32, /// COP2
318 RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on
320 RegKind_CCR = 128, /// CCR
321 RegKind_HWRegs = 256, /// HWRegs
322 RegKind_COP3 = 512, /// COP3
324 /// Potentially any (e.g. $1)
325 RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
326 RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
327 RegKind_CCR | RegKind_HWRegs | RegKind_COP3
332 k_Immediate, /// An immediate (possibly involving symbol references)
333 k_Memory, /// Base + Offset Memory Address
334 k_PhysRegister, /// A physical register from the Mips namespace
335 k_RegisterIndex, /// A register index in one or more RegKind.
336 k_Token /// A simple token
340 MipsOperand(KindTy K, MipsAsmParser &Parser)
341 : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
344 /// For diagnostics, and checking the assembler temporary
345 MipsAsmParser &AsmParser;
353 unsigned Num; /// Register Number
357 unsigned Index; /// Index into the register class
358 RegKind Kind; /// Bitfield of the kinds it could possibly be
359 const MCRegisterInfo *RegInfo;
373 struct PhysRegOp PhysReg;
374 struct RegIdxOp RegIdx;
379 SMLoc StartLoc, EndLoc;
381 /// Internal constructor for register kinds
382 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind,
383 const MCRegisterInfo *RegInfo,
385 MipsAsmParser &Parser) {
386 auto Op = make_unique<MipsOperand>(k_RegisterIndex, Parser);
387 Op->RegIdx.Index = Index;
388 Op->RegIdx.RegInfo = RegInfo;
389 Op->RegIdx.Kind = RegKind;
396 /// Coerce the register to GPR32 and return the real register for the current
398 unsigned getGPR32Reg() const {
399 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
400 AsmParser.WarnIfAssemblerTemporary(RegIdx.Index, StartLoc);
401 unsigned ClassID = Mips::GPR32RegClassID;
402 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
405 /// Coerce the register to GPR64 and return the real register for the current
407 unsigned getGPR64Reg() const {
408 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
409 unsigned ClassID = Mips::GPR64RegClassID;
410 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
414 /// Coerce the register to AFGR64 and return the real register for the current
416 unsigned getAFGR64Reg() const {
417 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
418 if (RegIdx.Index % 2 != 0)
419 AsmParser.Warning(StartLoc, "Float register should be even.");
420 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
421 .getRegister(RegIdx.Index / 2);
424 /// Coerce the register to FGR64 and return the real register for the current
426 unsigned getFGR64Reg() const {
427 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
428 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
429 .getRegister(RegIdx.Index);
432 /// Coerce the register to FGR32 and return the real register for the current
434 unsigned getFGR32Reg() const {
435 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
436 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
437 .getRegister(RegIdx.Index);
440 /// Coerce the register to FGRH32 and return the real register for the current
442 unsigned getFGRH32Reg() const {
443 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
444 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)
445 .getRegister(RegIdx.Index);
448 /// Coerce the register to FCC and return the real register for the current
450 unsigned getFCCReg() const {
451 assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
452 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
453 .getRegister(RegIdx.Index);
456 /// Coerce the register to MSA128 and return the real register for the current
458 unsigned getMSA128Reg() const {
459 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
460 // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
462 unsigned ClassID = Mips::MSA128BRegClassID;
463 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
466 /// Coerce the register to MSACtrl and return the real register for the
468 unsigned getMSACtrlReg() const {
469 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
470 unsigned ClassID = Mips::MSACtrlRegClassID;
471 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
474 /// Coerce the register to COP2 and return the real register for the
476 unsigned getCOP2Reg() const {
477 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
478 unsigned ClassID = Mips::COP2RegClassID;
479 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
482 /// Coerce the register to COP3 and return the real register for the
484 unsigned getCOP3Reg() const {
485 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
486 unsigned ClassID = Mips::COP3RegClassID;
487 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
490 /// Coerce the register to ACC64DSP and return the real register for the
492 unsigned getACC64DSPReg() const {
493 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
494 unsigned ClassID = Mips::ACC64DSPRegClassID;
495 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
498 /// Coerce the register to HI32DSP and return the real register for the
500 unsigned getHI32DSPReg() const {
501 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
502 unsigned ClassID = Mips::HI32DSPRegClassID;
503 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
506 /// Coerce the register to LO32DSP and return the real register for the
508 unsigned getLO32DSPReg() const {
509 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
510 unsigned ClassID = Mips::LO32DSPRegClassID;
511 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
514 /// Coerce the register to CCR and return the real register for the
516 unsigned getCCRReg() const {
517 assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
518 unsigned ClassID = Mips::CCRRegClassID;
519 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
522 /// Coerce the register to HWRegs and return the real register for the
524 unsigned getHWRegsReg() const {
525 assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
526 unsigned ClassID = Mips::HWRegsRegClassID;
527 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
531 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
532 // Add as immediate when possible. Null MCExpr = 0.
534 Inst.addOperand(MCOperand::CreateImm(0));
535 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
536 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
538 Inst.addOperand(MCOperand::CreateExpr(Expr));
541 void addRegOperands(MCInst &Inst, unsigned N) const {
542 llvm_unreachable("Use a custom parser instead");
545 /// Render the operand to an MCInst as a GPR32
546 /// Asserts if the wrong number of operands are requested, or the operand
547 /// is not a k_RegisterIndex compatible with RegKind_GPR
548 void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
549 assert(N == 1 && "Invalid number of operands!");
550 Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
553 /// Render the operand to an MCInst as a GPR64
554 /// Asserts if the wrong number of operands are requested, or the operand
555 /// is not a k_RegisterIndex compatible with RegKind_GPR
556 void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
557 assert(N == 1 && "Invalid number of operands!");
558 Inst.addOperand(MCOperand::CreateReg(getGPR64Reg()));
561 void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
562 assert(N == 1 && "Invalid number of operands!");
563 Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg()));
566 void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
567 assert(N == 1 && "Invalid number of operands!");
568 Inst.addOperand(MCOperand::CreateReg(getFGR64Reg()));
571 void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
572 assert(N == 1 && "Invalid number of operands!");
573 Inst.addOperand(MCOperand::CreateReg(getFGR32Reg()));
574 // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
575 if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
576 AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
580 void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
581 assert(N == 1 && "Invalid number of operands!");
582 Inst.addOperand(MCOperand::CreateReg(getFGRH32Reg()));
585 void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
586 assert(N == 1 && "Invalid number of operands!");
587 Inst.addOperand(MCOperand::CreateReg(getFCCReg()));
590 void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
591 assert(N == 1 && "Invalid number of operands!");
592 Inst.addOperand(MCOperand::CreateReg(getMSA128Reg()));
595 void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
596 assert(N == 1 && "Invalid number of operands!");
597 Inst.addOperand(MCOperand::CreateReg(getMSACtrlReg()));
600 void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
601 assert(N == 1 && "Invalid number of operands!");
602 Inst.addOperand(MCOperand::CreateReg(getCOP2Reg()));
605 void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
606 assert(N == 1 && "Invalid number of operands!");
607 Inst.addOperand(MCOperand::CreateReg(getCOP3Reg()));
610 void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
611 assert(N == 1 && "Invalid number of operands!");
612 Inst.addOperand(MCOperand::CreateReg(getACC64DSPReg()));
615 void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
616 assert(N == 1 && "Invalid number of operands!");
617 Inst.addOperand(MCOperand::CreateReg(getHI32DSPReg()));
620 void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
621 assert(N == 1 && "Invalid number of operands!");
622 Inst.addOperand(MCOperand::CreateReg(getLO32DSPReg()));
625 void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
626 assert(N == 1 && "Invalid number of operands!");
627 Inst.addOperand(MCOperand::CreateReg(getCCRReg()));
630 void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
631 assert(N == 1 && "Invalid number of operands!");
632 Inst.addOperand(MCOperand::CreateReg(getHWRegsReg()));
635 void addImmOperands(MCInst &Inst, unsigned N) const {
636 assert(N == 1 && "Invalid number of operands!");
637 const MCExpr *Expr = getImm();
641 void addMemOperands(MCInst &Inst, unsigned N) const {
642 assert(N == 2 && "Invalid number of operands!");
644 Inst.addOperand(MCOperand::CreateReg(getMemBase()->getGPR32Reg()));
646 const MCExpr *Expr = getMemOff();
650 bool isReg() const override {
651 // As a special case until we sort out the definition of div/divu, pretend
652 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
653 if (isGPRAsmReg() && RegIdx.Index == 0)
656 return Kind == k_PhysRegister;
658 bool isRegIdx() const { return Kind == k_RegisterIndex; }
659 bool isImm() const override { return Kind == k_Immediate; }
660 bool isConstantImm() const {
661 return isImm() && dyn_cast<MCConstantExpr>(getImm());
663 bool isToken() const override {
664 // Note: It's not possible to pretend that other operand kinds are tokens.
665 // The matcher emitter checks tokens first.
666 return Kind == k_Token;
668 bool isMem() const override { return Kind == k_Memory; }
669 bool isConstantMemOff() const {
670 return isMem() && dyn_cast<MCConstantExpr>(getMemOff());
672 template <unsigned Bits> bool isMemWithSimmOffset() const {
673 return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff());
675 bool isInvNum() const { return Kind == k_Immediate; }
676 bool isLSAImm() const {
677 if (!isConstantImm())
679 int64_t Val = getConstantImm();
680 return 1 <= Val && Val <= 4;
683 StringRef getToken() const {
684 assert(Kind == k_Token && "Invalid access!");
685 return StringRef(Tok.Data, Tok.Length);
688 unsigned getReg() const override {
689 // As a special case until we sort out the definition of div/divu, pretend
690 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
691 if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
692 RegIdx.Kind & RegKind_GPR)
693 return getGPR32Reg(); // FIXME: GPR64 too
695 assert(Kind == k_PhysRegister && "Invalid access!");
699 const MCExpr *getImm() const {
700 assert((Kind == k_Immediate) && "Invalid access!");
704 int64_t getConstantImm() const {
705 const MCExpr *Val = getImm();
706 return static_cast<const MCConstantExpr *>(Val)->getValue();
709 MipsOperand *getMemBase() const {
710 assert((Kind == k_Memory) && "Invalid access!");
714 const MCExpr *getMemOff() const {
715 assert((Kind == k_Memory) && "Invalid access!");
719 int64_t getConstantMemOff() const {
720 return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
723 static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S,
724 MipsAsmParser &Parser) {
725 auto Op = make_unique<MipsOperand>(k_Token, Parser);
726 Op->Tok.Data = Str.data();
727 Op->Tok.Length = Str.size();
733 /// Create a numeric register (e.g. $1). The exact register remains
734 /// unresolved until an instruction successfully matches
735 static std::unique_ptr<MipsOperand>
736 CreateNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
737 SMLoc E, MipsAsmParser &Parser) {
738 DEBUG(dbgs() << "CreateNumericReg(" << Index << ", ...)\n");
739 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser);
742 /// Create a register that is definitely a GPR.
743 /// This is typically only used for named registers such as $gp.
744 static std::unique_ptr<MipsOperand>
745 CreateGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
746 MipsAsmParser &Parser) {
747 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser);
750 /// Create a register that is definitely a FGR.
751 /// This is typically only used for named registers such as $f0.
752 static std::unique_ptr<MipsOperand>
753 CreateFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
754 MipsAsmParser &Parser) {
755 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
758 /// Create a register that is definitely an FCC.
759 /// This is typically only used for named registers such as $fcc0.
760 static std::unique_ptr<MipsOperand>
761 CreateFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
762 MipsAsmParser &Parser) {
763 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
766 /// Create a register that is definitely an ACC.
767 /// This is typically only used for named registers such as $ac0.
768 static std::unique_ptr<MipsOperand>
769 CreateACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
770 MipsAsmParser &Parser) {
771 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser);
774 /// Create a register that is definitely an MSA128.
775 /// This is typically only used for named registers such as $w0.
776 static std::unique_ptr<MipsOperand>
777 CreateMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
778 SMLoc E, MipsAsmParser &Parser) {
779 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser);
782 /// Create a register that is definitely an MSACtrl.
783 /// This is typically only used for named registers such as $msaaccess.
784 static std::unique_ptr<MipsOperand>
785 CreateMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
786 SMLoc E, MipsAsmParser &Parser) {
787 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
790 static std::unique_ptr<MipsOperand>
791 CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
792 auto Op = make_unique<MipsOperand>(k_Immediate, Parser);
799 static std::unique_ptr<MipsOperand>
800 CreateMem(std::unique_ptr<MipsOperand> Base, const MCExpr *Off, SMLoc S,
801 SMLoc E, MipsAsmParser &Parser) {
802 auto Op = make_unique<MipsOperand>(k_Memory, Parser);
803 Op->Mem.Base = Base.release();
810 bool isGPRAsmReg() const {
811 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
813 bool isFGRAsmReg() const {
814 // AFGR64 is $0-$15 but we handle this in getAFGR64()
815 return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
817 bool isHWRegsAsmReg() const {
818 return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
820 bool isCCRAsmReg() const {
821 return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
823 bool isFCCAsmReg() const {
824 if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC))
826 if (!AsmParser.hasEightFccRegisters())
827 return RegIdx.Index == 0;
828 return RegIdx.Index <= 7;
830 bool isACCAsmReg() const {
831 return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
833 bool isCOP2AsmReg() const {
834 return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
836 bool isCOP3AsmReg() const {
837 return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
839 bool isMSA128AsmReg() const {
840 return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
842 bool isMSACtrlAsmReg() const {
843 return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
846 /// getStartLoc - Get the location of the first token of this operand.
847 SMLoc getStartLoc() const override { return StartLoc; }
848 /// getEndLoc - Get the location of the last token of this operand.
849 SMLoc getEndLoc() const override { return EndLoc; }
851 virtual ~MipsOperand() {
859 case k_RegisterIndex:
865 void print(raw_ostream &OS) const override {
880 OS << "PhysReg<" << PhysReg.Num << ">";
882 case k_RegisterIndex:
883 OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">";
890 }; // class MipsOperand
894 extern const MCInstrDesc MipsInsts[];
896 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
897 return MipsInsts[Opcode];
900 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
901 SmallVectorImpl<MCInst> &Instructions) {
902 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
906 if (MCID.isBranch() || MCID.isCall()) {
907 const unsigned Opcode = Inst.getOpcode();
917 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
918 Offset = Inst.getOperand(2);
920 break; // We'll deal with this situation later on when applying fixups.
921 if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
922 return Error(IDLoc, "branch target out of range");
923 if (OffsetToAlignment(Offset.getImm(),
924 1LL << (inMicroMipsMode() ? 1 : 2)))
925 return Error(IDLoc, "branch to misaligned address");
939 case Mips::BGEZAL_MM:
940 case Mips::BLTZAL_MM:
943 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
944 Offset = Inst.getOperand(1);
946 break; // We'll deal with this situation later on when applying fixups.
947 if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
948 return Error(IDLoc, "branch target out of range");
949 if (OffsetToAlignment(Offset.getImm(),
950 1LL << (inMicroMipsMode() ? 1 : 2)))
951 return Error(IDLoc, "branch to misaligned address");
956 // SSNOP is deprecated on MIPS32r6/MIPS64r6
957 // We still accept it but it is a normal nop.
958 if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) {
959 std::string ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
960 Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a "
964 if (MCID.hasDelaySlot() && Options.isReorder()) {
965 // If this instruction has a delay slot and .set reorder is active,
966 // emit a NOP after it.
967 Instructions.push_back(Inst);
969 NopInst.setOpcode(Mips::SLL);
970 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
971 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
972 NopInst.addOperand(MCOperand::CreateImm(0));
973 Instructions.push_back(NopInst);
977 if (MCID.mayLoad() || MCID.mayStore()) {
978 // Check the offset of memory operand, if it is a symbol
979 // reference or immediate we may have to expand instructions.
980 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
981 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
982 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
983 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
984 MCOperand &Op = Inst.getOperand(i);
986 int MemOffset = Op.getImm();
987 if (MemOffset < -32768 || MemOffset > 32767) {
988 // Offset can't exceed 16bit value.
989 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
992 } else if (Op.isExpr()) {
993 const MCExpr *Expr = Op.getExpr();
994 if (Expr->getKind() == MCExpr::SymbolRef) {
995 const MCSymbolRefExpr *SR =
996 static_cast<const MCSymbolRefExpr *>(Expr);
997 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
999 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
1002 } else if (!isEvaluated(Expr)) {
1003 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
1011 if (needsExpansion(Inst))
1012 return expandInstruction(Inst, IDLoc, Instructions);
1014 Instructions.push_back(Inst);
1019 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
1021 switch (Inst.getOpcode()) {
1022 case Mips::LoadImm32Reg:
1023 case Mips::LoadAddr32Imm:
1024 case Mips::LoadAddr32Reg:
1025 case Mips::LoadImm64Reg:
1032 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
1033 SmallVectorImpl<MCInst> &Instructions) {
1034 switch (Inst.getOpcode()) {
1036 assert(0 && "unimplemented expansion");
1038 case Mips::LoadImm32Reg:
1039 return expandLoadImm(Inst, IDLoc, Instructions);
1040 case Mips::LoadImm64Reg:
1042 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1045 return expandLoadImm(Inst, IDLoc, Instructions);
1046 case Mips::LoadAddr32Imm:
1047 return expandLoadAddressImm(Inst, IDLoc, Instructions);
1048 case Mips::LoadAddr32Reg:
1049 return expandLoadAddressReg(Inst, IDLoc, Instructions);
1054 template <int Shift, bool PerformShift>
1055 void createShiftOr(int64_t Value, unsigned RegNo, SMLoc IDLoc,
1056 SmallVectorImpl<MCInst> &Instructions) {
1059 tmpInst.setOpcode(Mips::DSLL);
1060 tmpInst.addOperand(MCOperand::CreateReg(RegNo));
1061 tmpInst.addOperand(MCOperand::CreateReg(RegNo));
1062 tmpInst.addOperand(MCOperand::CreateImm(16));
1063 tmpInst.setLoc(IDLoc);
1064 Instructions.push_back(tmpInst);
1067 tmpInst.setOpcode(Mips::ORi);
1068 tmpInst.addOperand(MCOperand::CreateReg(RegNo));
1069 tmpInst.addOperand(MCOperand::CreateReg(RegNo));
1071 MCOperand::CreateImm(((Value & (0xffffLL << Shift)) >> Shift)));
1072 tmpInst.setLoc(IDLoc);
1073 Instructions.push_back(tmpInst);
1077 bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
1078 SmallVectorImpl<MCInst> &Instructions) {
1080 const MCOperand &ImmOp = Inst.getOperand(1);
1081 assert(ImmOp.isImm() && "expected immediate operand kind");
1082 const MCOperand &RegOp = Inst.getOperand(0);
1083 assert(RegOp.isReg() && "expected register operand kind");
1085 int64_t ImmValue = ImmOp.getImm();
1086 tmpInst.setLoc(IDLoc);
1087 // FIXME: gas has a special case for values that are 000...1111, which
1088 // becomes a li -1 and then a dsrl
1089 if (0 <= ImmValue && ImmValue <= 65535) {
1090 // For 0 <= j <= 65535.
1091 // li d,j => ori d,$zero,j
1092 tmpInst.setOpcode(Mips::ORi);
1093 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1094 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1095 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1096 Instructions.push_back(tmpInst);
1097 } else if (ImmValue < 0 && ImmValue >= -32768) {
1098 // For -32768 <= j < 0.
1099 // li d,j => addiu d,$zero,j
1100 tmpInst.setOpcode(Mips::ADDiu);
1101 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1102 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1103 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1104 Instructions.push_back(tmpInst);
1105 } else if ((ImmValue & 0xffffffff) == ImmValue) {
1106 // For any value of j that is representable as a 32-bit integer, create
1108 // li d,j => lui d,hi16(j)
1110 tmpInst.setOpcode(Mips::LUi);
1111 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1112 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1113 Instructions.push_back(tmpInst);
1114 createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1115 } else if ((ImmValue & (0xffffLL << 48)) == 0) {
1117 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1121 // <------- lo32 ------>
1122 // <------- hi32 ------>
1123 // <- hi16 -> <- lo16 ->
1124 // _________________________________
1126 // | 16-bytes | 16-bytes | 16-bytes |
1127 // |__________|__________|__________|
1129 // For any value of j that is representable as a 48-bit integer, create
1131 // li d,j => lui d,hi16(j)
1132 // ori d,d,hi16(lo32(j))
1134 // ori d,d,lo16(lo32(j))
1135 tmpInst.setOpcode(Mips::LUi);
1136 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1138 MCOperand::CreateImm((ImmValue & (0xffffLL << 32)) >> 32));
1139 Instructions.push_back(tmpInst);
1140 createShiftOr<16, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1141 createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1144 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1148 // <------- hi32 ------> <------- lo32 ------>
1149 // <- hi16 -> <- lo16 ->
1150 // ___________________________________________
1152 // | 16-bytes | 16-bytes | 16-bytes | 16-bytes |
1153 // |__________|__________|__________|__________|
1155 // For any value of j that isn't representable as a 48-bit integer.
1156 // li d,j => lui d,hi16(j)
1157 // ori d,d,lo16(hi32(j))
1159 // ori d,d,hi16(lo32(j))
1161 // ori d,d,lo16(lo32(j))
1162 tmpInst.setOpcode(Mips::LUi);
1163 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1165 MCOperand::CreateImm((ImmValue & (0xffffLL << 48)) >> 48));
1166 Instructions.push_back(tmpInst);
1167 createShiftOr<32, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1168 createShiftOr<16, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1169 createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1175 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
1176 SmallVectorImpl<MCInst> &Instructions) {
1178 const MCOperand &ImmOp = Inst.getOperand(2);
1179 assert(ImmOp.isImm() && "expected immediate operand kind");
1180 const MCOperand &SrcRegOp = Inst.getOperand(1);
1181 assert(SrcRegOp.isReg() && "expected register operand kind");
1182 const MCOperand &DstRegOp = Inst.getOperand(0);
1183 assert(DstRegOp.isReg() && "expected register operand kind");
1184 int ImmValue = ImmOp.getImm();
1185 if (-32768 <= ImmValue && ImmValue <= 65535) {
1186 // For -32768 <= j <= 65535.
1187 // la d,j(s) => addiu d,s,j
1188 tmpInst.setOpcode(Mips::ADDiu);
1189 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1190 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1191 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1192 Instructions.push_back(tmpInst);
1194 // For any other value of j that is representable as a 32-bit integer.
1195 // la d,j(s) => lui d,hi16(j)
1198 tmpInst.setOpcode(Mips::LUi);
1199 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1200 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1201 Instructions.push_back(tmpInst);
1203 tmpInst.setOpcode(Mips::ORi);
1204 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1205 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1206 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1207 Instructions.push_back(tmpInst);
1209 tmpInst.setOpcode(Mips::ADDu);
1210 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1211 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1212 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1213 Instructions.push_back(tmpInst);
1219 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
1220 SmallVectorImpl<MCInst> &Instructions) {
1222 const MCOperand &ImmOp = Inst.getOperand(1);
1223 assert(ImmOp.isImm() && "expected immediate operand kind");
1224 const MCOperand &RegOp = Inst.getOperand(0);
1225 assert(RegOp.isReg() && "expected register operand kind");
1226 int ImmValue = ImmOp.getImm();
1227 if (-32768 <= ImmValue && ImmValue <= 65535) {
1228 // For -32768 <= j <= 65535.
1229 // la d,j => addiu d,$zero,j
1230 tmpInst.setOpcode(Mips::ADDiu);
1231 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1232 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1233 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1234 Instructions.push_back(tmpInst);
1236 // For any other value of j that is representable as a 32-bit integer.
1237 // la d,j => lui d,hi16(j)
1239 tmpInst.setOpcode(Mips::LUi);
1240 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1241 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1242 Instructions.push_back(tmpInst);
1244 tmpInst.setOpcode(Mips::ORi);
1245 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1246 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1247 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1248 Instructions.push_back(tmpInst);
1253 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
1254 SmallVectorImpl<MCInst> &Instructions,
1255 bool isLoad, bool isImmOpnd) {
1256 const MCSymbolRefExpr *SR;
1258 unsigned ImmOffset, HiOffset, LoOffset;
1259 const MCExpr *ExprOffset;
1261 // 1st operand is either the source or destination register.
1262 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
1263 unsigned RegOpNum = Inst.getOperand(0).getReg();
1264 // 2nd operand is the base register.
1265 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
1266 unsigned BaseRegNum = Inst.getOperand(1).getReg();
1267 // 3rd operand is either an immediate or expression.
1269 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
1270 ImmOffset = Inst.getOperand(2).getImm();
1271 LoOffset = ImmOffset & 0x0000ffff;
1272 HiOffset = (ImmOffset & 0xffff0000) >> 16;
1273 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
1274 if (LoOffset & 0x8000)
1277 ExprOffset = Inst.getOperand(2).getExpr();
1278 // All instructions will have the same location.
1279 TempInst.setLoc(IDLoc);
1280 // These are some of the types of expansions we perform here:
1281 // 1) lw $8, sym => lui $8, %hi(sym)
1282 // lw $8, %lo(sym)($8)
1283 // 2) lw $8, offset($9) => lui $8, %hi(offset)
1285 // lw $8, %lo(offset)($9)
1286 // 3) lw $8, offset($8) => lui $at, %hi(offset)
1288 // lw $8, %lo(offset)($at)
1289 // 4) sw $8, sym => lui $at, %hi(sym)
1290 // sw $8, %lo(sym)($at)
1291 // 5) sw $8, offset($8) => lui $at, %hi(offset)
1293 // sw $8, %lo(offset)($at)
1294 // 6) ldc1 $f0, sym => lui $at, %hi(sym)
1295 // ldc1 $f0, %lo(sym)($at)
1297 // For load instructions we can use the destination register as a temporary
1298 // if base and dst are different (examples 1 and 2) and if the base register
1299 // is general purpose otherwise we must use $at (example 6) and error if it's
1300 // not available. For stores we must use $at (examples 4 and 5) because we
1301 // must not clobber the source register setting up the offset.
1302 const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
1303 int16_t RegClassOp0 = Desc.OpInfo[0].RegClass;
1304 unsigned RegClassIDOp0 =
1305 getContext().getRegisterInfo()->getRegClass(RegClassOp0).getID();
1306 bool IsGPR = (RegClassIDOp0 == Mips::GPR32RegClassID) ||
1307 (RegClassIDOp0 == Mips::GPR64RegClassID);
1308 if (isLoad && IsGPR && (BaseRegNum != RegOpNum))
1309 TmpRegNum = RegOpNum;
1311 int AT = getATReg(IDLoc);
1312 // At this point we need AT to perform the expansions and we exit if it is
1317 (isGP64bit()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, AT);
1320 TempInst.setOpcode(Mips::LUi);
1321 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1323 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
1325 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1326 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
1327 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
1328 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
1330 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1332 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
1333 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1336 // Add the instruction to the list.
1337 Instructions.push_back(TempInst);
1338 // Prepare TempInst for next instruction.
1340 // Add temp register to base.
1341 TempInst.setOpcode(Mips::ADDu);
1342 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1343 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1344 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
1345 Instructions.push_back(TempInst);
1347 // And finally, create original instruction with low part
1348 // of offset and new base.
1349 TempInst.setOpcode(Inst.getOpcode());
1350 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
1351 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1353 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
1355 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1356 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
1357 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
1359 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1361 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
1362 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1365 Instructions.push_back(TempInst);
1369 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
1370 // As described by the Mips32r2 spec, the registers Rd and Rs for
1371 // jalr.hb must be different.
1372 unsigned Opcode = Inst.getOpcode();
1374 if (Opcode == Mips::JALR_HB &&
1375 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()))
1376 return Match_RequiresDifferentSrcAndDst;
1378 return Match_Success;
1381 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1382 OperandVector &Operands,
1384 unsigned &ErrorInfo,
1385 bool MatchingInlineAsm) {
1388 SmallVector<MCInst, 8> Instructions;
1389 unsigned MatchResult =
1390 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
1392 switch (MatchResult) {
1395 case Match_Success: {
1396 if (processInstruction(Inst, IDLoc, Instructions))
1398 for (unsigned i = 0; i < Instructions.size(); i++)
1399 Out.EmitInstruction(Instructions[i], STI);
1402 case Match_MissingFeature:
1403 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1405 case Match_InvalidOperand: {
1406 SMLoc ErrorLoc = IDLoc;
1407 if (ErrorInfo != ~0U) {
1408 if (ErrorInfo >= Operands.size())
1409 return Error(IDLoc, "too few operands for instruction");
1411 ErrorLoc = ((MipsOperand &)*Operands[ErrorInfo]).getStartLoc();
1412 if (ErrorLoc == SMLoc())
1416 return Error(ErrorLoc, "invalid operand for instruction");
1418 case Match_MnemonicFail:
1419 return Error(IDLoc, "invalid instruction");
1420 case Match_RequiresDifferentSrcAndDst:
1421 return Error(IDLoc, "source and destination must be different");
1426 void MipsAsmParser::WarnIfAssemblerTemporary(int RegIndex, SMLoc Loc) {
1427 if ((RegIndex != 0) && ((int)Options.getATRegNum() == RegIndex)) {
1429 Warning(Loc, "Used $at without \".set noat\"");
1431 Warning(Loc, Twine("Used $") + Twine(RegIndex) + " with \".set at=$" +
1432 Twine(RegIndex) + "\"");
1436 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
1439 CC = StringSwitch<unsigned>(Name)
1475 if (isABI_N32() || isABI_N64()) {
1476 // Although SGI documentation just cuts out t0-t3 for n32/n64,
1477 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
1478 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
1479 if (8 <= CC && CC <= 11)
1483 CC = StringSwitch<unsigned>(Name)
1496 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
1498 if (Name[0] == 'f') {
1499 StringRef NumString = Name.substr(1);
1501 if (NumString.getAsInteger(10, IntVal))
1502 return -1; // This is not an integer.
1503 if (IntVal > 31) // Maximum index for fpu register.
1510 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
1512 if (Name.startswith("fcc")) {
1513 StringRef NumString = Name.substr(3);
1515 if (NumString.getAsInteger(10, IntVal))
1516 return -1; // This is not an integer.
1517 if (IntVal > 7) // There are only 8 fcc registers.
1524 int MipsAsmParser::matchACRegisterName(StringRef Name) {
1526 if (Name.startswith("ac")) {
1527 StringRef NumString = Name.substr(2);
1529 if (NumString.getAsInteger(10, IntVal))
1530 return -1; // This is not an integer.
1531 if (IntVal > 3) // There are only 3 acc registers.
1538 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
1541 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
1550 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1553 CC = StringSwitch<unsigned>(Name)
1556 .Case("msaaccess", 2)
1558 .Case("msamodify", 4)
1559 .Case("msarequest", 5)
1561 .Case("msaunmap", 7)
1567 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1575 int MipsAsmParser::getATReg(SMLoc Loc) {
1576 int AT = Options.getATRegNum();
1578 reportParseError(Loc,
1579 "Pseudo instruction requires $at, which is not available");
1583 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1584 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1587 unsigned MipsAsmParser::getGPR(int RegNo) {
1588 return getReg(isGP64bit() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
1592 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1594 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
1597 return getReg(RegClass, RegNum);
1600 bool MipsAsmParser::ParseOperand(OperandVector &Operands, StringRef Mnemonic) {
1601 DEBUG(dbgs() << "ParseOperand\n");
1603 // Check if the current operand has a custom associated parser, if so, try to
1604 // custom parse the operand, or fallback to the general approach.
1605 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1606 if (ResTy == MatchOperand_Success)
1608 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1609 // there was a match, but an error occurred, in which case, just return that
1610 // the operand parsing failed.
1611 if (ResTy == MatchOperand_ParseFail)
1614 DEBUG(dbgs() << ".. Generic Parser\n");
1616 switch (getLexer().getKind()) {
1618 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1620 case AsmToken::Dollar: {
1621 // Parse the register.
1622 SMLoc S = Parser.getTok().getLoc();
1624 // Almost all registers have been parsed by custom parsers. There is only
1625 // one exception to this. $zero (and it's alias $0) will reach this point
1626 // for div, divu, and similar instructions because it is not an operand
1627 // to the instruction definition but an explicit register. Special case
1628 // this situation for now.
1629 if (ParseAnyRegister(Operands) != MatchOperand_NoMatch)
1632 // Maybe it is a symbol reference.
1633 StringRef Identifier;
1634 if (Parser.parseIdentifier(Identifier))
1637 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1638 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1639 // Otherwise create a symbol reference.
1641 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1643 Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this));
1646 // Else drop to expression parsing.
1647 case AsmToken::LParen:
1648 case AsmToken::Minus:
1649 case AsmToken::Plus:
1650 case AsmToken::Integer:
1651 case AsmToken::Tilde:
1652 case AsmToken::String: {
1653 DEBUG(dbgs() << ".. generic integer\n");
1654 OperandMatchResultTy ResTy = ParseImm(Operands);
1655 return ResTy != MatchOperand_Success;
1657 case AsmToken::Percent: {
1658 // It is a symbol reference or constant expression.
1659 const MCExpr *IdVal;
1660 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1661 if (parseRelocOperand(IdVal))
1664 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1666 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1668 } // case AsmToken::Percent
1669 } // switch(getLexer().getKind())
1673 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1674 StringRef RelocStr) {
1676 // Check the type of the expression.
1677 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1678 // It's a constant, evaluate reloc value.
1680 switch (getVariantKind(RelocStr)) {
1681 case MCSymbolRefExpr::VK_Mips_ABS_LO:
1682 // Get the 1st 16-bits.
1683 Val = MCE->getValue() & 0xffff;
1685 case MCSymbolRefExpr::VK_Mips_ABS_HI:
1686 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1, to compensate for low
1687 // 16 bits being negative.
1688 Val = ((MCE->getValue() + 0x8000) >> 16) & 0xffff;
1690 case MCSymbolRefExpr::VK_Mips_HIGHER:
1691 // Get the 3rd 16-bits.
1692 Val = ((MCE->getValue() + 0x80008000LL) >> 32) & 0xffff;
1694 case MCSymbolRefExpr::VK_Mips_HIGHEST:
1695 // Get the 4th 16-bits.
1696 Val = ((MCE->getValue() + 0x800080008000LL) >> 48) & 0xffff;
1699 report_fatal_error("Unsupported reloc value!");
1701 return MCConstantExpr::Create(Val, getContext());
1704 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1705 // It's a symbol, create a symbolic expression from the symbol.
1706 StringRef Symbol = MSRE->getSymbol().getName();
1707 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1708 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1712 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1713 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1715 // Try to create target expression.
1716 if (MipsMCExpr::isSupportedBinaryExpr(VK, BE))
1717 return MipsMCExpr::Create(VK, Expr, getContext());
1719 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1720 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1721 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1725 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1726 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1727 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1730 // Just return the original expression.
1734 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1736 switch (Expr->getKind()) {
1737 case MCExpr::Constant:
1739 case MCExpr::SymbolRef:
1740 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1741 case MCExpr::Binary:
1742 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1743 if (!isEvaluated(BE->getLHS()))
1745 return isEvaluated(BE->getRHS());
1748 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1749 case MCExpr::Target:
1755 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1756 Parser.Lex(); // Eat the % token.
1757 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1758 if (Tok.isNot(AsmToken::Identifier))
1761 std::string Str = Tok.getIdentifier().str();
1763 Parser.Lex(); // Eat the identifier.
1764 // Now make an expression from the rest of the operand.
1765 const MCExpr *IdVal;
1768 if (getLexer().getKind() == AsmToken::LParen) {
1770 Parser.Lex(); // Eat the '(' token.
1771 if (getLexer().getKind() == AsmToken::Percent) {
1772 Parser.Lex(); // Eat the % token.
1773 const AsmToken &nextTok = Parser.getTok();
1774 if (nextTok.isNot(AsmToken::Identifier))
1777 Str += nextTok.getIdentifier();
1778 Parser.Lex(); // Eat the identifier.
1779 if (getLexer().getKind() != AsmToken::LParen)
1784 if (getParser().parseParenExpression(IdVal, EndLoc))
1787 while (getLexer().getKind() == AsmToken::RParen)
1788 Parser.Lex(); // Eat the ')' token.
1791 return true; // Parenthesis must follow the relocation operand.
1793 Res = evaluateRelocExpr(IdVal, Str);
1797 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1799 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
1800 OperandMatchResultTy ResTy = ParseAnyRegister(Operands);
1801 if (ResTy == MatchOperand_Success) {
1802 assert(Operands.size() == 1);
1803 MipsOperand &Operand = static_cast<MipsOperand &>(*Operands.front());
1804 StartLoc = Operand.getStartLoc();
1805 EndLoc = Operand.getEndLoc();
1807 // AFAIK, we only support numeric registers and named GPR's in CFI
1809 // Don't worry about eating tokens before failing. Using an unrecognised
1810 // register is a parse error.
1811 if (Operand.isGPRAsmReg()) {
1812 // Resolve to GPR32 or GPR64 appropriately.
1813 RegNo = isGP64bit() ? Operand.getGPR64Reg() : Operand.getGPR32Reg();
1816 return (RegNo == (unsigned)-1);
1819 assert(Operands.size() == 0);
1820 return (RegNo == (unsigned)-1);
1823 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1827 while (getLexer().getKind() == AsmToken::LParen)
1830 switch (getLexer().getKind()) {
1833 case AsmToken::Identifier:
1834 case AsmToken::LParen:
1835 case AsmToken::Integer:
1836 case AsmToken::Minus:
1837 case AsmToken::Plus:
1839 Result = getParser().parseParenExpression(Res, S);
1841 Result = (getParser().parseExpression(Res));
1842 while (getLexer().getKind() == AsmToken::RParen)
1845 case AsmToken::Percent:
1846 Result = parseRelocOperand(Res);
1851 MipsAsmParser::OperandMatchResultTy
1852 MipsAsmParser::parseMemOperand(OperandVector &Operands) {
1853 DEBUG(dbgs() << "parseMemOperand\n");
1854 const MCExpr *IdVal = nullptr;
1856 bool isParenExpr = false;
1857 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1858 // First operand is the offset.
1859 S = Parser.getTok().getLoc();
1861 if (getLexer().getKind() == AsmToken::LParen) {
1866 if (getLexer().getKind() != AsmToken::Dollar) {
1867 if (parseMemOffset(IdVal, isParenExpr))
1868 return MatchOperand_ParseFail;
1870 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1871 if (Tok.isNot(AsmToken::LParen)) {
1872 MipsOperand &Mnemonic = static_cast<MipsOperand &>(*Operands[0]);
1873 if (Mnemonic.getToken() == "la") {
1875 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1876 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1877 return MatchOperand_Success;
1879 if (Tok.is(AsmToken::EndOfStatement)) {
1881 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1883 // Zero register assumed, add a memory operand with ZERO as its base.
1884 // "Base" will be managed by k_Memory.
1885 auto Base = MipsOperand::CreateGPRReg(0, getContext().getRegisterInfo(),
1888 MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this));
1889 return MatchOperand_Success;
1891 Error(Parser.getTok().getLoc(), "'(' expected");
1892 return MatchOperand_ParseFail;
1895 Parser.Lex(); // Eat the '(' token.
1898 Res = ParseAnyRegister(Operands);
1899 if (Res != MatchOperand_Success)
1902 if (Parser.getTok().isNot(AsmToken::RParen)) {
1903 Error(Parser.getTok().getLoc(), "')' expected");
1904 return MatchOperand_ParseFail;
1907 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1909 Parser.Lex(); // Eat the ')' token.
1912 IdVal = MCConstantExpr::Create(0, getContext());
1914 // Replace the register operand with the memory operand.
1915 std::unique_ptr<MipsOperand> op(
1916 static_cast<MipsOperand *>(Operands.back().release()));
1917 // Remove the register from the operands.
1918 // "op" will be managed by k_Memory.
1919 Operands.pop_back();
1920 // Add the memory operand.
1921 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1923 if (IdVal->EvaluateAsAbsolute(Imm))
1924 IdVal = MCConstantExpr::Create(Imm, getContext());
1925 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1926 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1930 Operands.push_back(MipsOperand::CreateMem(std::move(op), IdVal, S, E, *this));
1931 return MatchOperand_Success;
1934 bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
1936 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1938 SMLoc S = Parser.getTok().getLoc();
1940 if (Sym->isVariable())
1941 Expr = Sym->getVariableValue();
1944 if (Expr->getKind() == MCExpr::SymbolRef) {
1945 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
1946 const StringRef DefSymbol = Ref->getSymbol().getName();
1947 if (DefSymbol.startswith("$")) {
1948 OperandMatchResultTy ResTy =
1949 MatchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S);
1950 if (ResTy == MatchOperand_Success) {
1953 } else if (ResTy == MatchOperand_ParseFail)
1954 llvm_unreachable("Should never ParseFail");
1957 } else if (Expr->getKind() == MCExpr::Constant) {
1959 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
1961 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc(), *this));
1968 MipsAsmParser::OperandMatchResultTy
1969 MipsAsmParser::MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
1970 StringRef Identifier,
1972 int Index = matchCPURegisterName(Identifier);
1974 Operands.push_back(MipsOperand::CreateGPRReg(
1975 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1976 return MatchOperand_Success;
1979 Index = matchFPURegisterName(Identifier);
1981 Operands.push_back(MipsOperand::CreateFGRReg(
1982 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1983 return MatchOperand_Success;
1986 Index = matchFCCRegisterName(Identifier);
1988 Operands.push_back(MipsOperand::CreateFCCReg(
1989 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1990 return MatchOperand_Success;
1993 Index = matchACRegisterName(Identifier);
1995 Operands.push_back(MipsOperand::CreateACCReg(
1996 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1997 return MatchOperand_Success;
2000 Index = matchMSA128RegisterName(Identifier);
2002 Operands.push_back(MipsOperand::CreateMSA128Reg(
2003 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
2004 return MatchOperand_Success;
2007 Index = matchMSA128CtrlRegisterName(Identifier);
2009 Operands.push_back(MipsOperand::CreateMSACtrlReg(
2010 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
2011 return MatchOperand_Success;
2014 return MatchOperand_NoMatch;
2017 MipsAsmParser::OperandMatchResultTy
2018 MipsAsmParser::MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) {
2019 auto Token = Parser.getLexer().peekTok(false);
2021 if (Token.is(AsmToken::Identifier)) {
2022 DEBUG(dbgs() << ".. identifier\n");
2023 StringRef Identifier = Token.getIdentifier();
2024 OperandMatchResultTy ResTy =
2025 MatchAnyRegisterNameWithoutDollar(Operands, Identifier, S);
2027 } else if (Token.is(AsmToken::Integer)) {
2028 DEBUG(dbgs() << ".. integer\n");
2029 Operands.push_back(MipsOperand::CreateNumericReg(
2030 Token.getIntVal(), getContext().getRegisterInfo(), S, Token.getLoc(),
2032 return MatchOperand_Success;
2035 DEBUG(dbgs() << Parser.getTok().getKind() << "\n");
2037 return MatchOperand_NoMatch;
2040 MipsAsmParser::OperandMatchResultTy
2041 MipsAsmParser::ParseAnyRegister(OperandVector &Operands) {
2042 DEBUG(dbgs() << "ParseAnyRegister\n");
2044 auto Token = Parser.getTok();
2046 SMLoc S = Token.getLoc();
2048 if (Token.isNot(AsmToken::Dollar)) {
2049 DEBUG(dbgs() << ".. !$ -> try sym aliasing\n");
2050 if (Token.is(AsmToken::Identifier)) {
2051 if (searchSymbolAlias(Operands))
2052 return MatchOperand_Success;
2054 DEBUG(dbgs() << ".. !symalias -> NoMatch\n");
2055 return MatchOperand_NoMatch;
2057 DEBUG(dbgs() << ".. $\n");
2059 OperandMatchResultTy ResTy = MatchAnyRegisterWithoutDollar(Operands, S);
2060 if (ResTy == MatchOperand_Success) {
2062 Parser.Lex(); // identifier
2067 MipsAsmParser::OperandMatchResultTy
2068 MipsAsmParser::ParseImm(OperandVector &Operands) {
2069 switch (getLexer().getKind()) {
2071 return MatchOperand_NoMatch;
2072 case AsmToken::LParen:
2073 case AsmToken::Minus:
2074 case AsmToken::Plus:
2075 case AsmToken::Integer:
2076 case AsmToken::Tilde:
2077 case AsmToken::String:
2081 const MCExpr *IdVal;
2082 SMLoc S = Parser.getTok().getLoc();
2083 if (getParser().parseExpression(IdVal))
2084 return MatchOperand_ParseFail;
2086 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2087 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
2088 return MatchOperand_Success;
2091 MipsAsmParser::OperandMatchResultTy
2092 MipsAsmParser::ParseJumpTarget(OperandVector &Operands) {
2093 DEBUG(dbgs() << "ParseJumpTarget\n");
2095 SMLoc S = getLexer().getLoc();
2097 // Integers and expressions are acceptable
2098 OperandMatchResultTy ResTy = ParseImm(Operands);
2099 if (ResTy != MatchOperand_NoMatch)
2102 // Registers are a valid target and have priority over symbols.
2103 ResTy = ParseAnyRegister(Operands);
2104 if (ResTy != MatchOperand_NoMatch)
2107 const MCExpr *Expr = nullptr;
2108 if (Parser.parseExpression(Expr)) {
2109 // We have no way of knowing if a symbol was consumed so we must ParseFail
2110 return MatchOperand_ParseFail;
2113 MipsOperand::CreateImm(Expr, S, getLexer().getLoc(), *this));
2114 return MatchOperand_Success;
2117 MipsAsmParser::OperandMatchResultTy
2118 MipsAsmParser::parseInvNum(OperandVector &Operands) {
2119 const MCExpr *IdVal;
2120 // If the first token is '$' we may have register operand.
2121 if (Parser.getTok().is(AsmToken::Dollar))
2122 return MatchOperand_NoMatch;
2123 SMLoc S = Parser.getTok().getLoc();
2124 if (getParser().parseExpression(IdVal))
2125 return MatchOperand_ParseFail;
2126 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
2127 assert(MCE && "Unexpected MCExpr type.");
2128 int64_t Val = MCE->getValue();
2129 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2130 Operands.push_back(MipsOperand::CreateImm(
2131 MCConstantExpr::Create(0 - Val, getContext()), S, E, *this));
2132 return MatchOperand_Success;
2135 MipsAsmParser::OperandMatchResultTy
2136 MipsAsmParser::ParseLSAImm(OperandVector &Operands) {
2137 switch (getLexer().getKind()) {
2139 return MatchOperand_NoMatch;
2140 case AsmToken::LParen:
2141 case AsmToken::Plus:
2142 case AsmToken::Minus:
2143 case AsmToken::Integer:
2148 SMLoc S = Parser.getTok().getLoc();
2150 if (getParser().parseExpression(Expr))
2151 return MatchOperand_ParseFail;
2154 if (!Expr->EvaluateAsAbsolute(Val)) {
2155 Error(S, "expected immediate value");
2156 return MatchOperand_ParseFail;
2159 // The LSA instruction allows a 2-bit unsigned immediate. For this reason
2160 // and because the CPU always adds one to the immediate field, the allowed
2161 // range becomes 1..4. We'll only check the range here and will deal
2162 // with the addition/subtraction when actually decoding/encoding
2164 if (Val < 1 || Val > 4) {
2165 Error(S, "immediate not in range (1..4)");
2166 return MatchOperand_ParseFail;
2170 MipsOperand::CreateImm(Expr, S, Parser.getTok().getLoc(), *this));
2171 return MatchOperand_Success;
2174 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
2176 MCSymbolRefExpr::VariantKind VK =
2177 StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
2178 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
2179 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
2180 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
2181 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
2182 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
2183 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
2184 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
2185 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
2186 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
2187 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
2188 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
2189 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
2190 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
2191 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
2192 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
2193 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
2194 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
2195 .Case("got_hi", MCSymbolRefExpr::VK_Mips_GOT_HI16)
2196 .Case("got_lo", MCSymbolRefExpr::VK_Mips_GOT_LO16)
2197 .Case("call_hi", MCSymbolRefExpr::VK_Mips_CALL_HI16)
2198 .Case("call_lo", MCSymbolRefExpr::VK_Mips_CALL_LO16)
2199 .Case("higher", MCSymbolRefExpr::VK_Mips_HIGHER)
2200 .Case("highest", MCSymbolRefExpr::VK_Mips_HIGHEST)
2201 .Case("pcrel_hi", MCSymbolRefExpr::VK_Mips_PCREL_HI16)
2202 .Case("pcrel_lo", MCSymbolRefExpr::VK_Mips_PCREL_LO16)
2203 .Default(MCSymbolRefExpr::VK_None);
2205 assert(VK != MCSymbolRefExpr::VK_None);
2210 /// Sometimes (i.e. load/stores) the operand may be followed immediately by
2212 /// ::= '(', register, ')'
2213 /// handle it before we iterate so we don't get tripped up by the lack of
2215 bool MipsAsmParser::ParseParenSuffix(StringRef Name, OperandVector &Operands) {
2216 if (getLexer().is(AsmToken::LParen)) {
2218 MipsOperand::CreateToken("(", getLexer().getLoc(), *this));
2220 if (ParseOperand(Operands, Name)) {
2221 SMLoc Loc = getLexer().getLoc();
2222 Parser.eatToEndOfStatement();
2223 return Error(Loc, "unexpected token in argument list");
2225 if (Parser.getTok().isNot(AsmToken::RParen)) {
2226 SMLoc Loc = getLexer().getLoc();
2227 Parser.eatToEndOfStatement();
2228 return Error(Loc, "unexpected token, expected ')'");
2231 MipsOperand::CreateToken(")", getLexer().getLoc(), *this));
2237 /// Sometimes (i.e. in MSA) the operand may be followed immediately by
2238 /// either one of these.
2239 /// ::= '[', register, ']'
2240 /// ::= '[', integer, ']'
2241 /// handle it before we iterate so we don't get tripped up by the lack of
2243 bool MipsAsmParser::ParseBracketSuffix(StringRef Name,
2244 OperandVector &Operands) {
2245 if (getLexer().is(AsmToken::LBrac)) {
2247 MipsOperand::CreateToken("[", getLexer().getLoc(), *this));
2249 if (ParseOperand(Operands, Name)) {
2250 SMLoc Loc = getLexer().getLoc();
2251 Parser.eatToEndOfStatement();
2252 return Error(Loc, "unexpected token in argument list");
2254 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2255 SMLoc Loc = getLexer().getLoc();
2256 Parser.eatToEndOfStatement();
2257 return Error(Loc, "unexpected token, expected ']'");
2260 MipsOperand::CreateToken("]", getLexer().getLoc(), *this));
2266 bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2267 SMLoc NameLoc, OperandVector &Operands) {
2268 DEBUG(dbgs() << "ParseInstruction\n");
2269 // We have reached first instruction, module directive after
2270 // this is forbidden.
2271 getTargetStreamer().setCanHaveModuleDir(false);
2272 // Check if we have valid mnemonic
2273 if (!mnemonicIsValid(Name, 0)) {
2274 Parser.eatToEndOfStatement();
2275 return Error(NameLoc, "Unknown instruction");
2277 // First operand in MCInst is instruction mnemonic.
2278 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this));
2280 // Read the remaining operands.
2281 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2282 // Read the first operand.
2283 if (ParseOperand(Operands, Name)) {
2284 SMLoc Loc = getLexer().getLoc();
2285 Parser.eatToEndOfStatement();
2286 return Error(Loc, "unexpected token in argument list");
2288 if (getLexer().is(AsmToken::LBrac) && ParseBracketSuffix(Name, Operands))
2290 // AFAIK, parenthesis suffixes are never on the first operand
2292 while (getLexer().is(AsmToken::Comma)) {
2293 Parser.Lex(); // Eat the comma.
2294 // Parse and remember the operand.
2295 if (ParseOperand(Operands, Name)) {
2296 SMLoc Loc = getLexer().getLoc();
2297 Parser.eatToEndOfStatement();
2298 return Error(Loc, "unexpected token in argument list");
2300 // Parse bracket and parenthesis suffixes before we iterate
2301 if (getLexer().is(AsmToken::LBrac)) {
2302 if (ParseBracketSuffix(Name, Operands))
2304 } else if (getLexer().is(AsmToken::LParen) &&
2305 ParseParenSuffix(Name, Operands))
2309 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2310 SMLoc Loc = getLexer().getLoc();
2311 Parser.eatToEndOfStatement();
2312 return Error(Loc, "unexpected token in argument list");
2314 Parser.Lex(); // Consume the EndOfStatement.
2318 bool MipsAsmParser::reportParseError(Twine ErrorMsg) {
2319 SMLoc Loc = getLexer().getLoc();
2320 Parser.eatToEndOfStatement();
2321 return Error(Loc, ErrorMsg);
2324 bool MipsAsmParser::reportParseError(SMLoc Loc, Twine ErrorMsg) {
2325 return Error(Loc, ErrorMsg);
2328 bool MipsAsmParser::parseSetNoAtDirective() {
2329 // Line should look like: ".set noat".
2331 Options.setATReg(0);
2334 // If this is not the end of the statement, report an error.
2335 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2336 reportParseError("unexpected token in statement");
2339 Parser.Lex(); // Consume the EndOfStatement.
2343 bool MipsAsmParser::parseSetAtDirective() {
2344 // Line can be .set at - defaults to $1
2348 if (getLexer().is(AsmToken::EndOfStatement)) {
2349 Options.setATReg(1);
2350 Parser.Lex(); // Consume the EndOfStatement.
2352 } else if (getLexer().is(AsmToken::Equal)) {
2353 getParser().Lex(); // Eat the '='.
2354 if (getLexer().isNot(AsmToken::Dollar)) {
2355 reportParseError("unexpected token in statement");
2358 Parser.Lex(); // Eat the '$'.
2359 const AsmToken &Reg = Parser.getTok();
2360 if (Reg.is(AsmToken::Identifier)) {
2361 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2362 } else if (Reg.is(AsmToken::Integer)) {
2363 AtRegNo = Reg.getIntVal();
2365 reportParseError("unexpected token in statement");
2369 if (AtRegNo < 0 || AtRegNo > 31) {
2370 reportParseError("unexpected token in statement");
2374 if (!Options.setATReg(AtRegNo)) {
2375 reportParseError("unexpected token in statement");
2378 getParser().Lex(); // Eat the register.
2380 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2381 reportParseError("unexpected token in statement");
2384 Parser.Lex(); // Consume the EndOfStatement.
2387 reportParseError("unexpected token in statement");
2392 bool MipsAsmParser::parseSetReorderDirective() {
2394 // If this is not the end of the statement, report an error.
2395 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2396 reportParseError("unexpected token in statement");
2399 Options.setReorder();
2400 getTargetStreamer().emitDirectiveSetReorder();
2401 Parser.Lex(); // Consume the EndOfStatement.
2405 bool MipsAsmParser::parseSetNoReorderDirective() {
2407 // If this is not the end of the statement, report an error.
2408 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2409 reportParseError("unexpected token in statement");
2412 Options.setNoreorder();
2413 getTargetStreamer().emitDirectiveSetNoReorder();
2414 Parser.Lex(); // Consume the EndOfStatement.
2418 bool MipsAsmParser::parseSetMacroDirective() {
2420 // If this is not the end of the statement, report an error.
2421 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2422 reportParseError("unexpected token in statement");
2426 Parser.Lex(); // Consume the EndOfStatement.
2430 bool MipsAsmParser::parseSetNoMacroDirective() {
2432 // If this is not the end of the statement, report an error.
2433 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2434 reportParseError("`noreorder' must be set before `nomacro'");
2437 if (Options.isReorder()) {
2438 reportParseError("`noreorder' must be set before `nomacro'");
2441 Options.setNomacro();
2442 Parser.Lex(); // Consume the EndOfStatement.
2446 bool MipsAsmParser::parseSetNoMips16Directive() {
2448 // If this is not the end of the statement, report an error.
2449 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2450 reportParseError("unexpected token in statement");
2453 // For now do nothing.
2454 Parser.Lex(); // Consume the EndOfStatement.
2458 bool MipsAsmParser::parseSetFpDirective() {
2459 MipsABIFlagsSection::FpABIKind FpAbiVal;
2460 // Line can be: .set fp=32
2463 Parser.Lex(); // Eat fp token
2464 AsmToken Tok = Parser.getTok();
2465 if (Tok.isNot(AsmToken::Equal)) {
2466 reportParseError("unexpected token in statement");
2469 Parser.Lex(); // Eat '=' token.
2470 Tok = Parser.getTok();
2472 if (!parseFpABIValue(FpAbiVal, ".set"))
2475 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2476 reportParseError("unexpected token in statement");
2479 getTargetStreamer().emitDirectiveSetFp(FpAbiVal);
2480 Parser.Lex(); // Consume the EndOfStatement.
2484 bool MipsAsmParser::parseSetAssignment() {
2486 const MCExpr *Value;
2488 if (Parser.parseIdentifier(Name))
2489 reportParseError("expected identifier after .set");
2491 if (getLexer().isNot(AsmToken::Comma))
2492 return reportParseError("unexpected token in .set directive");
2495 if (Parser.parseExpression(Value))
2496 return reportParseError("expected valid expression after comma");
2498 // Check if the Name already exists as a symbol.
2499 MCSymbol *Sym = getContext().LookupSymbol(Name);
2501 return reportParseError("symbol already defined");
2502 Sym = getContext().GetOrCreateSymbol(Name);
2503 Sym->setVariableValue(Value);
2508 bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
2510 if (getLexer().isNot(AsmToken::EndOfStatement))
2511 return reportParseError("unexpected token in .set directive");
2515 llvm_unreachable("Unimplemented feature");
2516 case Mips::FeatureDSP:
2517 setFeatureBits(Mips::FeatureDSP, "dsp");
2518 getTargetStreamer().emitDirectiveSetDsp();
2520 case Mips::FeatureMicroMips:
2521 getTargetStreamer().emitDirectiveSetMicroMips();
2523 case Mips::FeatureMips16:
2524 getTargetStreamer().emitDirectiveSetMips16();
2526 case Mips::FeatureMips32r2:
2527 setFeatureBits(Mips::FeatureMips32r2, "mips32r2");
2528 getTargetStreamer().emitDirectiveSetMips32R2();
2530 case Mips::FeatureMips64:
2531 setFeatureBits(Mips::FeatureMips64, "mips64");
2532 getTargetStreamer().emitDirectiveSetMips64();
2534 case Mips::FeatureMips64r2:
2535 setFeatureBits(Mips::FeatureMips64r2, "mips64r2");
2536 getTargetStreamer().emitDirectiveSetMips64R2();
2542 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
2543 if (getLexer().isNot(AsmToken::Comma)) {
2544 SMLoc Loc = getLexer().getLoc();
2545 Parser.eatToEndOfStatement();
2546 return Error(Loc, ErrorStr);
2549 Parser.Lex(); // Eat the comma.
2553 bool MipsAsmParser::parseDirectiveCPLoad(SMLoc Loc) {
2554 if (Options.isReorder())
2555 Warning(Loc, ".cpload in reorder section");
2557 // FIXME: Warn if cpload is used in Mips16 mode.
2559 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg;
2560 OperandMatchResultTy ResTy = ParseAnyRegister(Reg);
2561 if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
2562 reportParseError("expected register containing function address");
2566 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]);
2567 if (!RegOpnd.isGPRAsmReg()) {
2568 reportParseError(RegOpnd.getStartLoc(), "invalid register");
2572 getTargetStreamer().emitDirectiveCpload(RegOpnd.getGPR32Reg());
2576 bool MipsAsmParser::parseDirectiveCPSetup() {
2579 bool SaveIsReg = true;
2581 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
2582 OperandMatchResultTy ResTy = ParseAnyRegister(TmpReg);
2583 if (ResTy == MatchOperand_NoMatch) {
2584 reportParseError("expected register containing function address");
2585 Parser.eatToEndOfStatement();
2589 MipsOperand &FuncRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
2590 if (!FuncRegOpnd.isGPRAsmReg()) {
2591 reportParseError(FuncRegOpnd.getStartLoc(), "invalid register");
2592 Parser.eatToEndOfStatement();
2596 FuncReg = FuncRegOpnd.getGPR32Reg();
2599 if (!eatComma("expected comma parsing directive"))
2602 ResTy = ParseAnyRegister(TmpReg);
2603 if (ResTy == MatchOperand_NoMatch) {
2604 const AsmToken &Tok = Parser.getTok();
2605 if (Tok.is(AsmToken::Integer)) {
2606 Save = Tok.getIntVal();
2610 reportParseError("expected save register or stack offset");
2611 Parser.eatToEndOfStatement();
2615 MipsOperand &SaveOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
2616 if (!SaveOpnd.isGPRAsmReg()) {
2617 reportParseError(SaveOpnd.getStartLoc(), "invalid register");
2618 Parser.eatToEndOfStatement();
2621 Save = SaveOpnd.getGPR32Reg();
2624 if (!eatComma("expected comma parsing directive"))
2628 if (Parser.parseIdentifier(Name))
2629 reportParseError("expected identifier");
2630 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2632 getTargetStreamer().emitDirectiveCpsetup(FuncReg, Save, *Sym, SaveIsReg);
2636 bool MipsAsmParser::parseDirectiveNaN() {
2637 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2638 const AsmToken &Tok = Parser.getTok();
2640 if (Tok.getString() == "2008") {
2642 getTargetStreamer().emitDirectiveNaN2008();
2644 } else if (Tok.getString() == "legacy") {
2646 getTargetStreamer().emitDirectiveNaNLegacy();
2650 // If we don't recognize the option passed to the .nan
2651 // directive (e.g. no option or unknown option), emit an error.
2652 reportParseError("invalid option in .nan directive");
2656 bool MipsAsmParser::parseDirectiveSet() {
2658 // Get the next token.
2659 const AsmToken &Tok = Parser.getTok();
2661 if (Tok.getString() == "noat") {
2662 return parseSetNoAtDirective();
2663 } else if (Tok.getString() == "at") {
2664 return parseSetAtDirective();
2665 } else if (Tok.getString() == "fp") {
2666 return parseSetFpDirective();
2667 } else if (Tok.getString() == "reorder") {
2668 return parseSetReorderDirective();
2669 } else if (Tok.getString() == "noreorder") {
2670 return parseSetNoReorderDirective();
2671 } else if (Tok.getString() == "macro") {
2672 return parseSetMacroDirective();
2673 } else if (Tok.getString() == "nomacro") {
2674 return parseSetNoMacroDirective();
2675 } else if (Tok.getString() == "mips16") {
2676 return parseSetFeature(Mips::FeatureMips16);
2677 } else if (Tok.getString() == "nomips16") {
2678 return parseSetNoMips16Directive();
2679 } else if (Tok.getString() == "nomicromips") {
2680 getTargetStreamer().emitDirectiveSetNoMicroMips();
2681 Parser.eatToEndOfStatement();
2683 } else if (Tok.getString() == "micromips") {
2684 return parseSetFeature(Mips::FeatureMicroMips);
2685 } else if (Tok.getString() == "mips32r2") {
2686 return parseSetFeature(Mips::FeatureMips32r2);
2687 } else if (Tok.getString() == "mips64") {
2688 return parseSetFeature(Mips::FeatureMips64);
2689 } else if (Tok.getString() == "mips64r2") {
2690 return parseSetFeature(Mips::FeatureMips64r2);
2691 } else if (Tok.getString() == "dsp") {
2692 return parseSetFeature(Mips::FeatureDSP);
2694 // It is just an identifier, look for an assignment.
2695 parseSetAssignment();
2702 /// parseDataDirective
2703 /// ::= .word [ expression (, expression)* ]
2704 bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) {
2705 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2707 const MCExpr *Value;
2708 if (getParser().parseExpression(Value))
2711 getParser().getStreamer().EmitValue(Value, Size);
2713 if (getLexer().is(AsmToken::EndOfStatement))
2716 // FIXME: Improve diagnostic.
2717 if (getLexer().isNot(AsmToken::Comma))
2718 return Error(L, "unexpected token in directive");
2727 /// parseDirectiveGpWord
2728 /// ::= .gpword local_sym
2729 bool MipsAsmParser::parseDirectiveGpWord() {
2730 const MCExpr *Value;
2731 // EmitGPRel32Value requires an expression, so we are using base class
2732 // method to evaluate the expression.
2733 if (getParser().parseExpression(Value))
2735 getParser().getStreamer().EmitGPRel32Value(Value);
2737 if (getLexer().isNot(AsmToken::EndOfStatement))
2738 return Error(getLexer().getLoc(), "unexpected token in directive");
2739 Parser.Lex(); // Eat EndOfStatement token.
2743 /// parseDirectiveGpDWord
2744 /// ::= .gpdword local_sym
2745 bool MipsAsmParser::parseDirectiveGpDWord() {
2746 const MCExpr *Value;
2747 // EmitGPRel64Value requires an expression, so we are using base class
2748 // method to evaluate the expression.
2749 if (getParser().parseExpression(Value))
2751 getParser().getStreamer().EmitGPRel64Value(Value);
2753 if (getLexer().isNot(AsmToken::EndOfStatement))
2754 return Error(getLexer().getLoc(), "unexpected token in directive");
2755 Parser.Lex(); // Eat EndOfStatement token.
2759 bool MipsAsmParser::parseDirectiveOption() {
2760 // Get the option token.
2761 AsmToken Tok = Parser.getTok();
2762 // At the moment only identifiers are supported.
2763 if (Tok.isNot(AsmToken::Identifier)) {
2764 Error(Parser.getTok().getLoc(), "unexpected token in .option directive");
2765 Parser.eatToEndOfStatement();
2769 StringRef Option = Tok.getIdentifier();
2771 if (Option == "pic0") {
2772 getTargetStreamer().emitDirectiveOptionPic0();
2774 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2775 Error(Parser.getTok().getLoc(),
2776 "unexpected token in .option pic0 directive");
2777 Parser.eatToEndOfStatement();
2782 if (Option == "pic2") {
2783 getTargetStreamer().emitDirectiveOptionPic2();
2785 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2786 Error(Parser.getTok().getLoc(),
2787 "unexpected token in .option pic2 directive");
2788 Parser.eatToEndOfStatement();
2794 Warning(Parser.getTok().getLoc(), "unknown option in .option directive");
2795 Parser.eatToEndOfStatement();
2799 /// parseDirectiveModule
2800 /// ::= .module oddspreg
2801 /// ::= .module nooddspreg
2802 /// ::= .module fp=value
2803 bool MipsAsmParser::parseDirectiveModule() {
2804 MCAsmLexer &Lexer = getLexer();
2805 SMLoc L = Lexer.getLoc();
2807 if (!getTargetStreamer().getCanHaveModuleDir()) {
2808 // TODO : get a better message.
2809 reportParseError(".module directive must appear before any code");
2813 if (Lexer.is(AsmToken::Identifier)) {
2814 StringRef Option = Parser.getTok().getString();
2817 if (Option == "oddspreg") {
2818 getTargetStreamer().emitDirectiveModuleOddSPReg(true, isABI_O32());
2819 clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
2821 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2822 reportParseError("Expected end of statement");
2827 } else if (Option == "nooddspreg") {
2829 Error(L, "'.module nooddspreg' requires the O32 ABI");
2833 getTargetStreamer().emitDirectiveModuleOddSPReg(false, isABI_O32());
2834 setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
2836 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2837 reportParseError("Expected end of statement");
2842 } else if (Option == "fp") {
2843 return parseDirectiveModuleFP();
2846 return Error(L, "'" + Twine(Option) + "' is not a valid .module option.");
2852 /// parseDirectiveModuleFP
2856 bool MipsAsmParser::parseDirectiveModuleFP() {
2857 MCAsmLexer &Lexer = getLexer();
2859 if (Lexer.isNot(AsmToken::Equal)) {
2860 reportParseError("unexpected token in statement");
2863 Parser.Lex(); // Eat '=' token.
2865 MipsABIFlagsSection::FpABIKind FpABI;
2866 if (!parseFpABIValue(FpABI, ".module"))
2869 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2870 reportParseError("unexpected token in statement");
2874 // Emit appropriate flags.
2875 getTargetStreamer().emitDirectiveModuleFP(FpABI, isABI_O32());
2876 Parser.Lex(); // Consume the EndOfStatement.
2880 bool MipsAsmParser::parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
2881 StringRef Directive) {
2882 MCAsmLexer &Lexer = getLexer();
2884 if (Lexer.is(AsmToken::Identifier)) {
2885 StringRef Value = Parser.getTok().getString();
2888 if (Value != "xx") {
2889 reportParseError("unsupported value, expected 'xx', '32' or '64'");
2894 reportParseError("'" + Directive + " fp=xx' requires the O32 ABI");
2898 FpABI = MipsABIFlagsSection::FpABIKind::XX;
2902 if (Lexer.is(AsmToken::Integer)) {
2903 unsigned Value = Parser.getTok().getIntVal();
2906 if (Value != 32 && Value != 64) {
2907 reportParseError("unsupported value, expected 'xx', '32' or '64'");
2913 reportParseError("'" + Directive + " fp=32' requires the O32 ABI");
2917 FpABI = MipsABIFlagsSection::FpABIKind::S32;
2919 FpABI = MipsABIFlagsSection::FpABIKind::S64;
2927 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2928 StringRef IDVal = DirectiveID.getString();
2930 if (IDVal == ".cpload")
2931 return parseDirectiveCPLoad(DirectiveID.getLoc());
2932 if (IDVal == ".dword") {
2933 parseDataDirective(8, DirectiveID.getLoc());
2937 if (IDVal == ".ent") {
2938 // Ignore this directive for now.
2943 if (IDVal == ".end") {
2944 // Ignore this directive for now.
2949 if (IDVal == ".frame") {
2950 // Ignore this directive for now.
2951 Parser.eatToEndOfStatement();
2955 if (IDVal == ".set") {
2956 return parseDirectiveSet();
2959 if (IDVal == ".fmask") {
2960 // Ignore this directive for now.
2961 Parser.eatToEndOfStatement();
2965 if (IDVal == ".mask") {
2966 // Ignore this directive for now.
2967 Parser.eatToEndOfStatement();
2971 if (IDVal == ".nan")
2972 return parseDirectiveNaN();
2974 if (IDVal == ".gpword") {
2975 parseDirectiveGpWord();
2979 if (IDVal == ".gpdword") {
2980 parseDirectiveGpDWord();
2984 if (IDVal == ".word") {
2985 parseDataDirective(4, DirectiveID.getLoc());
2989 if (IDVal == ".option")
2990 return parseDirectiveOption();
2992 if (IDVal == ".abicalls") {
2993 getTargetStreamer().emitDirectiveAbiCalls();
2994 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2995 Error(Parser.getTok().getLoc(), "unexpected token in directive");
2997 Parser.eatToEndOfStatement();
3002 if (IDVal == ".cpsetup")
3003 return parseDirectiveCPSetup();
3005 if (IDVal == ".module")
3006 return parseDirectiveModule();
3011 extern "C" void LLVMInitializeMipsAsmParser() {
3012 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
3013 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
3014 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
3015 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
3018 #define GET_REGISTER_MATCHER
3019 #define GET_MATCHER_IMPLEMENTATION
3020 #include "MipsGenAsmMatcher.inc"