1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCParser/MCAsmLexer.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/MC/MCTargetAsmParser.h"
22 #include "llvm/Support/TargetRegistry.h"
27 class MipsAssemblerOptions {
29 MipsAssemblerOptions():
30 aTReg(1), reorder(true), macro(true) {
33 unsigned getATRegNum() {return aTReg;}
34 bool setATReg(unsigned Reg);
36 bool isReorder() {return reorder;}
37 void setReorder() {reorder = true;}
38 void setNoreorder() {reorder = false;}
40 bool isMacro() {return macro;}
41 void setMacro() {macro = true;}
42 void setNomacro() {macro = false;}
52 class MipsAsmParser : public MCTargetAsmParser {
64 MipsAssemblerOptions Options;
67 #define GET_ASSEMBLER_HEADER
68 #include "MipsGenAsmMatcher.inc"
70 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
71 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
72 MCStreamer &Out, unsigned &ErrorInfo,
73 bool MatchingInlineAsm);
75 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
77 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
79 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
81 bool parseMathOperation(StringRef Name, SMLoc NameLoc,
82 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
84 bool ParseDirective(AsmToken DirectiveID);
86 MipsAsmParser::OperandMatchResultTy
87 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
89 MipsAsmParser::OperandMatchResultTy
90 parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
92 MipsAsmParser::OperandMatchResultTy
93 parseCPU64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
95 MipsAsmParser::OperandMatchResultTy
96 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
98 MipsAsmParser::OperandMatchResultTy
99 parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
101 MipsAsmParser::OperandMatchResultTy
102 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
104 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
107 int tryParseRegister(bool is64BitReg);
109 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
112 bool needsExpansion(MCInst &Inst);
114 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
115 SmallVectorImpl<MCInst> &Instructions);
116 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
117 SmallVectorImpl<MCInst> &Instructions);
118 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
119 SmallVectorImpl<MCInst> &Instructions);
120 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
121 SmallVectorImpl<MCInst> &Instructions);
122 bool reportParseError(StringRef ErrorMsg);
124 bool parseMemOffset(const MCExpr *&Res);
125 bool parseRelocOperand(const MCExpr *&Res);
127 bool parseDirectiveSet();
129 bool parseSetAtDirective();
130 bool parseSetNoAtDirective();
131 bool parseSetMacroDirective();
132 bool parseSetNoMacroDirective();
133 bool parseSetReorderDirective();
134 bool parseSetNoReorderDirective();
136 bool parseDirectiveWord(unsigned Size, SMLoc L);
138 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
140 bool isMips64() const {
141 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
144 bool isFP64() const {
145 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
148 int matchRegisterName(StringRef Symbol, bool is64BitReg);
150 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
152 void setFpFormat(FpFormatTy Format) {
156 void setDefaultFpFormat();
158 void setFpFormat(StringRef Format);
160 FpFormatTy getFpFormat() {return FpFormat;}
162 bool requestsDoubleOperand(StringRef Mnemonic);
164 unsigned getReg(int RC,int RegNo);
168 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
169 : MCTargetAsmParser(), STI(sti), Parser(parser) {
170 // Initialize the set of available features.
171 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
174 MCAsmParser &getParser() const { return Parser; }
175 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
182 /// MipsOperand - Instances of this class represent a parsed Mips machine
184 class MipsOperand : public MCParsedAsmOperand {
210 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
233 SMLoc StartLoc, EndLoc;
236 void addRegOperands(MCInst &Inst, unsigned N) const {
237 assert(N == 1 && "Invalid number of operands!");
238 Inst.addOperand(MCOperand::CreateReg(getReg()));
241 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
242 // Add as immediate when possible. Null MCExpr = 0.
244 Inst.addOperand(MCOperand::CreateImm(0));
245 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
246 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
248 Inst.addOperand(MCOperand::CreateExpr(Expr));
251 void addImmOperands(MCInst &Inst, unsigned N) const {
252 assert(N == 1 && "Invalid number of operands!");
253 const MCExpr *Expr = getImm();
257 void addMemOperands(MCInst &Inst, unsigned N) const {
258 assert(N == 2 && "Invalid number of operands!");
260 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
262 const MCExpr *Expr = getMemOff();
266 bool isReg() const { return Kind == k_Register; }
267 bool isImm() const { return Kind == k_Immediate; }
268 bool isToken() const { return Kind == k_Token; }
269 bool isMem() const { return Kind == k_Memory; }
271 StringRef getToken() const {
272 assert(Kind == k_Token && "Invalid access!");
273 return StringRef(Tok.Data, Tok.Length);
276 unsigned getReg() const {
277 assert((Kind == k_Register) && "Invalid access!");
281 void setRegKind(RegisterKind RegKind) {
282 assert((Kind == k_Register) && "Invalid access!");
286 const MCExpr *getImm() const {
287 assert((Kind == k_Immediate) && "Invalid access!");
291 unsigned getMemBase() const {
292 assert((Kind == k_Memory) && "Invalid access!");
296 const MCExpr *getMemOff() const {
297 assert((Kind == k_Memory) && "Invalid access!");
301 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
302 MipsOperand *Op = new MipsOperand(k_Token);
303 Op->Tok.Data = Str.data();
304 Op->Tok.Length = Str.size();
310 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
311 MipsOperand *Op = new MipsOperand(k_Register);
312 Op->Reg.RegNum = RegNum;
318 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
319 MipsOperand *Op = new MipsOperand(k_Immediate);
326 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
328 MipsOperand *Op = new MipsOperand(k_Memory);
336 bool isCPURegsAsm() const {
337 return Kind == k_Register && Reg.Kind == Kind_CPURegs;
339 void addCPURegsAsmOperands(MCInst &Inst, unsigned N) const {
340 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
343 bool isCPU64RegsAsm() const {
344 return Kind == k_Register && Reg.Kind == Kind_CPU64Regs;
346 void addCPU64RegsAsmOperands(MCInst &Inst, unsigned N) const {
347 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
350 bool isHWRegsAsm() const {
351 assert((Kind == k_Register) && "Invalid access!");
352 return Reg.Kind == Kind_HWRegs;
354 void addHWRegsAsmOperands(MCInst &Inst, unsigned N) const {
355 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
358 bool isHW64RegsAsm() const {
359 assert((Kind == k_Register) && "Invalid access!");
360 return Reg.Kind == Kind_HW64Regs;
362 void addHW64RegsAsmOperands(MCInst &Inst, unsigned N) const {
363 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
366 void addCCRAsmOperands(MCInst &Inst, unsigned N) const {
367 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
370 bool isCCRAsm() const {
371 assert((Kind == k_Register) && "Invalid access!");
372 return Reg.Kind == Kind_CCRRegs;
375 /// getStartLoc - Get the location of the first token of this operand.
376 SMLoc getStartLoc() const { return StartLoc; }
377 /// getEndLoc - Get the location of the last token of this operand.
378 SMLoc getEndLoc() const { return EndLoc; }
380 virtual void print(raw_ostream &OS) const {
381 llvm_unreachable("unimplemented!");
386 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
388 switch(Inst.getOpcode()) {
389 case Mips::LoadImm32Reg:
390 case Mips::LoadAddr32Imm:
391 case Mips::LoadAddr32Reg:
398 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
399 SmallVectorImpl<MCInst> &Instructions){
400 switch(Inst.getOpcode()) {
401 case Mips::LoadImm32Reg:
402 return expandLoadImm(Inst, IDLoc, Instructions);
403 case Mips::LoadAddr32Imm:
404 return expandLoadAddressImm(Inst,IDLoc,Instructions);
405 case Mips::LoadAddr32Reg:
406 return expandLoadAddressReg(Inst,IDLoc,Instructions);
410 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
411 SmallVectorImpl<MCInst> &Instructions){
413 const MCOperand &ImmOp = Inst.getOperand(1);
414 assert(ImmOp.isImm() && "expected immediate operand kind");
415 const MCOperand &RegOp = Inst.getOperand(0);
416 assert(RegOp.isReg() && "expected register operand kind");
418 int ImmValue = ImmOp.getImm();
419 tmpInst.setLoc(IDLoc);
420 if ( 0 <= ImmValue && ImmValue <= 65535) {
421 // for 0 <= j <= 65535.
422 // li d,j => ori d,$zero,j
423 tmpInst.setOpcode(Mips::ORi);
424 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
426 MCOperand::CreateReg(Mips::ZERO));
427 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
428 Instructions.push_back(tmpInst);
429 } else if ( ImmValue < 0 && ImmValue >= -32768) {
430 // for -32768 <= j < 0.
431 // li d,j => addiu d,$zero,j
432 tmpInst.setOpcode(Mips::ADDiu);
433 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
435 MCOperand::CreateReg(Mips::ZERO));
436 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
437 Instructions.push_back(tmpInst);
439 // for any other value of j that is representable as a 32-bit integer.
440 // li d,j => lui d,hi16(j)
442 tmpInst.setOpcode(Mips::LUi);
443 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
444 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
445 Instructions.push_back(tmpInst);
447 tmpInst.setOpcode(Mips::ORi);
448 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
449 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
450 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
451 tmpInst.setLoc(IDLoc);
452 Instructions.push_back(tmpInst);
456 void MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
457 SmallVectorImpl<MCInst> &Instructions){
459 const MCOperand &ImmOp = Inst.getOperand(2);
460 assert(ImmOp.isImm() && "expected immediate operand kind");
461 const MCOperand &SrcRegOp = Inst.getOperand(1);
462 assert(SrcRegOp.isReg() && "expected register operand kind");
463 const MCOperand &DstRegOp = Inst.getOperand(0);
464 assert(DstRegOp.isReg() && "expected register operand kind");
465 int ImmValue = ImmOp.getImm();
466 if ( -32768 <= ImmValue && ImmValue <= 65535) {
467 //for -32768 <= j <= 65535.
468 //la d,j(s) => addiu d,s,j
469 tmpInst.setOpcode(Mips::ADDiu);
470 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
471 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
472 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
473 Instructions.push_back(tmpInst);
475 //for any other value of j that is representable as a 32-bit integer.
476 //la d,j(s) => lui d,hi16(j)
479 tmpInst.setOpcode(Mips::LUi);
480 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
481 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
482 Instructions.push_back(tmpInst);
484 tmpInst.setOpcode(Mips::ORi);
485 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
486 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
487 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
488 Instructions.push_back(tmpInst);
490 tmpInst.setOpcode(Mips::ADDu);
491 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
492 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
493 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
494 Instructions.push_back(tmpInst);
498 void MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
499 SmallVectorImpl<MCInst> &Instructions){
501 const MCOperand &ImmOp = Inst.getOperand(1);
502 assert(ImmOp.isImm() && "expected immediate operand kind");
503 const MCOperand &RegOp = Inst.getOperand(0);
504 assert(RegOp.isReg() && "expected register operand kind");
505 int ImmValue = ImmOp.getImm();
506 if ( -32768 <= ImmValue && ImmValue <= 65535) {
507 //for -32768 <= j <= 65535.
508 //la d,j => addiu d,$zero,j
509 tmpInst.setOpcode(Mips::ADDiu);
510 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
512 MCOperand::CreateReg(Mips::ZERO));
513 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
514 Instructions.push_back(tmpInst);
516 //for any other value of j that is representable as a 32-bit integer.
517 //la d,j => lui d,hi16(j)
519 tmpInst.setOpcode(Mips::LUi);
520 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
521 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
522 Instructions.push_back(tmpInst);
524 tmpInst.setOpcode(Mips::ORi);
525 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
526 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
527 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
528 Instructions.push_back(tmpInst);
533 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
534 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
535 MCStreamer &Out, unsigned &ErrorInfo,
536 bool MatchingInlineAsm) {
538 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
541 switch (MatchResult) {
543 case Match_Success: {
544 if (needsExpansion(Inst)) {
545 SmallVector<MCInst, 4> Instructions;
546 expandInstruction(Inst, IDLoc, Instructions);
547 for(unsigned i =0; i < Instructions.size(); i++){
548 Out.EmitInstruction(Instructions[i]);
552 Out.EmitInstruction(Inst);
556 case Match_MissingFeature:
557 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
559 case Match_InvalidOperand: {
560 SMLoc ErrorLoc = IDLoc;
561 if (ErrorInfo != ~0U) {
562 if (ErrorInfo >= Operands.size())
563 return Error(IDLoc, "too few operands for instruction");
565 ErrorLoc = ((MipsOperand*)Operands[ErrorInfo])->getStartLoc();
566 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
569 return Error(ErrorLoc, "invalid operand for instruction");
571 case Match_MnemonicFail:
572 return Error(IDLoc, "invalid instruction");
577 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
581 CC = StringSwitch<unsigned>(Name)
582 .Case("zero", Mips::ZERO)
583 .Case("a0", Mips::A0)
584 .Case("a1", Mips::A1)
585 .Case("a2", Mips::A2)
586 .Case("a3", Mips::A3)
587 .Case("v0", Mips::V0)
588 .Case("v1", Mips::V1)
589 .Case("s0", Mips::S0)
590 .Case("s1", Mips::S1)
591 .Case("s2", Mips::S2)
592 .Case("s3", Mips::S3)
593 .Case("s4", Mips::S4)
594 .Case("s5", Mips::S5)
595 .Case("s6", Mips::S6)
596 .Case("s7", Mips::S7)
597 .Case("k0", Mips::K0)
598 .Case("k1", Mips::K1)
599 .Case("sp", Mips::SP)
600 .Case("fp", Mips::FP)
601 .Case("gp", Mips::GP)
602 .Case("ra", Mips::RA)
603 .Case("t0", Mips::T0)
604 .Case("t1", Mips::T1)
605 .Case("t2", Mips::T2)
606 .Case("t3", Mips::T3)
607 .Case("t4", Mips::T4)
608 .Case("t5", Mips::T5)
609 .Case("t6", Mips::T6)
610 .Case("t7", Mips::T7)
611 .Case("t8", Mips::T8)
612 .Case("t9", Mips::T9)
613 .Case("at", Mips::AT)
614 .Case("fcc0", Mips::FCC0)
617 CC = StringSwitch<unsigned>(Name)
618 .Case("zero", Mips::ZERO_64)
619 .Case("at", Mips::AT_64)
620 .Case("v0", Mips::V0_64)
621 .Case("v1", Mips::V1_64)
622 .Case("a0", Mips::A0_64)
623 .Case("a1", Mips::A1_64)
624 .Case("a2", Mips::A2_64)
625 .Case("a3", Mips::A3_64)
626 .Case("a4", Mips::T0_64)
627 .Case("a5", Mips::T1_64)
628 .Case("a6", Mips::T2_64)
629 .Case("a7", Mips::T3_64)
630 .Case("t4", Mips::T4_64)
631 .Case("t5", Mips::T5_64)
632 .Case("t6", Mips::T6_64)
633 .Case("t7", Mips::T7_64)
634 .Case("s0", Mips::S0_64)
635 .Case("s1", Mips::S1_64)
636 .Case("s2", Mips::S2_64)
637 .Case("s3", Mips::S3_64)
638 .Case("s4", Mips::S4_64)
639 .Case("s5", Mips::S5_64)
640 .Case("s6", Mips::S6_64)
641 .Case("s7", Mips::S7_64)
642 .Case("t8", Mips::T8_64)
643 .Case("t9", Mips::T9_64)
644 .Case("kt0", Mips::K0_64)
645 .Case("kt1", Mips::K1_64)
646 .Case("gp", Mips::GP_64)
647 .Case("sp", Mips::SP_64)
648 .Case("fp", Mips::FP_64)
649 .Case("s8", Mips::FP_64)
650 .Case("ra", Mips::RA_64)
656 if (Name[0] == 'f') {
657 StringRef NumString = Name.substr(1);
659 if( NumString.getAsInteger(10, IntVal))
660 return -1; // not integer
664 FpFormatTy Format = getFpFormat();
666 if (Format == FP_FORMAT_S || Format == FP_FORMAT_W)
667 return getReg(Mips::FGR32RegClassID, IntVal);
668 if (Format == FP_FORMAT_D) {
670 return getReg(Mips::FGR64RegClassID, IntVal);
672 // only even numbers available as register pairs
673 if (( IntVal > 31) || (IntVal%2 != 0))
675 return getReg(Mips::AFGR64RegClassID, IntVal/2);
681 void MipsAsmParser::setDefaultFpFormat() {
683 if (isMips64() || isFP64())
684 FpFormat = FP_FORMAT_D;
686 FpFormat = FP_FORMAT_S;
689 bool MipsAsmParser::requestsDoubleOperand(StringRef Mnemonic){
691 bool IsDouble = StringSwitch<bool>(Mnemonic.lower())
700 void MipsAsmParser::setFpFormat(StringRef Format) {
702 FpFormat = StringSwitch<FpFormatTy>(Format.lower())
703 .Case(".s", FP_FORMAT_S)
704 .Case(".d", FP_FORMAT_D)
705 .Case(".l", FP_FORMAT_L)
706 .Case(".w", FP_FORMAT_W)
707 .Default(FP_FORMAT_NONE);
710 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
718 unsigned MipsAsmParser::getATReg() {
719 unsigned Reg = Options.getATRegNum();
721 return getReg(Mips::CPU64RegsRegClassID,Reg);
723 return getReg(Mips::CPURegsRegClassID,Reg);
726 unsigned MipsAsmParser::getReg(int RC,int RegNo) {
727 return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
730 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
735 return getReg(RegClass, RegNum);
738 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
739 const AsmToken &Tok = Parser.getTok();
742 if (Tok.is(AsmToken::Identifier)) {
743 std::string lowerCase = Tok.getString().lower();
744 RegNum = matchRegisterName(lowerCase, is64BitReg);
745 } else if (Tok.is(AsmToken::Integer))
746 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
747 is64BitReg ? Mips::CPU64RegsRegClassID
748 : Mips::CPURegsRegClassID);
753 tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
756 SMLoc S = Parser.getTok().getLoc();
759 RegNo = tryParseRegister(is64BitReg);
763 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
764 Parser.getTok().getLoc()));
765 Parser.Lex(); // Eat register token.
769 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
770 StringRef Mnemonic) {
771 // Check if the current operand has a custom associated parser, if so, try to
772 // custom parse the operand, or fallback to the general approach.
773 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
774 if (ResTy == MatchOperand_Success)
776 // If there wasn't a custom match, try the generic matcher below. Otherwise,
777 // there was a match, but an error occurred, in which case, just return that
778 // the operand parsing failed.
779 if (ResTy == MatchOperand_ParseFail)
782 switch (getLexer().getKind()) {
784 Error(Parser.getTok().getLoc(), "unexpected token in operand");
786 case AsmToken::Dollar: {
788 SMLoc S = Parser.getTok().getLoc();
789 Parser.Lex(); // Eat dollar token.
790 // parse register operand
791 if (!tryParseRegisterOperand(Operands, isMips64())) {
792 if (getLexer().is(AsmToken::LParen)) {
793 // check if it is indexed addressing operand
794 Operands.push_back(MipsOperand::CreateToken("(", S));
795 Parser.Lex(); // eat parenthesis
796 if (getLexer().isNot(AsmToken::Dollar))
799 Parser.Lex(); // eat dollar
800 if (tryParseRegisterOperand(Operands, isMips64()))
803 if (!getLexer().is(AsmToken::RParen))
806 S = Parser.getTok().getLoc();
807 Operands.push_back(MipsOperand::CreateToken(")", S));
812 // maybe it is a symbol reference
813 StringRef Identifier;
814 if (Parser.ParseIdentifier(Identifier))
817 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
819 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
821 // Otherwise create a symbol ref.
822 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
825 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
828 case AsmToken::Identifier:
829 case AsmToken::LParen:
830 case AsmToken::Minus:
832 case AsmToken::Integer:
833 case AsmToken::String: {
834 // quoted label names
836 SMLoc S = Parser.getTok().getLoc();
837 if (getParser().ParseExpression(IdVal))
839 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
840 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
843 case AsmToken::Percent: {
844 // it is a symbol reference or constant expression
846 SMLoc S = Parser.getTok().getLoc(); // start location of the operand
847 if (parseRelocOperand(IdVal))
850 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
852 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
854 } // case AsmToken::Percent
855 } // switch(getLexer().getKind())
859 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
861 Parser.Lex(); // eat % token
862 const AsmToken &Tok = Parser.getTok(); // get next token, operation
863 if (Tok.isNot(AsmToken::Identifier))
866 std::string Str = Tok.getIdentifier().str();
868 Parser.Lex(); // eat identifier
869 // now make expression from the rest of the operand
873 if (getLexer().getKind() == AsmToken::LParen) {
875 Parser.Lex(); // eat '(' token
876 if (getLexer().getKind() == AsmToken::Percent) {
877 Parser.Lex(); // eat % token
878 const AsmToken &nextTok = Parser.getTok();
879 if (nextTok.isNot(AsmToken::Identifier))
882 Str += nextTok.getIdentifier();
883 Parser.Lex(); // eat identifier
884 if (getLexer().getKind() != AsmToken::LParen)
889 if (getParser().ParseParenExpression(IdVal,EndLoc))
892 while (getLexer().getKind() == AsmToken::RParen)
893 Parser.Lex(); // eat ')' token
896 return true; // parenthesis must follow reloc operand
898 // Check the type of the expression
899 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal)) {
900 // it's a constant, evaluate lo or hi value
901 int Val = MCE->getValue();
904 } else if (Str == "hi") {
905 Val = (Val & 0xffff0000) >> 16;
907 Res = MCConstantExpr::Create(Val, getContext());
911 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(IdVal)) {
912 // it's a symbol, create symbolic expression from symbol
913 StringRef Symbol = MSRE->getSymbol().getName();
914 MCSymbolRefExpr::VariantKind VK = getVariantKind(Str);
915 Res = MCSymbolRefExpr::Create(Symbol,VK,getContext());
921 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
924 StartLoc = Parser.getTok().getLoc();
925 RegNo = tryParseRegister(isMips64());
926 EndLoc = Parser.getTok().getLoc();
927 return (RegNo == (unsigned)-1);
930 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res) {
934 switch(getLexer().getKind()) {
937 case AsmToken::Integer:
938 case AsmToken::Minus:
940 return (getParser().ParseExpression(Res));
941 case AsmToken::Percent:
942 return parseRelocOperand(Res);
943 case AsmToken::LParen:
944 return false; // it's probably assuming 0
949 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
950 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
952 const MCExpr *IdVal = 0;
954 // first operand is the offset
955 S = Parser.getTok().getLoc();
957 if (parseMemOffset(IdVal))
958 return MatchOperand_ParseFail;
960 const AsmToken &Tok = Parser.getTok(); // get next token
961 if (Tok.isNot(AsmToken::LParen)) {
962 MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
963 if (Mnemonic->getToken() == "la") {
964 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() -1);
965 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
966 return MatchOperand_Success;
968 Error(Parser.getTok().getLoc(), "'(' expected");
969 return MatchOperand_ParseFail;
972 Parser.Lex(); // Eat '(' token.
974 const AsmToken &Tok1 = Parser.getTok(); // get next token
975 if (Tok1.is(AsmToken::Dollar)) {
976 Parser.Lex(); // Eat '$' token.
977 if (tryParseRegisterOperand(Operands, isMips64())) {
978 Error(Parser.getTok().getLoc(), "unexpected token in operand");
979 return MatchOperand_ParseFail;
983 Error(Parser.getTok().getLoc(), "unexpected token in operand");
984 return MatchOperand_ParseFail;
987 const AsmToken &Tok2 = Parser.getTok(); // get next token
988 if (Tok2.isNot(AsmToken::RParen)) {
989 Error(Parser.getTok().getLoc(), "')' expected");
990 return MatchOperand_ParseFail;
993 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
995 Parser.Lex(); // Eat ')' token.
998 IdVal = MCConstantExpr::Create(0, getContext());
1000 // now replace register operand with the mem operand
1001 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1002 int RegNo = op->getReg();
1003 // remove register from operands
1004 Operands.pop_back();
1005 // and add memory operand
1006 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1008 return MatchOperand_Success;
1011 MipsAsmParser::OperandMatchResultTy
1012 MipsAsmParser::parseCPU64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1015 return MatchOperand_NoMatch;
1016 // if the first token is not '$' we have an error
1017 if (Parser.getTok().isNot(AsmToken::Dollar))
1018 return MatchOperand_NoMatch;
1020 Parser.Lex(); // Eat $
1021 if(!tryParseRegisterOperand(Operands, true)) {
1022 // set the proper register kind
1023 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1024 op->setRegKind(MipsOperand::Kind_CPU64Regs);
1025 return MatchOperand_Success;
1027 return MatchOperand_NoMatch;
1030 MipsAsmParser::OperandMatchResultTy
1031 MipsAsmParser::parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1033 // if the first token is not '$' we have an error
1034 if (Parser.getTok().isNot(AsmToken::Dollar))
1035 return MatchOperand_NoMatch;
1037 Parser.Lex(); // Eat $
1038 if(!tryParseRegisterOperand(Operands, false)) {
1039 // set the propper register kind
1040 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
1041 op->setRegKind(MipsOperand::Kind_CPURegs);
1042 return MatchOperand_Success;
1044 return MatchOperand_NoMatch;
1047 MipsAsmParser::OperandMatchResultTy
1048 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1051 return MatchOperand_NoMatch;
1053 // if the first token is not '$' we have error
1054 if (Parser.getTok().isNot(AsmToken::Dollar))
1055 return MatchOperand_NoMatch;
1056 SMLoc S = Parser.getTok().getLoc();
1057 Parser.Lex(); // Eat $
1059 const AsmToken &Tok = Parser.getTok(); // get next token
1060 if (Tok.isNot(AsmToken::Integer))
1061 return MatchOperand_NoMatch;
1063 unsigned RegNum = Tok.getIntVal();
1064 // at the moment only hwreg29 is supported
1066 return MatchOperand_ParseFail;
1068 MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29, S,
1069 Parser.getTok().getLoc());
1070 op->setRegKind(MipsOperand::Kind_HWRegs);
1071 Operands.push_back(op);
1073 Parser.Lex(); // Eat reg number
1074 return MatchOperand_Success;
1077 MipsAsmParser::OperandMatchResultTy
1078 MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1081 return MatchOperand_NoMatch;
1082 //if the first token is not '$' we have error
1083 if (Parser.getTok().isNot(AsmToken::Dollar))
1084 return MatchOperand_NoMatch;
1085 SMLoc S = Parser.getTok().getLoc();
1086 Parser.Lex(); // Eat $
1088 const AsmToken &Tok = Parser.getTok(); // get next token
1089 if (Tok.isNot(AsmToken::Integer))
1090 return MatchOperand_NoMatch;
1092 unsigned RegNum = Tok.getIntVal();
1093 // at the moment only hwreg29 is supported
1095 return MatchOperand_ParseFail;
1097 MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
1098 Parser.getTok().getLoc());
1099 op->setRegKind(MipsOperand::Kind_HW64Regs);
1100 Operands.push_back(op);
1102 Parser.Lex(); // Eat reg number
1103 return MatchOperand_Success;
1106 MipsAsmParser::OperandMatchResultTy
1107 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1109 //if the first token is not '$' we have error
1110 if (Parser.getTok().isNot(AsmToken::Dollar))
1111 return MatchOperand_NoMatch;
1112 SMLoc S = Parser.getTok().getLoc();
1113 Parser.Lex(); // Eat $
1115 const AsmToken &Tok = Parser.getTok(); // get next token
1116 if (Tok.is(AsmToken::Integer)) {
1117 RegNum = Tok.getIntVal();
1118 // at the moment only fcc0 is supported
1120 return MatchOperand_ParseFail;
1121 } else if (Tok.is(AsmToken::Identifier)) {
1122 // at the moment only fcc0 is supported
1123 if (Tok.getIdentifier() != "fcc0")
1124 return MatchOperand_ParseFail;
1126 return MatchOperand_NoMatch;
1128 MipsOperand *op = MipsOperand::CreateReg(Mips::FCC0, S,
1129 Parser.getTok().getLoc());
1130 op->setRegKind(MipsOperand::Kind_CCRRegs);
1131 Operands.push_back(op);
1133 Parser.Lex(); // Eat reg number
1134 return MatchOperand_Success;
1137 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1139 MCSymbolRefExpr::VariantKind VK
1140 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1141 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1142 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1143 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1144 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1145 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1146 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1147 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1148 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1149 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1150 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1151 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1152 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1153 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1154 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1155 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1156 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1157 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1158 .Default(MCSymbolRefExpr::VK_None);
1163 static int ConvertCcString(StringRef CondString) {
1164 int CC = StringSwitch<unsigned>(CondString)
1186 bool MipsAsmParser::
1187 parseMathOperation(StringRef Name, SMLoc NameLoc,
1188 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1190 size_t Start = Name.find('.'), Next = Name.rfind('.');
1191 StringRef Format1 = Name.slice(Start, Next);
1192 // and add the first format to the operands
1193 Operands.push_back(MipsOperand::CreateToken(Format1, NameLoc));
1194 // now for the second format
1195 StringRef Format2 = Name.slice(Next, StringRef::npos);
1196 Operands.push_back(MipsOperand::CreateToken(Format2, NameLoc));
1198 // set the format for the first register
1199 setFpFormat(Format1);
1201 // Read the remaining operands.
1202 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1203 // Read the first operand.
1204 if (ParseOperand(Operands, Name)) {
1205 SMLoc Loc = getLexer().getLoc();
1206 Parser.EatToEndOfStatement();
1207 return Error(Loc, "unexpected token in argument list");
1210 if (getLexer().isNot(AsmToken::Comma)) {
1211 SMLoc Loc = getLexer().getLoc();
1212 Parser.EatToEndOfStatement();
1213 return Error(Loc, "unexpected token in argument list");
1216 Parser.Lex(); // Eat the comma.
1218 //set the format for the first register
1219 setFpFormat(Format2);
1221 // Parse and remember the operand.
1222 if (ParseOperand(Operands, Name)) {
1223 SMLoc Loc = getLexer().getLoc();
1224 Parser.EatToEndOfStatement();
1225 return Error(Loc, "unexpected token in argument list");
1229 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1230 SMLoc Loc = getLexer().getLoc();
1231 Parser.EatToEndOfStatement();
1232 return Error(Loc, "unexpected token in argument list");
1235 Parser.Lex(); // Consume the EndOfStatement
1239 bool MipsAsmParser::
1240 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1241 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1242 // floating point instructions: should register be treated as double?
1243 if (requestsDoubleOperand(Name)) {
1244 setFpFormat(FP_FORMAT_D);
1245 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
1248 setDefaultFpFormat();
1249 // Create the leading tokens for the mnemonic, split by '.' characters.
1250 size_t Start = 0, Next = Name.find('.');
1251 StringRef Mnemonic = Name.slice(Start, Next);
1253 Operands.push_back(MipsOperand::CreateToken(Mnemonic, NameLoc));
1255 if (Next != StringRef::npos) {
1256 // there is a format token in mnemonic
1257 // StringRef Rest = Name.slice(Next, StringRef::npos);
1258 size_t Dot = Name.find('.', Next+1);
1259 StringRef Format = Name.slice(Next, Dot);
1260 if (Dot == StringRef::npos) //only one '.' in a string, it's a format
1261 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1263 if (Name.startswith("c.")){
1264 // floating point compare, add '.' and immediate represent for cc
1265 Operands.push_back(MipsOperand::CreateToken(".", NameLoc));
1266 int Cc = ConvertCcString(Format);
1268 return Error(NameLoc, "Invalid conditional code");
1270 SMLoc E = SMLoc::getFromPointer(
1271 Parser.getTok().getLoc().getPointer() -1 );
1272 Operands.push_back(MipsOperand::CreateImm(
1273 MCConstantExpr::Create(Cc, getContext()), NameLoc, E));
1275 // trunc, ceil, floor ...
1276 return parseMathOperation(Name, NameLoc, Operands);
1279 // the rest is a format
1280 Format = Name.slice(Dot, StringRef::npos);
1281 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1284 setFpFormat(Format);
1288 // Read the remaining operands.
1289 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1290 // Read the first operand.
1291 if (ParseOperand(Operands, Name)) {
1292 SMLoc Loc = getLexer().getLoc();
1293 Parser.EatToEndOfStatement();
1294 return Error(Loc, "unexpected token in argument list");
1297 while (getLexer().is(AsmToken::Comma) ) {
1298 Parser.Lex(); // Eat the comma.
1300 // Parse and remember the operand.
1301 if (ParseOperand(Operands, Name)) {
1302 SMLoc Loc = getLexer().getLoc();
1303 Parser.EatToEndOfStatement();
1304 return Error(Loc, "unexpected token in argument list");
1309 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1310 SMLoc Loc = getLexer().getLoc();
1311 Parser.EatToEndOfStatement();
1312 return Error(Loc, "unexpected token in argument list");
1315 Parser.Lex(); // Consume the EndOfStatement
1319 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
1320 SMLoc Loc = getLexer().getLoc();
1321 Parser.EatToEndOfStatement();
1322 return Error(Loc, ErrorMsg);
1325 bool MipsAsmParser::parseSetNoAtDirective() {
1326 // line should look like:
1329 Options.setATReg(0);
1332 // if this is not the end of the statement, report error
1333 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1334 reportParseError("unexpected token in statement");
1337 Parser.Lex(); // Consume the EndOfStatement
1340 bool MipsAsmParser::parseSetAtDirective() {
1342 // .set at - defaults to $1
1345 if (getLexer().is(AsmToken::EndOfStatement)) {
1346 Options.setATReg(1);
1347 Parser.Lex(); // Consume the EndOfStatement
1349 } else if (getLexer().is(AsmToken::Equal)) {
1350 getParser().Lex(); //eat '='
1351 if (getLexer().isNot(AsmToken::Dollar)) {
1352 reportParseError("unexpected token in statement");
1355 Parser.Lex(); // eat '$'
1356 if (getLexer().isNot(AsmToken::Integer)) {
1357 reportParseError("unexpected token in statement");
1360 const AsmToken &Reg = Parser.getTok();
1361 if (!Options.setATReg(Reg.getIntVal())) {
1362 reportParseError("unexpected token in statement");
1365 getParser().Lex(); //eat reg
1367 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1368 reportParseError("unexpected token in statement");
1371 Parser.Lex(); // Consume the EndOfStatement
1374 reportParseError("unexpected token in statement");
1379 bool MipsAsmParser::parseSetReorderDirective() {
1381 // if this is not the end of the statement, report error
1382 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1383 reportParseError("unexpected token in statement");
1386 Options.setReorder();
1387 Parser.Lex(); // Consume the EndOfStatement
1391 bool MipsAsmParser::parseSetNoReorderDirective() {
1393 // if this is not the end of the statement, report error
1394 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1395 reportParseError("unexpected token in statement");
1398 Options.setNoreorder();
1399 Parser.Lex(); // Consume the EndOfStatement
1403 bool MipsAsmParser::parseSetMacroDirective() {
1405 // if this is not the end of the statement, report error
1406 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1407 reportParseError("unexpected token in statement");
1411 Parser.Lex(); // Consume the EndOfStatement
1415 bool MipsAsmParser::parseSetNoMacroDirective() {
1417 // if this is not the end of the statement, report error
1418 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1419 reportParseError("`noreorder' must be set before `nomacro'");
1422 if (Options.isReorder()) {
1423 reportParseError("`noreorder' must be set before `nomacro'");
1426 Options.setNomacro();
1427 Parser.Lex(); // Consume the EndOfStatement
1430 bool MipsAsmParser::parseDirectiveSet() {
1433 const AsmToken &Tok = Parser.getTok();
1435 if (Tok.getString() == "noat") {
1436 return parseSetNoAtDirective();
1437 } else if (Tok.getString() == "at") {
1438 return parseSetAtDirective();
1439 } else if (Tok.getString() == "reorder") {
1440 return parseSetReorderDirective();
1441 } else if (Tok.getString() == "noreorder") {
1442 return parseSetNoReorderDirective();
1443 } else if (Tok.getString() == "macro") {
1444 return parseSetMacroDirective();
1445 } else if (Tok.getString() == "nomacro") {
1446 return parseSetNoMacroDirective();
1447 } else if (Tok.getString() == "nomips16") {
1448 // ignore this directive for now
1449 Parser.EatToEndOfStatement();
1451 } else if (Tok.getString() == "nomicromips") {
1452 // ignore this directive for now
1453 Parser.EatToEndOfStatement();
1460 /// parseDirectiveWord
1461 /// ::= .word [ expression (, expression)* ]
1462 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
1463 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1465 const MCExpr *Value;
1466 if (getParser().ParseExpression(Value))
1469 getParser().getStreamer().EmitValue(Value, Size);
1471 if (getLexer().is(AsmToken::EndOfStatement))
1474 // FIXME: Improve diagnostic.
1475 if (getLexer().isNot(AsmToken::Comma))
1476 return Error(L, "unexpected token in directive");
1485 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
1487 StringRef IDVal = DirectiveID.getString();
1489 if ( IDVal == ".ent") {
1490 // ignore this directive for now
1495 if (IDVal == ".end") {
1496 // ignore this directive for now
1501 if (IDVal == ".frame") {
1502 // ignore this directive for now
1503 Parser.EatToEndOfStatement();
1507 if (IDVal == ".set") {
1508 return parseDirectiveSet();
1511 if (IDVal == ".fmask") {
1512 // ignore this directive for now
1513 Parser.EatToEndOfStatement();
1517 if (IDVal == ".mask") {
1518 // ignore this directive for now
1519 Parser.EatToEndOfStatement();
1523 if (IDVal == ".gpword") {
1524 // ignore this directive for now
1525 Parser.EatToEndOfStatement();
1529 if (IDVal == ".word") {
1530 parseDirectiveWord(4, DirectiveID.getLoc());
1537 extern "C" void LLVMInitializeMipsAsmParser() {
1538 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
1539 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
1540 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
1541 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
1544 #define GET_REGISTER_MATCHER
1545 #define GET_MATCHER_IMPLEMENTATION
1546 #include "MipsGenAsmMatcher.inc"