1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCExpr.h"
11 #include "MCTargetDesc/MipsMCTargetDesc.h"
12 #include "MipsRegisterInfo.h"
13 #include "MipsTargetStreamer.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstBuilder.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/TargetRegistry.h"
32 #define DEBUG_TYPE "mips-asm-parser"
39 class MipsAssemblerOptions {
41 MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {}
43 unsigned getATRegNum() { return aTReg; }
44 bool setATReg(unsigned Reg);
46 bool isReorder() { return reorder; }
47 void setReorder() { reorder = true; }
48 void setNoreorder() { reorder = false; }
50 bool isMacro() { return macro; }
51 void setMacro() { macro = true; }
52 void setNomacro() { macro = false; }
62 class MipsAsmParser : public MCTargetAsmParser {
63 MipsTargetStreamer &getTargetStreamer() {
64 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
65 return static_cast<MipsTargetStreamer &>(TS);
70 MipsAssemblerOptions Options;
72 #define GET_ASSEMBLER_HEADER
73 #include "MipsGenAsmMatcher.inc"
75 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
77 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
78 OperandVector &Operands, MCStreamer &Out,
80 bool MatchingInlineAsm) override;
82 /// Parse a register as used in CFI directives
83 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
85 bool ParseParenSuffix(StringRef Name, OperandVector &Operands);
87 bool ParseBracketSuffix(StringRef Name, OperandVector &Operands);
89 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
90 SMLoc NameLoc, OperandVector &Operands) override;
92 bool ParseDirective(AsmToken DirectiveID) override;
94 MipsAsmParser::OperandMatchResultTy parseMemOperand(OperandVector &Operands);
96 MipsAsmParser::OperandMatchResultTy
97 MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
98 StringRef Identifier, SMLoc S);
100 MipsAsmParser::OperandMatchResultTy
101 MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S);
103 MipsAsmParser::OperandMatchResultTy ParseAnyRegister(OperandVector &Operands);
105 MipsAsmParser::OperandMatchResultTy ParseImm(OperandVector &Operands);
107 MipsAsmParser::OperandMatchResultTy ParseJumpTarget(OperandVector &Operands);
109 MipsAsmParser::OperandMatchResultTy parseInvNum(OperandVector &Operands);
111 MipsAsmParser::OperandMatchResultTy ParseLSAImm(OperandVector &Operands);
113 bool searchSymbolAlias(OperandVector &Operands);
115 bool ParseOperand(OperandVector &, StringRef Mnemonic);
117 bool needsExpansion(MCInst &Inst);
119 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
120 SmallVectorImpl<MCInst> &Instructions);
121 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
122 SmallVectorImpl<MCInst> &Instructions);
123 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
124 SmallVectorImpl<MCInst> &Instructions);
125 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
126 SmallVectorImpl<MCInst> &Instructions);
127 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
128 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
130 bool reportParseError(StringRef ErrorMsg);
131 bool reportParseError(SMLoc Loc, StringRef ErrorMsg);
133 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
134 bool parseRelocOperand(const MCExpr *&Res);
136 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
138 bool isEvaluated(const MCExpr *Expr);
139 bool parseSetFeature(uint64_t Feature);
140 bool parseDirectiveCPLoad(SMLoc Loc);
141 bool parseDirectiveCPSetup();
142 bool parseDirectiveNaN();
143 bool parseDirectiveSet();
144 bool parseDirectiveOption();
146 bool parseSetAtDirective();
147 bool parseSetNoAtDirective();
148 bool parseSetMacroDirective();
149 bool parseSetNoMacroDirective();
150 bool parseSetReorderDirective();
151 bool parseSetNoReorderDirective();
152 bool parseSetNoMips16Directive();
154 bool parseSetAssignment();
156 bool parseDataDirective(unsigned Size, SMLoc L);
157 bool parseDirectiveGpWord();
158 bool parseDirectiveGpDWord();
160 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
162 bool isGP64() const {
163 return (STI.getFeatureBits() & Mips::FeatureGP64Bit) != 0;
166 bool isFP64() const {
167 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
170 bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
171 bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
173 bool isMicroMips() const {
174 return STI.getFeatureBits() & Mips::FeatureMicroMips;
177 bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4; }
178 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
179 bool hasMips32r6() const {
180 return STI.getFeatureBits() & Mips::FeatureMips32r6;
182 bool hasMips64r6() const {
183 return STI.getFeatureBits() & Mips::FeatureMips64r6;
186 bool eatComma(StringRef ErrorStr);
188 int matchCPURegisterName(StringRef Symbol);
190 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
192 int matchFPURegisterName(StringRef Name);
194 int matchFCCRegisterName(StringRef Name);
196 int matchACRegisterName(StringRef Name);
198 int matchMSA128RegisterName(StringRef Name);
200 int matchMSA128CtrlRegisterName(StringRef Name);
202 unsigned getReg(int RC, int RegNo);
204 unsigned getGPR(int RegNo);
208 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
209 SmallVectorImpl<MCInst> &Instructions);
211 // Helper function that checks if the value of a vector index is within the
212 // boundaries of accepted values for each RegisterKind
213 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
214 bool validateMSAIndex(int Val, int RegKind);
216 void setFeatureBits(unsigned Feature, StringRef FeatureString) {
217 if (!(STI.getFeatureBits() & Feature)) {
218 setAvailableFeatures(
219 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
223 void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
224 if (STI.getFeatureBits() & Feature) {
225 setAvailableFeatures(
226 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
231 enum MipsMatchResultTy {
232 Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY
233 #define GET_OPERAND_DIAGNOSTIC_TYPES
234 #include "MipsGenAsmMatcher.inc"
235 #undef GET_OPERAND_DIAGNOSTIC_TYPES
239 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
240 const MCInstrInfo &MII,
241 const MCTargetOptions &Options)
242 : MCTargetAsmParser(), STI(sti), Parser(parser) {
243 // Initialize the set of available features.
244 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
246 // Assert exactly one ABI was chosen.
247 assert((((STI.getFeatureBits() & Mips::FeatureO32) != 0) +
248 ((STI.getFeatureBits() & Mips::FeatureEABI) != 0) +
249 ((STI.getFeatureBits() & Mips::FeatureN32) != 0) +
250 ((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
253 MCAsmParser &getParser() const { return Parser; }
254 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
256 /// True if all of $fcc0 - $fcc7 exist for the current ISA.
257 bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
259 /// Warn if RegNo is the current assembler temporary.
260 void WarnIfAssemblerTemporary(int RegNo, SMLoc Loc);
266 /// MipsOperand - Instances of this class represent a parsed Mips machine
268 class MipsOperand : public MCParsedAsmOperand {
270 /// Broad categories of register classes
271 /// The exact class is finalized by the render method.
273 RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64())
274 RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and
276 RegKind_FCC = 4, /// FCC
277 RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which)
278 RegKind_MSACtrl = 16, /// MSA control registers
279 RegKind_COP2 = 32, /// COP2
280 RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on
282 RegKind_CCR = 128, /// CCR
283 RegKind_HWRegs = 256, /// HWRegs
284 RegKind_COP3 = 512, /// COP3
286 /// Potentially any (e.g. $1)
287 RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
288 RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
289 RegKind_CCR | RegKind_HWRegs | RegKind_COP3
294 k_Immediate, /// An immediate (possibly involving symbol references)
295 k_Memory, /// Base + Offset Memory Address
296 k_PhysRegister, /// A physical register from the Mips namespace
297 k_RegisterIndex, /// A register index in one or more RegKind.
298 k_Token /// A simple token
302 MipsOperand(KindTy K, MipsAsmParser &Parser)
303 : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
306 /// For diagnostics, and checking the assembler temporary
307 MipsAsmParser &AsmParser;
315 unsigned Num; /// Register Number
319 unsigned Index; /// Index into the register class
320 RegKind Kind; /// Bitfield of the kinds it could possibly be
321 const MCRegisterInfo *RegInfo;
335 struct PhysRegOp PhysReg;
336 struct RegIdxOp RegIdx;
341 SMLoc StartLoc, EndLoc;
343 /// Internal constructor for register kinds
344 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind,
345 const MCRegisterInfo *RegInfo,
347 MipsAsmParser &Parser) {
348 auto Op = make_unique<MipsOperand>(k_RegisterIndex, Parser);
349 Op->RegIdx.Index = Index;
350 Op->RegIdx.RegInfo = RegInfo;
351 Op->RegIdx.Kind = RegKind;
358 /// Coerce the register to GPR32 and return the real register for the current
360 unsigned getGPR32Reg() const {
361 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
362 AsmParser.WarnIfAssemblerTemporary(RegIdx.Index, StartLoc);
363 unsigned ClassID = Mips::GPR32RegClassID;
364 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
367 /// Coerce the register to GPR64 and return the real register for the current
369 unsigned getGPR64Reg() const {
370 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
371 unsigned ClassID = Mips::GPR64RegClassID;
372 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
376 /// Coerce the register to AFGR64 and return the real register for the current
378 unsigned getAFGR64Reg() const {
379 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
380 if (RegIdx.Index % 2 != 0)
381 AsmParser.Warning(StartLoc, "Float register should be even.");
382 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
383 .getRegister(RegIdx.Index / 2);
386 /// Coerce the register to FGR64 and return the real register for the current
388 unsigned getFGR64Reg() const {
389 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
390 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
391 .getRegister(RegIdx.Index);
394 /// Coerce the register to FGR32 and return the real register for the current
396 unsigned getFGR32Reg() const {
397 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
398 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
399 .getRegister(RegIdx.Index);
402 /// Coerce the register to FGRH32 and return the real register for the current
404 unsigned getFGRH32Reg() const {
405 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
406 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)
407 .getRegister(RegIdx.Index);
410 /// Coerce the register to FCC and return the real register for the current
412 unsigned getFCCReg() const {
413 assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
414 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
415 .getRegister(RegIdx.Index);
418 /// Coerce the register to MSA128 and return the real register for the current
420 unsigned getMSA128Reg() const {
421 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
422 // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
424 unsigned ClassID = Mips::MSA128BRegClassID;
425 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
428 /// Coerce the register to MSACtrl and return the real register for the
430 unsigned getMSACtrlReg() const {
431 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
432 unsigned ClassID = Mips::MSACtrlRegClassID;
433 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
436 /// Coerce the register to COP2 and return the real register for the
438 unsigned getCOP2Reg() const {
439 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
440 unsigned ClassID = Mips::COP2RegClassID;
441 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
444 /// Coerce the register to COP3 and return the real register for the
446 unsigned getCOP3Reg() const {
447 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
448 unsigned ClassID = Mips::COP3RegClassID;
449 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
452 /// Coerce the register to ACC64DSP and return the real register for the
454 unsigned getACC64DSPReg() const {
455 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
456 unsigned ClassID = Mips::ACC64DSPRegClassID;
457 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
460 /// Coerce the register to HI32DSP and return the real register for the
462 unsigned getHI32DSPReg() const {
463 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
464 unsigned ClassID = Mips::HI32DSPRegClassID;
465 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
468 /// Coerce the register to LO32DSP and return the real register for the
470 unsigned getLO32DSPReg() const {
471 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
472 unsigned ClassID = Mips::LO32DSPRegClassID;
473 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
476 /// Coerce the register to CCR and return the real register for the
478 unsigned getCCRReg() const {
479 assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
480 unsigned ClassID = Mips::CCRRegClassID;
481 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
484 /// Coerce the register to HWRegs and return the real register for the
486 unsigned getHWRegsReg() const {
487 assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
488 unsigned ClassID = Mips::HWRegsRegClassID;
489 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
493 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
494 // Add as immediate when possible. Null MCExpr = 0.
496 Inst.addOperand(MCOperand::CreateImm(0));
497 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
498 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
500 Inst.addOperand(MCOperand::CreateExpr(Expr));
503 void addRegOperands(MCInst &Inst, unsigned N) const {
504 llvm_unreachable("Use a custom parser instead");
507 /// Render the operand to an MCInst as a GPR32
508 /// Asserts if the wrong number of operands are requested, or the operand
509 /// is not a k_RegisterIndex compatible with RegKind_GPR
510 void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
511 assert(N == 1 && "Invalid number of operands!");
512 Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
515 /// Render the operand to an MCInst as a GPR64
516 /// Asserts if the wrong number of operands are requested, or the operand
517 /// is not a k_RegisterIndex compatible with RegKind_GPR
518 void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
519 assert(N == 1 && "Invalid number of operands!");
520 Inst.addOperand(MCOperand::CreateReg(getGPR64Reg()));
523 void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
524 assert(N == 1 && "Invalid number of operands!");
525 Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg()));
528 void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
529 assert(N == 1 && "Invalid number of operands!");
530 Inst.addOperand(MCOperand::CreateReg(getFGR64Reg()));
533 void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
534 assert(N == 1 && "Invalid number of operands!");
535 Inst.addOperand(MCOperand::CreateReg(getFGR32Reg()));
538 void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
539 assert(N == 1 && "Invalid number of operands!");
540 Inst.addOperand(MCOperand::CreateReg(getFGRH32Reg()));
543 void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
544 assert(N == 1 && "Invalid number of operands!");
545 Inst.addOperand(MCOperand::CreateReg(getFCCReg()));
548 void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
549 assert(N == 1 && "Invalid number of operands!");
550 Inst.addOperand(MCOperand::CreateReg(getMSA128Reg()));
553 void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
554 assert(N == 1 && "Invalid number of operands!");
555 Inst.addOperand(MCOperand::CreateReg(getMSACtrlReg()));
558 void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
559 assert(N == 1 && "Invalid number of operands!");
560 Inst.addOperand(MCOperand::CreateReg(getCOP2Reg()));
563 void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
564 assert(N == 1 && "Invalid number of operands!");
565 Inst.addOperand(MCOperand::CreateReg(getCOP3Reg()));
568 void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
569 assert(N == 1 && "Invalid number of operands!");
570 Inst.addOperand(MCOperand::CreateReg(getACC64DSPReg()));
573 void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
574 assert(N == 1 && "Invalid number of operands!");
575 Inst.addOperand(MCOperand::CreateReg(getHI32DSPReg()));
578 void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
579 assert(N == 1 && "Invalid number of operands!");
580 Inst.addOperand(MCOperand::CreateReg(getLO32DSPReg()));
583 void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
584 assert(N == 1 && "Invalid number of operands!");
585 Inst.addOperand(MCOperand::CreateReg(getCCRReg()));
588 void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
589 assert(N == 1 && "Invalid number of operands!");
590 Inst.addOperand(MCOperand::CreateReg(getHWRegsReg()));
593 void addImmOperands(MCInst &Inst, unsigned N) const {
594 assert(N == 1 && "Invalid number of operands!");
595 const MCExpr *Expr = getImm();
599 void addMemOperands(MCInst &Inst, unsigned N) const {
600 assert(N == 2 && "Invalid number of operands!");
602 Inst.addOperand(MCOperand::CreateReg(getMemBase()->getGPR32Reg()));
604 const MCExpr *Expr = getMemOff();
608 bool isReg() const override {
609 // As a special case until we sort out the definition of div/divu, pretend
610 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
611 if (isGPRAsmReg() && RegIdx.Index == 0)
614 return Kind == k_PhysRegister;
616 bool isRegIdx() const { return Kind == k_RegisterIndex; }
617 bool isImm() const override { return Kind == k_Immediate; }
618 bool isConstantImm() const {
619 return isImm() && dyn_cast<MCConstantExpr>(getImm());
621 bool isToken() const override {
622 // Note: It's not possible to pretend that other operand kinds are tokens.
623 // The matcher emitter checks tokens first.
624 return Kind == k_Token;
626 bool isMem() const override { return Kind == k_Memory; }
627 bool isConstantMemOff() const {
628 return isMem() && dyn_cast<MCConstantExpr>(getMemOff());
630 template <unsigned Bits> bool isMemWithSimmOffset() const {
631 return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff());
633 bool isInvNum() const { return Kind == k_Immediate; }
634 bool isLSAImm() const {
635 if (!isConstantImm())
637 int64_t Val = getConstantImm();
638 return 1 <= Val && Val <= 4;
641 StringRef getToken() const {
642 assert(Kind == k_Token && "Invalid access!");
643 return StringRef(Tok.Data, Tok.Length);
646 unsigned getReg() const override {
647 // As a special case until we sort out the definition of div/divu, pretend
648 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
649 if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
650 RegIdx.Kind & RegKind_GPR)
651 return getGPR32Reg(); // FIXME: GPR64 too
653 assert(Kind == k_PhysRegister && "Invalid access!");
657 const MCExpr *getImm() const {
658 assert((Kind == k_Immediate) && "Invalid access!");
662 int64_t getConstantImm() const {
663 const MCExpr *Val = getImm();
664 return static_cast<const MCConstantExpr *>(Val)->getValue();
667 MipsOperand *getMemBase() const {
668 assert((Kind == k_Memory) && "Invalid access!");
672 const MCExpr *getMemOff() const {
673 assert((Kind == k_Memory) && "Invalid access!");
677 int64_t getConstantMemOff() const {
678 return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
681 static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S,
682 MipsAsmParser &Parser) {
683 auto Op = make_unique<MipsOperand>(k_Token, Parser);
684 Op->Tok.Data = Str.data();
685 Op->Tok.Length = Str.size();
691 /// Create a numeric register (e.g. $1). The exact register remains
692 /// unresolved until an instruction successfully matches
693 static std::unique_ptr<MipsOperand>
694 CreateNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
695 SMLoc E, MipsAsmParser &Parser) {
696 DEBUG(dbgs() << "CreateNumericReg(" << Index << ", ...)\n");
697 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser);
700 /// Create a register that is definitely a GPR.
701 /// This is typically only used for named registers such as $gp.
702 static std::unique_ptr<MipsOperand>
703 CreateGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
704 MipsAsmParser &Parser) {
705 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser);
708 /// Create a register that is definitely a FGR.
709 /// This is typically only used for named registers such as $f0.
710 static std::unique_ptr<MipsOperand>
711 CreateFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
712 MipsAsmParser &Parser) {
713 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
716 /// Create a register that is definitely an FCC.
717 /// This is typically only used for named registers such as $fcc0.
718 static std::unique_ptr<MipsOperand>
719 CreateFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
720 MipsAsmParser &Parser) {
721 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
724 /// Create a register that is definitely an ACC.
725 /// This is typically only used for named registers such as $ac0.
726 static std::unique_ptr<MipsOperand>
727 CreateACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
728 MipsAsmParser &Parser) {
729 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser);
732 /// Create a register that is definitely an MSA128.
733 /// This is typically only used for named registers such as $w0.
734 static std::unique_ptr<MipsOperand>
735 CreateMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
736 SMLoc E, MipsAsmParser &Parser) {
737 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser);
740 /// Create a register that is definitely an MSACtrl.
741 /// This is typically only used for named registers such as $msaaccess.
742 static std::unique_ptr<MipsOperand>
743 CreateMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
744 SMLoc E, MipsAsmParser &Parser) {
745 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
748 static std::unique_ptr<MipsOperand>
749 CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
750 auto Op = make_unique<MipsOperand>(k_Immediate, Parser);
757 static std::unique_ptr<MipsOperand>
758 CreateMem(std::unique_ptr<MipsOperand> Base, const MCExpr *Off, SMLoc S,
759 SMLoc E, MipsAsmParser &Parser) {
760 auto Op = make_unique<MipsOperand>(k_Memory, Parser);
761 Op->Mem.Base = Base.release();
768 bool isGPRAsmReg() const {
769 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
771 bool isFGRAsmReg() const {
772 // AFGR64 is $0-$15 but we handle this in getAFGR64()
773 return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
775 bool isHWRegsAsmReg() const {
776 return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
778 bool isCCRAsmReg() const {
779 return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
781 bool isFCCAsmReg() const {
782 if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC))
784 if (!AsmParser.hasEightFccRegisters())
785 return RegIdx.Index == 0;
786 return RegIdx.Index <= 7;
788 bool isACCAsmReg() const {
789 return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
791 bool isCOP2AsmReg() const {
792 return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
794 bool isCOP3AsmReg() const {
795 return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
797 bool isMSA128AsmReg() const {
798 return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
800 bool isMSACtrlAsmReg() const {
801 return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
804 /// getStartLoc - Get the location of the first token of this operand.
805 SMLoc getStartLoc() const override { return StartLoc; }
806 /// getEndLoc - Get the location of the last token of this operand.
807 SMLoc getEndLoc() const override { return EndLoc; }
809 virtual ~MipsOperand() {
817 case k_RegisterIndex:
823 void print(raw_ostream &OS) const override {
838 OS << "PhysReg<" << PhysReg.Num << ">";
840 case k_RegisterIndex:
841 OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">";
848 }; // class MipsOperand
852 extern const MCInstrDesc MipsInsts[];
854 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
855 return MipsInsts[Opcode];
858 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
859 SmallVectorImpl<MCInst> &Instructions) {
860 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
864 if (MCID.isBranch() || MCID.isCall()) {
865 const unsigned Opcode = Inst.getOpcode();
875 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
876 Offset = Inst.getOperand(2);
878 break; // We'll deal with this situation later on when applying fixups.
879 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
880 return Error(IDLoc, "branch target out of range");
881 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
882 return Error(IDLoc, "branch to misaligned address");
896 case Mips::BGEZAL_MM:
897 case Mips::BLTZAL_MM:
900 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
901 Offset = Inst.getOperand(1);
903 break; // We'll deal with this situation later on when applying fixups.
904 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
905 return Error(IDLoc, "branch target out of range");
906 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
907 return Error(IDLoc, "branch to misaligned address");
912 // SSNOP is deprecated on MIPS32r6/MIPS64r6
913 // We still accept it but it is a normal nop.
914 if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) {
915 std::string ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
916 Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a "
920 if (MCID.hasDelaySlot() && Options.isReorder()) {
921 // If this instruction has a delay slot and .set reorder is active,
922 // emit a NOP after it.
923 Instructions.push_back(Inst);
925 NopInst.setOpcode(Mips::SLL);
926 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
927 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
928 NopInst.addOperand(MCOperand::CreateImm(0));
929 Instructions.push_back(NopInst);
933 if (MCID.mayLoad() || MCID.mayStore()) {
934 // Check the offset of memory operand, if it is a symbol
935 // reference or immediate we may have to expand instructions.
936 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
937 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
938 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
939 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
940 MCOperand &Op = Inst.getOperand(i);
942 int MemOffset = Op.getImm();
943 if (MemOffset < -32768 || MemOffset > 32767) {
944 // Offset can't exceed 16bit value.
945 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
948 } else if (Op.isExpr()) {
949 const MCExpr *Expr = Op.getExpr();
950 if (Expr->getKind() == MCExpr::SymbolRef) {
951 const MCSymbolRefExpr *SR =
952 static_cast<const MCSymbolRefExpr *>(Expr);
953 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
955 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
958 } else if (!isEvaluated(Expr)) {
959 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
967 if (needsExpansion(Inst))
968 expandInstruction(Inst, IDLoc, Instructions);
970 Instructions.push_back(Inst);
975 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
977 switch (Inst.getOpcode()) {
978 case Mips::LoadImm32Reg:
979 case Mips::LoadAddr32Imm:
980 case Mips::LoadAddr32Reg:
987 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
988 SmallVectorImpl<MCInst> &Instructions) {
989 switch (Inst.getOpcode()) {
990 case Mips::LoadImm32Reg:
991 return expandLoadImm(Inst, IDLoc, Instructions);
992 case Mips::LoadAddr32Imm:
993 return expandLoadAddressImm(Inst, IDLoc, Instructions);
994 case Mips::LoadAddr32Reg:
995 return expandLoadAddressReg(Inst, IDLoc, Instructions);
999 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
1000 SmallVectorImpl<MCInst> &Instructions) {
1002 const MCOperand &ImmOp = Inst.getOperand(1);
1003 assert(ImmOp.isImm() && "expected immediate operand kind");
1004 const MCOperand &RegOp = Inst.getOperand(0);
1005 assert(RegOp.isReg() && "expected register operand kind");
1007 int ImmValue = ImmOp.getImm();
1008 tmpInst.setLoc(IDLoc);
1009 if (0 <= ImmValue && ImmValue <= 65535) {
1010 // For 0 <= j <= 65535.
1011 // li d,j => ori d,$zero,j
1012 tmpInst.setOpcode(Mips::ORi);
1013 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1014 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1015 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1016 Instructions.push_back(tmpInst);
1017 } else if (ImmValue < 0 && ImmValue >= -32768) {
1018 // For -32768 <= j < 0.
1019 // li d,j => addiu d,$zero,j
1020 tmpInst.setOpcode(Mips::ADDiu);
1021 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1022 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1023 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1024 Instructions.push_back(tmpInst);
1026 // For any other value of j that is representable as a 32-bit integer.
1027 // li d,j => lui d,hi16(j)
1029 tmpInst.setOpcode(Mips::LUi);
1030 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1031 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1032 Instructions.push_back(tmpInst);
1034 tmpInst.setOpcode(Mips::ORi);
1035 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1036 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1037 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1038 tmpInst.setLoc(IDLoc);
1039 Instructions.push_back(tmpInst);
1044 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
1045 SmallVectorImpl<MCInst> &Instructions) {
1047 const MCOperand &ImmOp = Inst.getOperand(2);
1048 assert(ImmOp.isImm() && "expected immediate operand kind");
1049 const MCOperand &SrcRegOp = Inst.getOperand(1);
1050 assert(SrcRegOp.isReg() && "expected register operand kind");
1051 const MCOperand &DstRegOp = Inst.getOperand(0);
1052 assert(DstRegOp.isReg() && "expected register operand kind");
1053 int ImmValue = ImmOp.getImm();
1054 if (-32768 <= ImmValue && ImmValue <= 65535) {
1055 // For -32768 <= j <= 65535.
1056 // la d,j(s) => addiu d,s,j
1057 tmpInst.setOpcode(Mips::ADDiu);
1058 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1059 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1060 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1061 Instructions.push_back(tmpInst);
1063 // For any other value of j that is representable as a 32-bit integer.
1064 // la d,j(s) => lui d,hi16(j)
1067 tmpInst.setOpcode(Mips::LUi);
1068 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1069 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1070 Instructions.push_back(tmpInst);
1072 tmpInst.setOpcode(Mips::ORi);
1073 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1074 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1075 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1076 Instructions.push_back(tmpInst);
1078 tmpInst.setOpcode(Mips::ADDu);
1079 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1080 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1081 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1082 Instructions.push_back(tmpInst);
1087 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
1088 SmallVectorImpl<MCInst> &Instructions) {
1090 const MCOperand &ImmOp = Inst.getOperand(1);
1091 assert(ImmOp.isImm() && "expected immediate operand kind");
1092 const MCOperand &RegOp = Inst.getOperand(0);
1093 assert(RegOp.isReg() && "expected register operand kind");
1094 int ImmValue = ImmOp.getImm();
1095 if (-32768 <= ImmValue && ImmValue <= 65535) {
1096 // For -32768 <= j <= 65535.
1097 // la d,j => addiu d,$zero,j
1098 tmpInst.setOpcode(Mips::ADDiu);
1099 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1100 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1101 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1102 Instructions.push_back(tmpInst);
1104 // For any other value of j that is representable as a 32-bit integer.
1105 // la d,j => lui d,hi16(j)
1107 tmpInst.setOpcode(Mips::LUi);
1108 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1109 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1110 Instructions.push_back(tmpInst);
1112 tmpInst.setOpcode(Mips::ORi);
1113 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1114 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1115 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1116 Instructions.push_back(tmpInst);
1120 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
1121 SmallVectorImpl<MCInst> &Instructions,
1122 bool isLoad, bool isImmOpnd) {
1123 const MCSymbolRefExpr *SR;
1125 unsigned ImmOffset, HiOffset, LoOffset;
1126 const MCExpr *ExprOffset;
1128 unsigned AtRegNum = getReg(
1129 (isGP64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
1130 // 1st operand is either the source or destination register.
1131 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
1132 unsigned RegOpNum = Inst.getOperand(0).getReg();
1133 // 2nd operand is the base register.
1134 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
1135 unsigned BaseRegNum = Inst.getOperand(1).getReg();
1136 // 3rd operand is either an immediate or expression.
1138 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
1139 ImmOffset = Inst.getOperand(2).getImm();
1140 LoOffset = ImmOffset & 0x0000ffff;
1141 HiOffset = (ImmOffset & 0xffff0000) >> 16;
1142 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
1143 if (LoOffset & 0x8000)
1146 ExprOffset = Inst.getOperand(2).getExpr();
1147 // All instructions will have the same location.
1148 TempInst.setLoc(IDLoc);
1149 // 1st instruction in expansion is LUi. For load instruction we can use
1150 // the dst register as a temporary if base and dst are different,
1151 // but for stores we must use $at.
1152 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
1153 TempInst.setOpcode(Mips::LUi);
1154 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1156 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
1158 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1159 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
1160 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
1161 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
1163 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1165 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
1166 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1169 // Add the instruction to the list.
1170 Instructions.push_back(TempInst);
1171 // Prepare TempInst for next instruction.
1173 // Add temp register to base.
1174 TempInst.setOpcode(Mips::ADDu);
1175 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1176 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1177 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
1178 Instructions.push_back(TempInst);
1180 // And finally, create original instruction with low part
1181 // of offset and new base.
1182 TempInst.setOpcode(Inst.getOpcode());
1183 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
1184 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1186 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
1188 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1189 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
1190 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
1192 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1194 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
1195 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1198 Instructions.push_back(TempInst);
1202 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
1203 // As described by the Mips32r2 spec, the registers Rd and Rs for
1204 // jalr.hb must be different.
1205 unsigned Opcode = Inst.getOpcode();
1207 if (Opcode == Mips::JALR_HB &&
1208 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()))
1209 return Match_RequiresDifferentSrcAndDst;
1211 return Match_Success;
1214 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1215 OperandVector &Operands,
1217 unsigned &ErrorInfo,
1218 bool MatchingInlineAsm) {
1221 SmallVector<MCInst, 8> Instructions;
1222 unsigned MatchResult =
1223 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
1225 switch (MatchResult) {
1228 case Match_Success: {
1229 if (processInstruction(Inst, IDLoc, Instructions))
1231 for (unsigned i = 0; i < Instructions.size(); i++)
1232 Out.EmitInstruction(Instructions[i], STI);
1235 case Match_MissingFeature:
1236 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1238 case Match_InvalidOperand: {
1239 SMLoc ErrorLoc = IDLoc;
1240 if (ErrorInfo != ~0U) {
1241 if (ErrorInfo >= Operands.size())
1242 return Error(IDLoc, "too few operands for instruction");
1244 ErrorLoc = ((MipsOperand &)*Operands[ErrorInfo]).getStartLoc();
1245 if (ErrorLoc == SMLoc())
1249 return Error(ErrorLoc, "invalid operand for instruction");
1251 case Match_MnemonicFail:
1252 return Error(IDLoc, "invalid instruction");
1253 case Match_RequiresDifferentSrcAndDst:
1254 return Error(IDLoc, "source and destination must be different");
1259 void MipsAsmParser::WarnIfAssemblerTemporary(int RegIndex, SMLoc Loc) {
1260 if ((RegIndex != 0) && ((int)Options.getATRegNum() == RegIndex)) {
1262 Warning(Loc, "Used $at without \".set noat\"");
1264 Warning(Loc, Twine("Used $") + Twine(RegIndex) + " with \".set at=$" +
1265 Twine(RegIndex) + "\"");
1269 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
1272 CC = StringSwitch<unsigned>(Name)
1308 if (isN32() || isN64()) {
1309 // Although SGI documentation just cuts out t0-t3 for n32/n64,
1310 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
1311 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
1312 if (8 <= CC && CC <= 11)
1316 CC = StringSwitch<unsigned>(Name)
1329 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
1331 if (Name[0] == 'f') {
1332 StringRef NumString = Name.substr(1);
1334 if (NumString.getAsInteger(10, IntVal))
1335 return -1; // This is not an integer.
1336 if (IntVal > 31) // Maximum index for fpu register.
1343 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
1345 if (Name.startswith("fcc")) {
1346 StringRef NumString = Name.substr(3);
1348 if (NumString.getAsInteger(10, IntVal))
1349 return -1; // This is not an integer.
1350 if (IntVal > 7) // There are only 8 fcc registers.
1357 int MipsAsmParser::matchACRegisterName(StringRef Name) {
1359 if (Name.startswith("ac")) {
1360 StringRef NumString = Name.substr(2);
1362 if (NumString.getAsInteger(10, IntVal))
1363 return -1; // This is not an integer.
1364 if (IntVal > 3) // There are only 3 acc registers.
1371 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
1374 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
1383 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1386 CC = StringSwitch<unsigned>(Name)
1389 .Case("msaaccess", 2)
1391 .Case("msamodify", 4)
1392 .Case("msarequest", 5)
1394 .Case("msaunmap", 7)
1400 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1408 int MipsAsmParser::getATReg() {
1409 int AT = Options.getATRegNum();
1411 TokError("Pseudo instruction requires $at, which is not available");
1415 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1416 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1419 unsigned MipsAsmParser::getGPR(int RegNo) {
1420 return getReg(isGP64() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
1424 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1426 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
1429 return getReg(RegClass, RegNum);
1432 bool MipsAsmParser::ParseOperand(OperandVector &Operands, StringRef Mnemonic) {
1433 DEBUG(dbgs() << "ParseOperand\n");
1435 // Check if the current operand has a custom associated parser, if so, try to
1436 // custom parse the operand, or fallback to the general approach.
1437 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1438 if (ResTy == MatchOperand_Success)
1440 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1441 // there was a match, but an error occurred, in which case, just return that
1442 // the operand parsing failed.
1443 if (ResTy == MatchOperand_ParseFail)
1446 DEBUG(dbgs() << ".. Generic Parser\n");
1448 switch (getLexer().getKind()) {
1450 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1452 case AsmToken::Dollar: {
1453 // Parse the register.
1454 SMLoc S = Parser.getTok().getLoc();
1456 // Almost all registers have been parsed by custom parsers. There is only
1457 // one exception to this. $zero (and it's alias $0) will reach this point
1458 // for div, divu, and similar instructions because it is not an operand
1459 // to the instruction definition but an explicit register. Special case
1460 // this situation for now.
1461 if (ParseAnyRegister(Operands) != MatchOperand_NoMatch)
1464 // Maybe it is a symbol reference.
1465 StringRef Identifier;
1466 if (Parser.parseIdentifier(Identifier))
1469 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1470 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1471 // Otherwise create a symbol reference.
1473 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1475 Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this));
1478 // Else drop to expression parsing.
1479 case AsmToken::LParen:
1480 case AsmToken::Minus:
1481 case AsmToken::Plus:
1482 case AsmToken::Integer:
1483 case AsmToken::String: {
1484 DEBUG(dbgs() << ".. generic integer\n");
1485 OperandMatchResultTy ResTy = ParseImm(Operands);
1486 return ResTy != MatchOperand_Success;
1488 case AsmToken::Percent: {
1489 // It is a symbol reference or constant expression.
1490 const MCExpr *IdVal;
1491 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1492 if (parseRelocOperand(IdVal))
1495 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1497 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1499 } // case AsmToken::Percent
1500 } // switch(getLexer().getKind())
1504 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1505 StringRef RelocStr) {
1507 // Check the type of the expression.
1508 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1509 // It's a constant, evaluate reloc value.
1511 switch (getVariantKind(RelocStr)) {
1512 case MCSymbolRefExpr::VK_Mips_ABS_LO:
1513 // Get the 1st 16-bits.
1514 Val = MCE->getValue() & 0xffff;
1516 case MCSymbolRefExpr::VK_Mips_ABS_HI:
1517 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1, to compensate for low
1518 // 16 bits being negative.
1519 Val = ((MCE->getValue() + 0x8000) >> 16) & 0xffff;
1521 case MCSymbolRefExpr::VK_Mips_HIGHER:
1522 // Get the 3rd 16-bits.
1523 Val = ((MCE->getValue() + 0x80008000LL) >> 32) & 0xffff;
1525 case MCSymbolRefExpr::VK_Mips_HIGHEST:
1526 // Get the 4th 16-bits.
1527 Val = ((MCE->getValue() + 0x800080008000LL) >> 48) & 0xffff;
1530 report_fatal_error("Unsupported reloc value!");
1532 return MCConstantExpr::Create(Val, getContext());
1535 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1536 // It's a symbol, create a symbolic expression from the symbol.
1537 StringRef Symbol = MSRE->getSymbol().getName();
1538 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1539 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1543 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1544 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1546 // Try to create target expression.
1547 if (MipsMCExpr::isSupportedBinaryExpr(VK, BE))
1548 return MipsMCExpr::Create(VK, Expr, getContext());
1550 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1551 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1552 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1556 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1557 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1558 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1561 // Just return the original expression.
1565 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1567 switch (Expr->getKind()) {
1568 case MCExpr::Constant:
1570 case MCExpr::SymbolRef:
1571 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1572 case MCExpr::Binary:
1573 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1574 if (!isEvaluated(BE->getLHS()))
1576 return isEvaluated(BE->getRHS());
1579 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1580 case MCExpr::Target:
1586 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1587 Parser.Lex(); // Eat the % token.
1588 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1589 if (Tok.isNot(AsmToken::Identifier))
1592 std::string Str = Tok.getIdentifier().str();
1594 Parser.Lex(); // Eat the identifier.
1595 // Now make an expression from the rest of the operand.
1596 const MCExpr *IdVal;
1599 if (getLexer().getKind() == AsmToken::LParen) {
1601 Parser.Lex(); // Eat the '(' token.
1602 if (getLexer().getKind() == AsmToken::Percent) {
1603 Parser.Lex(); // Eat the % token.
1604 const AsmToken &nextTok = Parser.getTok();
1605 if (nextTok.isNot(AsmToken::Identifier))
1608 Str += nextTok.getIdentifier();
1609 Parser.Lex(); // Eat the identifier.
1610 if (getLexer().getKind() != AsmToken::LParen)
1615 if (getParser().parseParenExpression(IdVal, EndLoc))
1618 while (getLexer().getKind() == AsmToken::RParen)
1619 Parser.Lex(); // Eat the ')' token.
1622 return true; // Parenthesis must follow the relocation operand.
1624 Res = evaluateRelocExpr(IdVal, Str);
1628 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1630 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
1631 OperandMatchResultTy ResTy = ParseAnyRegister(Operands);
1632 if (ResTy == MatchOperand_Success) {
1633 assert(Operands.size() == 1);
1634 MipsOperand &Operand = static_cast<MipsOperand &>(*Operands.front());
1635 StartLoc = Operand.getStartLoc();
1636 EndLoc = Operand.getEndLoc();
1638 // AFAIK, we only support numeric registers and named GPR's in CFI
1640 // Don't worry about eating tokens before failing. Using an unrecognised
1641 // register is a parse error.
1642 if (Operand.isGPRAsmReg()) {
1643 // Resolve to GPR32 or GPR64 appropriately.
1644 RegNo = isGP64() ? Operand.getGPR64Reg() : Operand.getGPR32Reg();
1647 return (RegNo == (unsigned)-1);
1650 assert(Operands.size() == 0);
1651 return (RegNo == (unsigned)-1);
1654 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1658 while (getLexer().getKind() == AsmToken::LParen)
1661 switch (getLexer().getKind()) {
1664 case AsmToken::Identifier:
1665 case AsmToken::LParen:
1666 case AsmToken::Integer:
1667 case AsmToken::Minus:
1668 case AsmToken::Plus:
1670 Result = getParser().parseParenExpression(Res, S);
1672 Result = (getParser().parseExpression(Res));
1673 while (getLexer().getKind() == AsmToken::RParen)
1676 case AsmToken::Percent:
1677 Result = parseRelocOperand(Res);
1682 MipsAsmParser::OperandMatchResultTy
1683 MipsAsmParser::parseMemOperand(OperandVector &Operands) {
1684 DEBUG(dbgs() << "parseMemOperand\n");
1685 const MCExpr *IdVal = nullptr;
1687 bool isParenExpr = false;
1688 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1689 // First operand is the offset.
1690 S = Parser.getTok().getLoc();
1692 if (getLexer().getKind() == AsmToken::LParen) {
1697 if (getLexer().getKind() != AsmToken::Dollar) {
1698 if (parseMemOffset(IdVal, isParenExpr))
1699 return MatchOperand_ParseFail;
1701 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1702 if (Tok.isNot(AsmToken::LParen)) {
1703 MipsOperand &Mnemonic = static_cast<MipsOperand &>(*Operands[0]);
1704 if (Mnemonic.getToken() == "la") {
1706 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1707 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1708 return MatchOperand_Success;
1710 if (Tok.is(AsmToken::EndOfStatement)) {
1712 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1714 // Zero register assumed, add a memory operand with ZERO as its base.
1715 // "Base" will be managed by k_Memory.
1716 auto Base = MipsOperand::CreateGPRReg(0, getContext().getRegisterInfo(),
1719 MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this));
1720 return MatchOperand_Success;
1722 Error(Parser.getTok().getLoc(), "'(' expected");
1723 return MatchOperand_ParseFail;
1726 Parser.Lex(); // Eat the '(' token.
1729 Res = ParseAnyRegister(Operands);
1730 if (Res != MatchOperand_Success)
1733 if (Parser.getTok().isNot(AsmToken::RParen)) {
1734 Error(Parser.getTok().getLoc(), "')' expected");
1735 return MatchOperand_ParseFail;
1738 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1740 Parser.Lex(); // Eat the ')' token.
1743 IdVal = MCConstantExpr::Create(0, getContext());
1745 // Replace the register operand with the memory operand.
1746 std::unique_ptr<MipsOperand> op(
1747 static_cast<MipsOperand *>(Operands.back().release()));
1748 // Remove the register from the operands.
1749 // "op" will be managed by k_Memory.
1750 Operands.pop_back();
1751 // Add the memory operand.
1752 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1754 if (IdVal->EvaluateAsAbsolute(Imm))
1755 IdVal = MCConstantExpr::Create(Imm, getContext());
1756 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1757 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1761 Operands.push_back(MipsOperand::CreateMem(std::move(op), IdVal, S, E, *this));
1762 return MatchOperand_Success;
1765 bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
1767 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1769 SMLoc S = Parser.getTok().getLoc();
1771 if (Sym->isVariable())
1772 Expr = Sym->getVariableValue();
1775 if (Expr->getKind() == MCExpr::SymbolRef) {
1776 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
1777 const StringRef DefSymbol = Ref->getSymbol().getName();
1778 if (DefSymbol.startswith("$")) {
1779 OperandMatchResultTy ResTy =
1780 MatchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S);
1781 if (ResTy == MatchOperand_Success) {
1784 } else if (ResTy == MatchOperand_ParseFail)
1785 llvm_unreachable("Should never ParseFail");
1788 } else if (Expr->getKind() == MCExpr::Constant) {
1790 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
1792 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc(), *this));
1799 MipsAsmParser::OperandMatchResultTy
1800 MipsAsmParser::MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
1801 StringRef Identifier,
1803 int Index = matchCPURegisterName(Identifier);
1805 Operands.push_back(MipsOperand::CreateGPRReg(
1806 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1807 return MatchOperand_Success;
1810 Index = matchFPURegisterName(Identifier);
1812 Operands.push_back(MipsOperand::CreateFGRReg(
1813 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1814 return MatchOperand_Success;
1817 Index = matchFCCRegisterName(Identifier);
1819 Operands.push_back(MipsOperand::CreateFCCReg(
1820 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1821 return MatchOperand_Success;
1824 Index = matchACRegisterName(Identifier);
1826 Operands.push_back(MipsOperand::CreateACCReg(
1827 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1828 return MatchOperand_Success;
1831 Index = matchMSA128RegisterName(Identifier);
1833 Operands.push_back(MipsOperand::CreateMSA128Reg(
1834 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1835 return MatchOperand_Success;
1838 Index = matchMSA128CtrlRegisterName(Identifier);
1840 Operands.push_back(MipsOperand::CreateMSACtrlReg(
1841 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1842 return MatchOperand_Success;
1845 return MatchOperand_NoMatch;
1848 MipsAsmParser::OperandMatchResultTy
1849 MipsAsmParser::MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) {
1850 auto Token = Parser.getLexer().peekTok(false);
1852 if (Token.is(AsmToken::Identifier)) {
1853 DEBUG(dbgs() << ".. identifier\n");
1854 StringRef Identifier = Token.getIdentifier();
1855 OperandMatchResultTy ResTy =
1856 MatchAnyRegisterNameWithoutDollar(Operands, Identifier, S);
1858 } else if (Token.is(AsmToken::Integer)) {
1859 DEBUG(dbgs() << ".. integer\n");
1860 Operands.push_back(MipsOperand::CreateNumericReg(
1861 Token.getIntVal(), getContext().getRegisterInfo(), S, Token.getLoc(),
1863 return MatchOperand_Success;
1866 DEBUG(dbgs() << Parser.getTok().getKind() << "\n");
1868 return MatchOperand_NoMatch;
1871 MipsAsmParser::OperandMatchResultTy
1872 MipsAsmParser::ParseAnyRegister(OperandVector &Operands) {
1873 DEBUG(dbgs() << "ParseAnyRegister\n");
1875 auto Token = Parser.getTok();
1877 SMLoc S = Token.getLoc();
1879 if (Token.isNot(AsmToken::Dollar)) {
1880 DEBUG(dbgs() << ".. !$ -> try sym aliasing\n");
1881 if (Token.is(AsmToken::Identifier)) {
1882 if (searchSymbolAlias(Operands))
1883 return MatchOperand_Success;
1885 DEBUG(dbgs() << ".. !symalias -> NoMatch\n");
1886 return MatchOperand_NoMatch;
1888 DEBUG(dbgs() << ".. $\n");
1890 OperandMatchResultTy ResTy = MatchAnyRegisterWithoutDollar(Operands, S);
1891 if (ResTy == MatchOperand_Success) {
1893 Parser.Lex(); // identifier
1898 MipsAsmParser::OperandMatchResultTy
1899 MipsAsmParser::ParseImm(OperandVector &Operands) {
1900 switch (getLexer().getKind()) {
1902 return MatchOperand_NoMatch;
1903 case AsmToken::LParen:
1904 case AsmToken::Minus:
1905 case AsmToken::Plus:
1906 case AsmToken::Integer:
1907 case AsmToken::String:
1911 const MCExpr *IdVal;
1912 SMLoc S = Parser.getTok().getLoc();
1913 if (getParser().parseExpression(IdVal))
1914 return MatchOperand_ParseFail;
1916 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1917 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1918 return MatchOperand_Success;
1921 MipsAsmParser::OperandMatchResultTy
1922 MipsAsmParser::ParseJumpTarget(OperandVector &Operands) {
1923 DEBUG(dbgs() << "ParseJumpTarget\n");
1925 SMLoc S = getLexer().getLoc();
1927 // Integers and expressions are acceptable
1928 OperandMatchResultTy ResTy = ParseImm(Operands);
1929 if (ResTy != MatchOperand_NoMatch)
1932 // Registers are a valid target and have priority over symbols.
1933 ResTy = ParseAnyRegister(Operands);
1934 if (ResTy != MatchOperand_NoMatch)
1937 const MCExpr *Expr = nullptr;
1938 if (Parser.parseExpression(Expr)) {
1939 // We have no way of knowing if a symbol was consumed so we must ParseFail
1940 return MatchOperand_ParseFail;
1943 MipsOperand::CreateImm(Expr, S, getLexer().getLoc(), *this));
1944 return MatchOperand_Success;
1947 MipsAsmParser::OperandMatchResultTy
1948 MipsAsmParser::parseInvNum(OperandVector &Operands) {
1949 const MCExpr *IdVal;
1950 // If the first token is '$' we may have register operand.
1951 if (Parser.getTok().is(AsmToken::Dollar))
1952 return MatchOperand_NoMatch;
1953 SMLoc S = Parser.getTok().getLoc();
1954 if (getParser().parseExpression(IdVal))
1955 return MatchOperand_ParseFail;
1956 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
1957 assert(MCE && "Unexpected MCExpr type.");
1958 int64_t Val = MCE->getValue();
1959 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1960 Operands.push_back(MipsOperand::CreateImm(
1961 MCConstantExpr::Create(0 - Val, getContext()), S, E, *this));
1962 return MatchOperand_Success;
1965 MipsAsmParser::OperandMatchResultTy
1966 MipsAsmParser::ParseLSAImm(OperandVector &Operands) {
1967 switch (getLexer().getKind()) {
1969 return MatchOperand_NoMatch;
1970 case AsmToken::LParen:
1971 case AsmToken::Plus:
1972 case AsmToken::Minus:
1973 case AsmToken::Integer:
1978 SMLoc S = Parser.getTok().getLoc();
1980 if (getParser().parseExpression(Expr))
1981 return MatchOperand_ParseFail;
1984 if (!Expr->EvaluateAsAbsolute(Val)) {
1985 Error(S, "expected immediate value");
1986 return MatchOperand_ParseFail;
1989 // The LSA instruction allows a 2-bit unsigned immediate. For this reason
1990 // and because the CPU always adds one to the immediate field, the allowed
1991 // range becomes 1..4. We'll only check the range here and will deal
1992 // with the addition/subtraction when actually decoding/encoding
1994 if (Val < 1 || Val > 4) {
1995 Error(S, "immediate not in range (1..4)");
1996 return MatchOperand_ParseFail;
2000 MipsOperand::CreateImm(Expr, S, Parser.getTok().getLoc(), *this));
2001 return MatchOperand_Success;
2004 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
2006 MCSymbolRefExpr::VariantKind VK =
2007 StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
2008 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
2009 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
2010 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
2011 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
2012 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
2013 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
2014 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
2015 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
2016 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
2017 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
2018 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
2019 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
2020 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
2021 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
2022 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
2023 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
2024 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
2025 .Case("got_hi", MCSymbolRefExpr::VK_Mips_GOT_HI16)
2026 .Case("got_lo", MCSymbolRefExpr::VK_Mips_GOT_LO16)
2027 .Case("call_hi", MCSymbolRefExpr::VK_Mips_CALL_HI16)
2028 .Case("call_lo", MCSymbolRefExpr::VK_Mips_CALL_LO16)
2029 .Case("higher", MCSymbolRefExpr::VK_Mips_HIGHER)
2030 .Case("highest", MCSymbolRefExpr::VK_Mips_HIGHEST)
2031 .Case("pcrel_hi", MCSymbolRefExpr::VK_Mips_PCREL_HI16)
2032 .Case("pcrel_lo", MCSymbolRefExpr::VK_Mips_PCREL_LO16)
2033 .Default(MCSymbolRefExpr::VK_None);
2035 assert(VK != MCSymbolRefExpr::VK_None);
2040 /// Sometimes (i.e. load/stores) the operand may be followed immediately by
2042 /// ::= '(', register, ')'
2043 /// handle it before we iterate so we don't get tripped up by the lack of
2045 bool MipsAsmParser::ParseParenSuffix(StringRef Name, OperandVector &Operands) {
2046 if (getLexer().is(AsmToken::LParen)) {
2048 MipsOperand::CreateToken("(", getLexer().getLoc(), *this));
2050 if (ParseOperand(Operands, Name)) {
2051 SMLoc Loc = getLexer().getLoc();
2052 Parser.eatToEndOfStatement();
2053 return Error(Loc, "unexpected token in argument list");
2055 if (Parser.getTok().isNot(AsmToken::RParen)) {
2056 SMLoc Loc = getLexer().getLoc();
2057 Parser.eatToEndOfStatement();
2058 return Error(Loc, "unexpected token, expected ')'");
2061 MipsOperand::CreateToken(")", getLexer().getLoc(), *this));
2067 /// Sometimes (i.e. in MSA) the operand may be followed immediately by
2068 /// either one of these.
2069 /// ::= '[', register, ']'
2070 /// ::= '[', integer, ']'
2071 /// handle it before we iterate so we don't get tripped up by the lack of
2073 bool MipsAsmParser::ParseBracketSuffix(StringRef Name,
2074 OperandVector &Operands) {
2075 if (getLexer().is(AsmToken::LBrac)) {
2077 MipsOperand::CreateToken("[", getLexer().getLoc(), *this));
2079 if (ParseOperand(Operands, Name)) {
2080 SMLoc Loc = getLexer().getLoc();
2081 Parser.eatToEndOfStatement();
2082 return Error(Loc, "unexpected token in argument list");
2084 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2085 SMLoc Loc = getLexer().getLoc();
2086 Parser.eatToEndOfStatement();
2087 return Error(Loc, "unexpected token, expected ']'");
2090 MipsOperand::CreateToken("]", getLexer().getLoc(), *this));
2096 bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2097 SMLoc NameLoc, OperandVector &Operands) {
2098 DEBUG(dbgs() << "ParseInstruction\n");
2099 // Check if we have valid mnemonic
2100 if (!mnemonicIsValid(Name, 0)) {
2101 Parser.eatToEndOfStatement();
2102 return Error(NameLoc, "Unknown instruction");
2104 // First operand in MCInst is instruction mnemonic.
2105 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this));
2107 // Read the remaining operands.
2108 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2109 // Read the first operand.
2110 if (ParseOperand(Operands, Name)) {
2111 SMLoc Loc = getLexer().getLoc();
2112 Parser.eatToEndOfStatement();
2113 return Error(Loc, "unexpected token in argument list");
2115 if (getLexer().is(AsmToken::LBrac) && ParseBracketSuffix(Name, Operands))
2117 // AFAIK, parenthesis suffixes are never on the first operand
2119 while (getLexer().is(AsmToken::Comma)) {
2120 Parser.Lex(); // Eat the comma.
2121 // Parse and remember the operand.
2122 if (ParseOperand(Operands, Name)) {
2123 SMLoc Loc = getLexer().getLoc();
2124 Parser.eatToEndOfStatement();
2125 return Error(Loc, "unexpected token in argument list");
2127 // Parse bracket and parenthesis suffixes before we iterate
2128 if (getLexer().is(AsmToken::LBrac)) {
2129 if (ParseBracketSuffix(Name, Operands))
2131 } else if (getLexer().is(AsmToken::LParen) &&
2132 ParseParenSuffix(Name, Operands))
2136 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2137 SMLoc Loc = getLexer().getLoc();
2138 Parser.eatToEndOfStatement();
2139 return Error(Loc, "unexpected token in argument list");
2141 Parser.Lex(); // Consume the EndOfStatement.
2145 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2146 SMLoc Loc = getLexer().getLoc();
2147 Parser.eatToEndOfStatement();
2148 return Error(Loc, ErrorMsg);
2151 bool MipsAsmParser::reportParseError(SMLoc Loc, StringRef ErrorMsg) {
2152 return Error(Loc, ErrorMsg);
2155 bool MipsAsmParser::parseSetNoAtDirective() {
2156 // Line should look like: ".set noat".
2158 Options.setATReg(0);
2161 // If this is not the end of the statement, report an error.
2162 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2163 reportParseError("unexpected token in statement");
2166 Parser.Lex(); // Consume the EndOfStatement.
2170 bool MipsAsmParser::parseSetAtDirective() {
2171 // Line can be .set at - defaults to $1
2175 if (getLexer().is(AsmToken::EndOfStatement)) {
2176 Options.setATReg(1);
2177 Parser.Lex(); // Consume the EndOfStatement.
2179 } else if (getLexer().is(AsmToken::Equal)) {
2180 getParser().Lex(); // Eat the '='.
2181 if (getLexer().isNot(AsmToken::Dollar)) {
2182 reportParseError("unexpected token in statement");
2185 Parser.Lex(); // Eat the '$'.
2186 const AsmToken &Reg = Parser.getTok();
2187 if (Reg.is(AsmToken::Identifier)) {
2188 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2189 } else if (Reg.is(AsmToken::Integer)) {
2190 AtRegNo = Reg.getIntVal();
2192 reportParseError("unexpected token in statement");
2196 if (AtRegNo < 0 || AtRegNo > 31) {
2197 reportParseError("unexpected token in statement");
2201 if (!Options.setATReg(AtRegNo)) {
2202 reportParseError("unexpected token in statement");
2205 getParser().Lex(); // Eat the register.
2207 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2208 reportParseError("unexpected token in statement");
2211 Parser.Lex(); // Consume the EndOfStatement.
2214 reportParseError("unexpected token in statement");
2219 bool MipsAsmParser::parseSetReorderDirective() {
2221 // If this is not the end of the statement, report an error.
2222 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2223 reportParseError("unexpected token in statement");
2226 Options.setReorder();
2227 getTargetStreamer().emitDirectiveSetReorder();
2228 Parser.Lex(); // Consume the EndOfStatement.
2232 bool MipsAsmParser::parseSetNoReorderDirective() {
2234 // If this is not the end of the statement, report an error.
2235 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2236 reportParseError("unexpected token in statement");
2239 Options.setNoreorder();
2240 getTargetStreamer().emitDirectiveSetNoReorder();
2241 Parser.Lex(); // Consume the EndOfStatement.
2245 bool MipsAsmParser::parseSetMacroDirective() {
2247 // If this is not the end of the statement, report an error.
2248 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2249 reportParseError("unexpected token in statement");
2253 Parser.Lex(); // Consume the EndOfStatement.
2257 bool MipsAsmParser::parseSetNoMacroDirective() {
2259 // If this is not the end of the statement, report an error.
2260 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2261 reportParseError("`noreorder' must be set before `nomacro'");
2264 if (Options.isReorder()) {
2265 reportParseError("`noreorder' must be set before `nomacro'");
2268 Options.setNomacro();
2269 Parser.Lex(); // Consume the EndOfStatement.
2273 bool MipsAsmParser::parseSetNoMips16Directive() {
2275 // If this is not the end of the statement, report an error.
2276 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2277 reportParseError("unexpected token in statement");
2280 // For now do nothing.
2281 Parser.Lex(); // Consume the EndOfStatement.
2285 bool MipsAsmParser::parseSetAssignment() {
2287 const MCExpr *Value;
2289 if (Parser.parseIdentifier(Name))
2290 reportParseError("expected identifier after .set");
2292 if (getLexer().isNot(AsmToken::Comma))
2293 return reportParseError("unexpected token in .set directive");
2296 if (Parser.parseExpression(Value))
2297 return reportParseError("expected valid expression after comma");
2299 // Check if the Name already exists as a symbol.
2300 MCSymbol *Sym = getContext().LookupSymbol(Name);
2302 return reportParseError("symbol already defined");
2303 Sym = getContext().GetOrCreateSymbol(Name);
2304 Sym->setVariableValue(Value);
2309 bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
2311 if (getLexer().isNot(AsmToken::EndOfStatement))
2312 return reportParseError("unexpected token in .set directive");
2316 llvm_unreachable("Unimplemented feature");
2317 case Mips::FeatureDSP:
2318 setFeatureBits(Mips::FeatureDSP, "dsp");
2319 getTargetStreamer().emitDirectiveSetDsp();
2321 case Mips::FeatureMicroMips:
2322 getTargetStreamer().emitDirectiveSetMicroMips();
2324 case Mips::FeatureMips16:
2325 getTargetStreamer().emitDirectiveSetMips16();
2327 case Mips::FeatureMips32r2:
2328 setFeatureBits(Mips::FeatureMips32r2, "mips32r2");
2329 getTargetStreamer().emitDirectiveSetMips32R2();
2331 case Mips::FeatureMips64:
2332 setFeatureBits(Mips::FeatureMips64, "mips64");
2333 getTargetStreamer().emitDirectiveSetMips64();
2335 case Mips::FeatureMips64r2:
2336 setFeatureBits(Mips::FeatureMips64r2, "mips64r2");
2337 getTargetStreamer().emitDirectiveSetMips64R2();
2343 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
2344 if (getLexer().isNot(AsmToken::Comma)) {
2345 SMLoc Loc = getLexer().getLoc();
2346 Parser.eatToEndOfStatement();
2347 return Error(Loc, ErrorStr);
2350 Parser.Lex(); // Eat the comma.
2354 bool MipsAsmParser::parseDirectiveCPLoad(SMLoc Loc) {
2355 if (Options.isReorder())
2356 Warning(Loc, ".cpload in reorder section");
2358 // FIXME: Warn if cpload is used in Mips16 mode.
2360 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg;
2361 OperandMatchResultTy ResTy = ParseAnyRegister(Reg);
2362 if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
2363 reportParseError("expected register containing function address");
2367 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]);
2368 if (!RegOpnd.isGPRAsmReg()) {
2369 reportParseError(RegOpnd.getStartLoc(), "invalid register");
2373 getTargetStreamer().emitDirectiveCpload(RegOpnd.getGPR32Reg());
2377 bool MipsAsmParser::parseDirectiveCPSetup() {
2380 bool SaveIsReg = true;
2382 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
2383 OperandMatchResultTy ResTy = ParseAnyRegister(TmpReg);
2384 if (ResTy == MatchOperand_NoMatch) {
2385 reportParseError("expected register containing function address");
2386 Parser.eatToEndOfStatement();
2390 MipsOperand &FuncRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
2391 if (!FuncRegOpnd.isGPRAsmReg()) {
2392 reportParseError(FuncRegOpnd.getStartLoc(), "invalid register");
2393 Parser.eatToEndOfStatement();
2397 FuncReg = FuncRegOpnd.getGPR32Reg();
2400 if (!eatComma("expected comma parsing directive"))
2403 ResTy = ParseAnyRegister(TmpReg);
2404 if (ResTy == MatchOperand_NoMatch) {
2405 const AsmToken &Tok = Parser.getTok();
2406 if (Tok.is(AsmToken::Integer)) {
2407 Save = Tok.getIntVal();
2411 reportParseError("expected save register or stack offset");
2412 Parser.eatToEndOfStatement();
2416 MipsOperand &SaveOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
2417 if (!SaveOpnd.isGPRAsmReg()) {
2418 reportParseError(SaveOpnd.getStartLoc(), "invalid register");
2419 Parser.eatToEndOfStatement();
2422 Save = SaveOpnd.getGPR32Reg();
2425 if (!eatComma("expected comma parsing directive"))
2429 if (Parser.parseIdentifier(Name))
2430 reportParseError("expected identifier");
2431 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2433 getTargetStreamer().emitDirectiveCpsetup(FuncReg, Save, *Sym, SaveIsReg);
2437 bool MipsAsmParser::parseDirectiveNaN() {
2438 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2439 const AsmToken &Tok = Parser.getTok();
2441 if (Tok.getString() == "2008") {
2443 getTargetStreamer().emitDirectiveNaN2008();
2445 } else if (Tok.getString() == "legacy") {
2447 getTargetStreamer().emitDirectiveNaNLegacy();
2451 // If we don't recognize the option passed to the .nan
2452 // directive (e.g. no option or unknown option), emit an error.
2453 reportParseError("invalid option in .nan directive");
2457 bool MipsAsmParser::parseDirectiveSet() {
2459 // Get the next token.
2460 const AsmToken &Tok = Parser.getTok();
2462 if (Tok.getString() == "noat") {
2463 return parseSetNoAtDirective();
2464 } else if (Tok.getString() == "at") {
2465 return parseSetAtDirective();
2466 } else if (Tok.getString() == "reorder") {
2467 return parseSetReorderDirective();
2468 } else if (Tok.getString() == "noreorder") {
2469 return parseSetNoReorderDirective();
2470 } else if (Tok.getString() == "macro") {
2471 return parseSetMacroDirective();
2472 } else if (Tok.getString() == "nomacro") {
2473 return parseSetNoMacroDirective();
2474 } else if (Tok.getString() == "mips16") {
2475 return parseSetFeature(Mips::FeatureMips16);
2476 } else if (Tok.getString() == "nomips16") {
2477 return parseSetNoMips16Directive();
2478 } else if (Tok.getString() == "nomicromips") {
2479 getTargetStreamer().emitDirectiveSetNoMicroMips();
2480 Parser.eatToEndOfStatement();
2482 } else if (Tok.getString() == "micromips") {
2483 return parseSetFeature(Mips::FeatureMicroMips);
2484 } else if (Tok.getString() == "mips32r2") {
2485 return parseSetFeature(Mips::FeatureMips32r2);
2486 } else if (Tok.getString() == "mips64") {
2487 return parseSetFeature(Mips::FeatureMips64);
2488 } else if (Tok.getString() == "mips64r2") {
2489 return parseSetFeature(Mips::FeatureMips64r2);
2490 } else if (Tok.getString() == "dsp") {
2491 return parseSetFeature(Mips::FeatureDSP);
2493 // It is just an identifier, look for an assignment.
2494 parseSetAssignment();
2501 /// parseDataDirective
2502 /// ::= .word [ expression (, expression)* ]
2503 bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) {
2504 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2506 const MCExpr *Value;
2507 if (getParser().parseExpression(Value))
2510 getParser().getStreamer().EmitValue(Value, Size);
2512 if (getLexer().is(AsmToken::EndOfStatement))
2515 // FIXME: Improve diagnostic.
2516 if (getLexer().isNot(AsmToken::Comma))
2517 return Error(L, "unexpected token in directive");
2526 /// parseDirectiveGpWord
2527 /// ::= .gpword local_sym
2528 bool MipsAsmParser::parseDirectiveGpWord() {
2529 const MCExpr *Value;
2530 // EmitGPRel32Value requires an expression, so we are using base class
2531 // method to evaluate the expression.
2532 if (getParser().parseExpression(Value))
2534 getParser().getStreamer().EmitGPRel32Value(Value);
2536 if (getLexer().isNot(AsmToken::EndOfStatement))
2537 return Error(getLexer().getLoc(), "unexpected token in directive");
2538 Parser.Lex(); // Eat EndOfStatement token.
2542 /// parseDirectiveGpDWord
2543 /// ::= .gpdword local_sym
2544 bool MipsAsmParser::parseDirectiveGpDWord() {
2545 const MCExpr *Value;
2546 // EmitGPRel64Value requires an expression, so we are using base class
2547 // method to evaluate the expression.
2548 if (getParser().parseExpression(Value))
2550 getParser().getStreamer().EmitGPRel64Value(Value);
2552 if (getLexer().isNot(AsmToken::EndOfStatement))
2553 return Error(getLexer().getLoc(), "unexpected token in directive");
2554 Parser.Lex(); // Eat EndOfStatement token.
2558 bool MipsAsmParser::parseDirectiveOption() {
2559 // Get the option token.
2560 AsmToken Tok = Parser.getTok();
2561 // At the moment only identifiers are supported.
2562 if (Tok.isNot(AsmToken::Identifier)) {
2563 Error(Parser.getTok().getLoc(), "unexpected token in .option directive");
2564 Parser.eatToEndOfStatement();
2568 StringRef Option = Tok.getIdentifier();
2570 if (Option == "pic0") {
2571 getTargetStreamer().emitDirectiveOptionPic0();
2573 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2574 Error(Parser.getTok().getLoc(),
2575 "unexpected token in .option pic0 directive");
2576 Parser.eatToEndOfStatement();
2581 if (Option == "pic2") {
2582 getTargetStreamer().emitDirectiveOptionPic2();
2584 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2585 Error(Parser.getTok().getLoc(),
2586 "unexpected token in .option pic2 directive");
2587 Parser.eatToEndOfStatement();
2593 Warning(Parser.getTok().getLoc(), "unknown option in .option directive");
2594 Parser.eatToEndOfStatement();
2598 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2599 StringRef IDVal = DirectiveID.getString();
2601 if (IDVal == ".cpload")
2602 return parseDirectiveCPLoad(DirectiveID.getLoc());
2603 if (IDVal == ".dword") {
2604 parseDataDirective(8, DirectiveID.getLoc());
2608 if (IDVal == ".ent") {
2609 // Ignore this directive for now.
2614 if (IDVal == ".end") {
2615 // Ignore this directive for now.
2620 if (IDVal == ".frame") {
2621 // Ignore this directive for now.
2622 Parser.eatToEndOfStatement();
2626 if (IDVal == ".set") {
2627 return parseDirectiveSet();
2630 if (IDVal == ".fmask") {
2631 // Ignore this directive for now.
2632 Parser.eatToEndOfStatement();
2636 if (IDVal == ".mask") {
2637 // Ignore this directive for now.
2638 Parser.eatToEndOfStatement();
2642 if (IDVal == ".nan")
2643 return parseDirectiveNaN();
2645 if (IDVal == ".gpword") {
2646 parseDirectiveGpWord();
2650 if (IDVal == ".gpdword") {
2651 parseDirectiveGpDWord();
2655 if (IDVal == ".word") {
2656 parseDataDirective(4, DirectiveID.getLoc());
2660 if (IDVal == ".option")
2661 return parseDirectiveOption();
2663 if (IDVal == ".abicalls") {
2664 getTargetStreamer().emitDirectiveAbiCalls();
2665 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2666 Error(Parser.getTok().getLoc(), "unexpected token in directive");
2668 Parser.eatToEndOfStatement();
2673 if (IDVal == ".cpsetup")
2674 return parseDirectiveCPSetup();
2679 extern "C" void LLVMInitializeMipsAsmParser() {
2680 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2681 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2682 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2683 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2686 #define GET_REGISTER_MATCHER
2687 #define GET_MATCHER_IMPLEMENTATION
2688 #include "MipsGenAsmMatcher.inc"