1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
27 // MSP430 Specific Node Definitions.
28 //===----------------------------------------------------------------------===//
29 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
30 [SDNPHasChain, SDNPOptInFlag]>;
32 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
34 //===----------------------------------------------------------------------===//
35 // Pseudo Instructions
36 //===----------------------------------------------------------------------===//
38 let neverHasSideEffects = 1 in
39 def NOP : Pseudo<(outs), (ins), "nop", []>;
41 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
45 // FIXME: Provide proper encoding!
46 let isReturn = 1, isTerminator = 1 in {
47 def RETI : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
50 //===----------------------------------------------------------------------===//
53 // FIXME: Provide proper encoding!
54 let neverHasSideEffects = 1 in {
55 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
56 "mov.w\t{$src, $dst|$dst, $src}",
60 // FIXME: Provide proper encoding!
61 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
62 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
63 "mov.w\t{$src, $dst|$dst, $src}",
64 [(set GR16:$dst, imm:$src)]>;
67 //===----------------------------------------------------------------------===//
68 // Arithmetic Instructions
70 let isTwoAddress = 1 in {
74 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
75 // FIXME: Provide proper encoding!
76 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
77 "add.w\t{$src2, $dst|$dst, $src2}",
78 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
82 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
83 "addc.w\t{$src2, $dst|$dst, $src2}",
84 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
89 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
90 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
91 "and.w\t{$src2, $dst|$dst, $src2}",
92 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
96 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
97 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
98 "xor.w\t{$src2, $dst|$dst, $src2}",
99 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
104 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
105 "sub.w\t{$src2, $dst|$dst, $src2}",
106 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
110 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
111 "subc.w\t{$src2, $dst|$dst, $src2}",
112 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
116 // FIXME: Provide proper encoding!
117 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
119 [(set GR16:$dst, (MSP430rra GR16:$src)),
122 } // isTwoAddress = 1