1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
28 def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
29 def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
30 def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>,
32 def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
35 //===----------------------------------------------------------------------===//
36 // MSP430 Specific Node Definitions.
37 //===----------------------------------------------------------------------===//
38 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
39 [SDNPHasChain, SDNPOptInFlag]>;
41 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
42 def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>;
43 def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>;
45 def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
46 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
47 def MSP430callseq_start :
48 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def MSP430callseq_end :
51 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
53 def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
54 def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp, [SDNPOutFlag]>;
55 def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC, [SDNPHasChain, SDNPInFlag]>;
56 def MSP430selectcc: SDNode<"MSP430ISD::SELECT_CC", SDT_MSP430SelectCC, [SDNPInFlag]>;
58 //===----------------------------------------------------------------------===//
59 // MSP430 Operand Definitions.
60 //===----------------------------------------------------------------------===//
63 def memsrc : Operand<i16> {
64 let PrintMethod = "printSrcMemOperand";
65 let MIOperandInfo = (ops GR16, i16imm);
68 def memdst : Operand<i16> {
69 let PrintMethod = "printSrcMemOperand";
70 let MIOperandInfo = (ops GR16, i16imm);
73 // Branch targets have OtherVT type.
74 def brtarget : Operand<OtherVT> {
75 let PrintMethod = "printPCRelImmOperand";
78 // Operand for printing out a condition code.
79 def cc : Operand<i8> {
80 let PrintMethod = "printCCOperand";
83 //===----------------------------------------------------------------------===//
84 // MSP430 Complex Pattern Definitions.
85 //===----------------------------------------------------------------------===//
87 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
89 //===----------------------------------------------------------------------===//
91 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
92 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
97 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
98 // a stack adjustment and the codegen must know that they may modify the stack
99 // pointer before prolog-epilog rewriting occurs.
100 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
101 // sub / add which can clobber SRW.
102 let Defs = [SPW, SRW], Uses = [SPW] in {
103 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
105 [(MSP430callseq_start timm:$amt)]>;
106 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
108 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
111 let usesCustomInserter = 1 in {
112 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cc),
115 (MSP430selectcc GR8:$src1, GR8:$src2, imm:$cc))]>;
116 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cc),
119 (MSP430selectcc GR16:$src1, GR16:$src2, imm:$cc))]>;
122 let neverHasSideEffects = 1 in
123 def NOP : Pseudo<(outs), (ins), "nop", []>;
125 //===----------------------------------------------------------------------===//
126 // Control Flow Instructions...
129 // FIXME: Provide proper encoding!
130 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
131 def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
134 let isBranch = 1, isTerminator = 1 in {
138 def JMP : Pseudo<(outs), (ins brtarget:$dst),
142 // Conditional branches
144 def JCC : Pseudo<(outs), (ins brtarget:$dst, cc:$cc),
146 [(MSP430brcc bb:$dst, imm:$cc)]>;
147 } // isBranch, isTerminator
149 //===----------------------------------------------------------------------===//
150 // Call Instructions...
153 // All calls clobber the non-callee saved registers. SPW is marked as
154 // a use to prevent stack-pointer assignments that appear immediately
155 // before calls from potentially appearing dead. Uses for argument
156 // registers are added manually.
157 let Defs = [R12W, R13W, R14W, R15W, SRW],
159 def CALLi : Pseudo<(outs), (ins i16imm:$dst, variable_ops),
160 "call\t$dst", [(MSP430call imm:$dst)]>;
161 def CALLr : Pseudo<(outs), (ins GR16:$dst, variable_ops),
162 "call\t$dst", [(MSP430call GR16:$dst)]>;
163 def CALLm : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
164 "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>;
168 //===----------------------------------------------------------------------===//
169 // Miscellaneous Instructions...
171 let Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in {
173 def POP16r : Pseudo<(outs GR16:$reg), (ins), "pop.w\t$reg", []>;
176 def PUSH16r : Pseudo<(outs), (ins GR16:$reg), "push.w\t$reg",[]>;
179 //===----------------------------------------------------------------------===//
182 // FIXME: Provide proper encoding!
183 let neverHasSideEffects = 1 in {
184 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
185 "mov.b\t{$src, $dst}",
187 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
188 "mov.w\t{$src, $dst}",
192 // FIXME: Provide proper encoding!
193 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
194 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
195 "mov.b\t{$src, $dst}",
196 [(set GR8:$dst, imm:$src)]>;
197 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
198 "mov.w\t{$src, $dst}",
199 [(set GR16:$dst, imm:$src)]>;
202 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
203 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
204 "mov.b\t{$src, $dst}",
205 [(set GR8:$dst, (load addr:$src))]>;
206 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
207 "mov.w\t{$src, $dst}",
208 [(set GR16:$dst, (load addr:$src))]>;
211 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
212 "mov.b\t{$src, $dst}",
213 [(set GR16:$dst, (zext GR8:$src))]>;
214 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
215 "mov.b\t{$src, $dst}",
216 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
218 let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb" in {
219 def MOV8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR16:$base),
220 "mov.b\t{@$base+, $dst}", []>;
221 def MOV16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$base),
222 "mov.w\t{@$base+, $dst}", []>;
225 // Any instruction that defines a 8-bit result leaves the high half of the
226 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
227 // be copying from a truncate, but any other 8-bit operation will zero-extend
229 def def8 : PatLeaf<(i8 GR8:$src), [{
230 return N->getOpcode() != ISD::TRUNCATE &&
231 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
232 N->getOpcode() != ISD::CopyFromReg;
235 // In the case of a 8-bit def that is known to implicitly zero-extend,
236 // we can use a SUBREG_TO_REG.
237 def : Pat<(i16 (zext def8:$src)),
238 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
241 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
242 "mov.b\t{$src, $dst}",
243 [(store (i8 imm:$src), addr:$dst)]>;
244 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
245 "mov.w\t{$src, $dst}",
246 [(store (i16 imm:$src), addr:$dst)]>;
248 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
249 "mov.b\t{$src, $dst}",
250 [(store GR8:$src, addr:$dst)]>;
251 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
252 "mov.w\t{$src, $dst}",
253 [(store GR16:$src, addr:$dst)]>;
255 def MOV8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
256 "mov.b\t{$src, $dst}",
257 [(store (i8 (load addr:$src)), addr:$dst)]>;
258 def MOV16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
259 "mov.w\t{$src, $dst}",
260 [(store (i16 (load addr:$src)), addr:$dst)]>;
262 //===----------------------------------------------------------------------===//
263 // Arithmetic Instructions
265 let isTwoAddress = 1 in {
267 let Defs = [SRW] in {
269 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
270 // FIXME: Provide proper encoding!
271 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
272 "add.b\t{$src2, $dst}",
273 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
275 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
276 "add.w\t{$src2, $dst}",
277 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
281 def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
282 "add.b\t{$src2, $dst}",
283 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
285 def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
286 "add.w\t{$src2, $dst}",
287 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
290 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
291 Constraints = "$base = $base_wb, $src1 = $dst" in {
292 def ADD8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
293 "add.b\t{@$base+, $dst}", []>;
294 def ADD16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
295 "add.w\t{@$base+, $dst}", []>;
299 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
300 "add.b\t{$src2, $dst}",
301 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
303 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
304 "add.w\t{$src2, $dst}",
305 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
308 let isTwoAddress = 0 in {
309 def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
310 "add.b\t{$src, $dst}",
311 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
313 def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
314 "add.w\t{$src, $dst}",
315 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
318 def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
319 "add.b\t{$src, $dst}",
320 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
322 def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
323 "add.w\t{$src, $dst}",
324 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
327 def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
328 "add.b\t{$src, $dst}",
329 [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
331 def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
332 "add.w\t{$src, $dst}",
333 [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
337 let Uses = [SRW] in {
339 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
340 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
341 "addc.b\t{$src2, $dst}",
342 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
344 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
345 "addc.w\t{$src2, $dst}",
346 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
350 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
351 "addc.b\t{$src2, $dst}",
352 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
354 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
355 "addc.w\t{$src2, $dst}",
356 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
359 def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
360 "addc.b\t{$src2, $dst}",
361 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
363 def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
364 "addc.w\t{$src2, $dst}",
365 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
368 let isTwoAddress = 0 in {
369 def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
370 "addc.b\t{$src, $dst}",
371 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
373 def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
374 "addc.w\t{$src, $dst}",
375 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
378 def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
379 "addc.b\t{$src, $dst}",
380 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
382 def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
383 "addc.w\t{$src, $dst}",
384 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
387 def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
388 "addc.b\t{$src, $dst}",
389 [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
391 def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
392 "addc.w\t{$src, $dst}",
393 [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
399 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
400 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
401 "and.b\t{$src2, $dst}",
402 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
404 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
405 "and.w\t{$src2, $dst}",
406 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
410 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
411 "and.b\t{$src2, $dst}",
412 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
414 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
415 "and.w\t{$src2, $dst}",
416 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
419 def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
420 "and.b\t{$src2, $dst}",
421 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
423 def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
424 "and.w\t{$src2, $dst}",
425 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
428 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
429 Constraints = "$base = $base_wb, $src1 = $dst" in {
430 def AND8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
431 "and.b\t{@$base+, $dst}", []>;
432 def AND16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
433 "and.w\t{@$base+, $dst}", []>;
436 let isTwoAddress = 0 in {
437 def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
438 "and.b\t{$src, $dst}",
439 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
441 def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
442 "and.w\t{$src, $dst}",
443 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
446 def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
447 "and.b\t{$src, $dst}",
448 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
450 def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
451 "and.w\t{$src, $dst}",
452 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
455 def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
456 "and.b\t{$src, $dst}",
457 [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
459 def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
460 "and.w\t{$src, $dst}",
461 [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
465 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
466 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
467 "bis.b\t{$src2, $dst}",
468 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
469 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
470 "bis.w\t{$src2, $dst}",
471 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
474 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
475 "bis.b\t{$src2, $dst}",
476 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
477 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
478 "bis.w\t{$src2, $dst}",
479 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
481 def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
482 "bis.b\t{$src2, $dst}",
483 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
484 def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
485 "bis.w\t{$src2, $dst}",
486 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
488 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
489 Constraints = "$base = $base_wb, $src1 = $dst" in {
490 def OR8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
491 "bis.b\t{@$base+, $dst}", []>;
492 def OR16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
493 "bis.w\t{@$base+, $dst}", []>;
496 let isTwoAddress = 0 in {
497 def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
498 "bis.b\t{$src, $dst}",
499 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
500 def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
501 "bis.w\t{$src, $dst}",
502 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>;
504 def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
505 "bis.b\t{$src, $dst}",
506 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>;
507 def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
508 "bis.w\t{$src, $dst}",
509 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>;
511 def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
512 "bis.b\t{$src, $dst}",
513 [(store (or (i8 (load addr:$dst)),
514 (i8 (load addr:$src))), addr:$dst)]>;
515 def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
516 "bis.w\t{$src, $dst}",
517 [(store (or (i16 (load addr:$dst)),
518 (i16 (load addr:$src))), addr:$dst)]>;
521 // bic does not modify condition codes
522 def BIC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
523 "bic.b\t{$src2, $dst}",
524 [(set GR8:$dst, (and GR8:$src1, (not GR8:$src2)))]>;
525 def BIC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
526 "bic.w\t{$src2, $dst}",
527 [(set GR16:$dst, (and GR16:$src1, (not GR16:$src2)))]>;
529 def BIC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
530 "bic.b\t{$src2, $dst}",
531 [(set GR8:$dst, (and GR8:$src1, (not (i8 (load addr:$src2)))))]>;
532 def BIC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
533 "bic.w\t{$src2, $dst}",
534 [(set GR16:$dst, (and GR16:$src1, (not (i16 (load addr:$src2)))))]>;
536 let isTwoAddress = 0 in {
537 def BIC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
538 "bic.b\t{$src, $dst}",
539 [(store (and (load addr:$dst), (not GR8:$src)), addr:$dst)]>;
540 def BIC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
541 "bic.w\t{$src, $dst}",
542 [(store (and (load addr:$dst), (not GR16:$src)), addr:$dst)]>;
544 def BIC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
545 "bic.b\t{$src, $dst}",
546 [(store (and (load addr:$dst), (not (i8 (load addr:$src)))), addr:$dst)]>;
547 def BIC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
548 "bic.w\t{$src, $dst}",
549 [(store (and (load addr:$dst), (not (i16 (load addr:$src)))), addr:$dst)]>;
552 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
553 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
554 "xor.b\t{$src2, $dst}",
555 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
557 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
558 "xor.w\t{$src2, $dst}",
559 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
563 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
564 "xor.b\t{$src2, $dst}",
565 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
567 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
568 "xor.w\t{$src2, $dst}",
569 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
572 def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
573 "xor.b\t{$src2, $dst}",
574 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
576 def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
577 "xor.w\t{$src2, $dst}",
578 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
581 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
582 Constraints = "$base = $base_wb, $src1 = $dst" in {
583 def XOR8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
584 "xor.b\t{@$base+, $dst}", []>;
585 def XOR16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
586 "xor.w\t{@$base+, $dst}", []>;
589 let isTwoAddress = 0 in {
590 def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
591 "xor.b\t{$src, $dst}",
592 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
594 def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
595 "xor.w\t{$src, $dst}",
596 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
599 def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
600 "xor.b\t{$src, $dst}",
601 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
603 def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
604 "xor.w\t{$src, $dst}",
605 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
608 def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
609 "xor.b\t{$src, $dst}",
610 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
612 def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
613 "xor.w\t{$src, $dst}",
614 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
619 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
620 "sub.b\t{$src2, $dst}",
621 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
623 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
624 "sub.w\t{$src2, $dst}",
625 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
628 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
629 "sub.b\t{$src2, $dst}",
630 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
632 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
633 "sub.w\t{$src2, $dst}",
634 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
637 def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
638 "sub.b\t{$src2, $dst}",
639 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
641 def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
642 "sub.w\t{$src2, $dst}",
643 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
646 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
647 Constraints = "$base = $base_wb, $src1 = $dst" in {
648 def SUB8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
649 "sub.b\t{@$base+, $dst}", []>;
650 def SUB16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
651 "sub.w\t{@$base+, $dst}", []>;
654 let isTwoAddress = 0 in {
655 def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
656 "sub.b\t{$src, $dst}",
657 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
659 def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
660 "sub.w\t{$src, $dst}",
661 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
664 def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
665 "sub.b\t{$src, $dst}",
666 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
668 def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
669 "sub.w\t{$src, $dst}",
670 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
673 def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
674 "sub.b\t{$src, $dst}",
675 [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
677 def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
678 "sub.w\t{$src, $dst}",
679 [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
683 let Uses = [SRW] in {
684 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
685 "subc.b\t{$src2, $dst}",
686 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
688 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
689 "subc.w\t{$src2, $dst}",
690 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
693 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
694 "subc.b\t{$src2, $dst}",
695 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
697 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
698 "subc.w\t{$src2, $dst}",
699 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
702 def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
703 "subc.b\t{$src2, $dst}",
704 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
706 def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
707 "subc.w\t{$src2, $dst}",
708 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
711 let isTwoAddress = 0 in {
712 def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
713 "subc.b\t{$src, $dst}",
714 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
716 def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
717 "subc.w\t{$src, $dst}",
718 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
721 def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
722 "subc.b\t{$src, $dst}",
723 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
725 def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
726 "subc.w\t{$src, $dst}",
727 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
730 def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
731 "subc.b\t{$src, $dst}",
732 [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
734 def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
735 "subc.w\t{$src, $dst}",
736 [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
742 // FIXME: Provide proper encoding!
743 def SAR8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
745 [(set GR8:$dst, (MSP430rra GR8:$src)),
747 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
749 [(set GR16:$dst, (MSP430rra GR16:$src)),
752 def SHL8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
754 [(set GR8:$dst, (MSP430rla GR8:$src)),
756 def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
758 [(set GR16:$dst, (MSP430rla GR16:$src)),
761 def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src),
764 [(set GR8:$dst, (MSP430rrc GR8:$src)),
766 def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
769 [(set GR16:$dst, (MSP430rrc GR16:$src)),
772 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
774 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
779 def ZEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
780 "mov.b\t{$src, $dst}",
781 [(set GR16:$dst, (zext (trunc GR16:$src)))]>;
783 def SWPB16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
785 [(set GR16:$dst, (bswap GR16:$src))]>;
787 } // isTwoAddress = 1
789 // Integer comparisons
790 let Defs = [SRW] in {
791 def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
792 "cmp.b\t{$src1, $src2}",
793 [(MSP430cmp GR8:$src1, GR8:$src2), (implicit SRW)]>;
794 def CMP16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
795 "cmp.w\t{$src1, $src2}",
796 [(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
798 def CMP8ir : Pseudo<(outs), (ins i8imm:$src1, GR8:$src2),
799 "cmp.b\t{$src1, $src2}",
800 [(MSP430cmp imm:$src1, GR8:$src2), (implicit SRW)]>;
801 def CMP16ir : Pseudo<(outs), (ins i16imm:$src1, GR16:$src2),
802 "cmp.w\t{$src1, $src2}",
803 [(MSP430cmp imm:$src1, GR16:$src2), (implicit SRW)]>;
805 def CMP8im : Pseudo<(outs), (ins i8imm:$src1, memsrc:$src2),
806 "cmp.b\t{$src1, $src2}",
807 [(MSP430cmp (i8 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
808 def CMP16im : Pseudo<(outs), (ins i16imm:$src1, memsrc:$src2),
809 "cmp.w\t{$src1, $src2}",
810 [(MSP430cmp (i16 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
812 def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
813 "cmp.b\t{$src1, $src2}",
814 [(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;
815 def CMP16rm : Pseudo<(outs), (ins GR16:$src1, memsrc:$src2),
816 "cmp.w\t{$src1, $src2}",
817 [(MSP430cmp GR16:$src1, (load addr:$src2)), (implicit SRW)]>;
819 def CMP8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
820 "cmp.b\t{$src1, $src2}",
821 [(MSP430cmp (load addr:$src1), GR8:$src2), (implicit SRW)]>;
822 def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
823 "cmp.w\t{$src1, $src2}",
824 [(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
826 def CMP8mi0 : Pseudo<(outs), (ins memsrc:$src1),
827 "cmp.b\t{$src1, #0}",
828 [(MSP430cmp (load addr:$src1), (i8 0)), (implicit SRW)]>;
829 def CMP16mi0: Pseudo<(outs), (ins memsrc:$src1),
830 "cmp.w\t{$src1, #0}",
831 [(MSP430cmp (load addr:$src1), (i16 0)), (implicit SRW)]>;
832 def CMP8mi1 : Pseudo<(outs), (ins memsrc:$src1),
833 "cmp.b\t{$src1, #1}",
834 [(MSP430cmp (load addr:$src1), (i8 1)), (implicit SRW)]>;
835 def CMP16mi1: Pseudo<(outs), (ins memsrc:$src1),
836 "cmp.w\t{$src1, #1}",
837 [(MSP430cmp (load addr:$src1), (i16 1)), (implicit SRW)]>;
838 def CMP8mi2 : Pseudo<(outs), (ins memsrc:$src1),
839 "cmp.b\t{$src1, #2}",
840 [(MSP430cmp (load addr:$src1), (i8 2)), (implicit SRW)]>;
841 def CMP16mi2: Pseudo<(outs), (ins memsrc:$src1),
842 "cmp.w\t{$src1, #2}",
843 [(MSP430cmp (load addr:$src1), (i16 2)), (implicit SRW)]>;
844 def CMP8mi4 : Pseudo<(outs), (ins memsrc:$src1),
845 "cmp.b\t{$src1, #4}",
846 [(MSP430cmp (load addr:$src1), (i8 4)), (implicit SRW)]>;
847 def CMP16mi4: Pseudo<(outs), (ins memsrc:$src1),
848 "cmp.w\t{$src1, #4}",
849 [(MSP430cmp (load addr:$src1), (i16 4)), (implicit SRW)]>;
850 def CMP8mi8 : Pseudo<(outs), (ins memsrc:$src1),
851 "cmp.b\t{$src1, #8}",
852 [(MSP430cmp (load addr:$src1), (i8 8)), (implicit SRW)]>;
853 def CMP16mi8: Pseudo<(outs), (ins memsrc:$src1),
854 "cmp.w\t{$src1, #8}",
855 [(MSP430cmp (load addr:$src1), (i16 8)), (implicit SRW)]>;
859 //===----------------------------------------------------------------------===//
860 // Non-Instruction Patterns
863 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
866 def : Pat<(anyext addr:$src), (MOVZX16rr8 GR8:$src)>;
869 def : Pat<(i8 (trunc GR16:$src)),
870 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
872 // GlobalAddress, ExternalSymbol
873 def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
874 def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>;
876 def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)),
877 (ADD16ri GR16:$src1, tglobaladdr:$src2)>;
878 def : Pat<(add GR16:$src1, (MSP430Wrapper texternalsym:$src2)),
879 (ADD16ri GR16:$src1, texternalsym:$src2)>;
881 def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst),
882 (MOV16mi addr:$dst, tglobaladdr:$src)>;
883 def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst),
884 (MOV16mi addr:$dst, texternalsym:$src)>;
887 def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
888 (CALLi tglobaladdr:$dst)>;
889 def : Pat<(MSP430call (i16 texternalsym:$dst)),
890 (CALLi texternalsym:$dst)>;
892 // add and sub always produce carry
893 def : Pat<(addc GR16:$src1, GR16:$src2),
894 (ADD16rr GR16:$src1, GR16:$src2)>;
895 def : Pat<(addc GR16:$src1, (load addr:$src2)),
896 (ADD16rm GR16:$src1, addr:$src2)>;
897 def : Pat<(addc GR16:$src1, imm:$src2),
898 (ADD16ri GR16:$src1, imm:$src2)>;
899 def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst),
900 (ADD16mr addr:$dst, GR16:$src)>;
901 def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
902 (ADD16mm addr:$dst, addr:$src)>;
904 def : Pat<(addc GR8:$src1, GR8:$src2),
905 (ADD8rr GR8:$src1, GR8:$src2)>;
906 def : Pat<(addc GR8:$src1, (load addr:$src2)),
907 (ADD8rm GR8:$src1, addr:$src2)>;
908 def : Pat<(addc GR8:$src1, imm:$src2),
909 (ADD8ri GR8:$src1, imm:$src2)>;
910 def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst),
911 (ADD8mr addr:$dst, GR8:$src)>;
912 def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
913 (ADD8mm addr:$dst, addr:$src)>;
915 def : Pat<(subc GR16:$src1, GR16:$src2),
916 (SUB16rr GR16:$src1, GR16:$src2)>;
917 def : Pat<(subc GR16:$src1, (load addr:$src2)),
918 (SUB16rm GR16:$src1, addr:$src2)>;
919 def : Pat<(subc GR16:$src1, imm:$src2),
920 (SUB16ri GR16:$src1, imm:$src2)>;
921 def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst),
922 (SUB16mr addr:$dst, GR16:$src)>;
923 def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
924 (SUB16mm addr:$dst, addr:$src)>;
926 def : Pat<(subc GR8:$src1, GR8:$src2),
927 (SUB8rr GR8:$src1, GR8:$src2)>;
928 def : Pat<(subc GR8:$src1, (load addr:$src2)),
929 (SUB8rm GR8:$src1, addr:$src2)>;
930 def : Pat<(subc GR8:$src1, imm:$src2),
931 (SUB8ri GR8:$src1, imm:$src2)>;
932 def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst),
933 (SUB8mr addr:$dst, GR8:$src)>;
934 def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
935 (SUB8mm addr:$dst, addr:$src)>;
938 def : Pat<(and GR16:$src, 255), (ZEXT16r GR16:$src)>;