1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
28 def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
29 def SDT_MSP430SetCC : SDTypeProfile<1, 2, [SDTCisVT<0, i8>,
30 SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
31 def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
32 def SDT_MSP430BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
33 SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
34 def SDT_MSP430Select : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
35 SDTCisVT<3, i8>, SDTCisVT<4, i16>]>;
36 def SDT_MSP430Clrc : SDTypeProfile<0, 0, []>;
38 //===----------------------------------------------------------------------===//
39 // MSP430 Specific Node Definitions.
40 //===----------------------------------------------------------------------===//
41 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
42 [SDNPHasChain, SDNPOptInFlag]>;
44 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
45 def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>;
46 def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, [SDNPInFlag]>;
48 def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
49 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
50 def MSP430callseq_start :
51 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
52 [SDNPHasChain, SDNPOutFlag]>;
53 def MSP430callseq_end :
54 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
56 def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
57 def MSP430setcc : SDNode<"MSP430ISD::SETCC", SDT_MSP430SetCC>;
58 def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp>;
59 def MSP430brcond : SDNode<"MSP430ISD::BRCOND", SDT_MSP430BrCond, [SDNPHasChain]>;
60 def MSP430select : SDNode<"MSP430ISD::SELECT", SDT_MSP430Select>;
61 def MSP430clrc : SDNode<"MSP430ISD::CLRC", SDT_MSP430Clrc, [SDNPOutFlag]>;
63 //===----------------------------------------------------------------------===//
64 // MSP430 Operand Definitions.
65 //===----------------------------------------------------------------------===//
68 def memsrc : Operand<i16> {
69 let PrintMethod = "printSrcMemOperand";
70 let MIOperandInfo = (ops GR16, i16imm);
73 def memdst : Operand<i16> {
74 let PrintMethod = "printSrcMemOperand";
75 let MIOperandInfo = (ops GR16, i16imm);
78 // Branch targets have OtherVT type.
79 def brtarget : Operand<OtherVT>;
81 // Operand for printing out a condition code.
82 def cc : Operand<i8> {
83 let PrintMethod = "printCCOperand";
86 //===----------------------------------------------------------------------===//
87 // MSP430 Complex Pattern Definitions.
88 //===----------------------------------------------------------------------===//
90 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
92 //===----------------------------------------------------------------------===//
94 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
95 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
97 //===----------------------------------------------------------------------===//
100 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
101 // a stack adjustment and the codegen must know that they may modify the stack
102 // pointer before prolog-epilog rewriting occurs.
103 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
104 // sub / add which can clobber SRW.
105 let Defs = [SPW, SRW], Uses = [SPW] in {
106 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
108 [(MSP430callseq_start timm:$amt)]>;
109 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
111 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
114 let usesCustomDAGSchedInserter = 1 in {
115 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cc),
118 (MSP430select GR16:$src1, GR16:$src2, imm:$cc, SRW))]>;
121 let neverHasSideEffects = 1 in
122 def NOP : Pseudo<(outs), (ins), "nop", []>;
124 //===----------------------------------------------------------------------===//
125 // Control Flow Instructions...
128 // FIXME: Provide proper encoding!
129 let isReturn = 1, isTerminator = 1 in {
130 def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
133 let isBranch = 1, isTerminator = 1 in {
137 def JMP : Pseudo<(outs), (ins brtarget:$dst),
141 // Conditional branches
143 def JCC : Pseudo<(outs), (ins brtarget:$dst, cc:$cc),
145 [(MSP430brcond bb:$dst, imm:$cc, SRW)]>;
146 } // isBranch, isTerminator
148 //===----------------------------------------------------------------------===//
149 // Call Instructions...
152 // All calls clobber the non-callee saved registers. SPW is marked as
153 // a use to prevent stack-pointer assignments that appear immediately
154 // before calls from potentially appearing dead. Uses for argument
155 // registers are added manually.
156 let Defs = [R12W, R13W, R14W, R15W, SRW],
158 def CALLi : Pseudo<(outs), (ins i16imm:$dst, variable_ops),
159 "call\t${dst:call}", [(MSP430call imm:$dst)]>;
160 def CALLr : Pseudo<(outs), (ins GR16:$dst, variable_ops),
161 "call\t$dst", [(MSP430call GR16:$dst)]>;
162 def CALLm : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
163 "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>;
167 //===----------------------------------------------------------------------===//
168 // Miscellaneous Instructions...
170 let Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in {
172 def POP16r : Pseudo<(outs GR16:$reg), (ins), "pop.w\t$reg", []>;
175 def PUSH16r : Pseudo<(outs), (ins GR16:$reg), "push.w\t$reg",[]>;
178 //===----------------------------------------------------------------------===//
181 // FIXME: Provide proper encoding!
182 let neverHasSideEffects = 1 in {
183 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
184 "mov.b\t{$src, $dst}",
186 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
187 "mov.w\t{$src, $dst}",
191 // FIXME: Provide proper encoding!
192 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
193 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
194 "mov.b\t{$src, $dst}",
195 [(set GR8:$dst, imm:$src)]>;
196 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
197 "mov.w\t{$src, $dst}",
198 [(set GR16:$dst, imm:$src)]>;
201 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
202 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
203 "mov.b\t{$src, $dst}",
204 [(set GR8:$dst, (load addr:$src))]>;
205 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
206 "mov.w\t{$src, $dst}",
207 [(set GR16:$dst, (load addr:$src))]>;
210 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
211 "mov.b\t{$src, $dst}",
212 [(set GR16:$dst, (zext GR8:$src))]>;
213 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
214 "mov.b\t{$src, $dst}",
215 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
217 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
218 "mov.b\t{$src, $dst}",
219 [(store (i8 imm:$src), addr:$dst)]>;
220 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
221 "mov.w\t{$src, $dst}",
222 [(store (i16 imm:$src), addr:$dst)]>;
224 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
225 "mov.b\t{$src, $dst}",
226 [(store GR8:$src, addr:$dst)]>;
227 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
228 "mov.w\t{$src, $dst}",
229 [(store GR16:$src, addr:$dst)]>;
231 //===----------------------------------------------------------------------===//
232 // Arithmetic Instructions
234 let isTwoAddress = 1 in {
236 let Defs = [SRW] in {
238 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
239 // FIXME: Provide proper encoding!
240 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
241 "add.b\t{$src2, $dst}",
242 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
244 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
245 "add.w\t{$src2, $dst}",
246 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
250 def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
251 "add.b\t{$src2, $dst}",
252 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
254 def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
255 "add.w\t{$src2, $dst}",
256 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
259 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
260 "add.b\t{$src2, $dst}",
261 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
263 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
264 "add.w\t{$src2, $dst}",
265 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
268 let isTwoAddress = 0 in {
269 def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
270 "add.b\t{$src, $dst}",
271 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
273 def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
274 "add.w\t{$src, $dst}",
275 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
278 def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
279 "add.b\t{$src, $dst}",
280 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
282 def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
283 "add.w\t{$src, $dst}",
284 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
287 def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
288 "add.b\t{$src, $dst}",
289 [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
291 def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
292 "add.w\t{$src, $dst}",
293 [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
297 let Uses = [SRW] in {
299 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
300 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
301 "addc.b\t{$src2, $dst}",
302 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
304 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
305 "addc.w\t{$src2, $dst}",
306 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
310 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
311 "addc.b\t{$src2, $dst}",
312 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
314 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
315 "addc.w\t{$src2, $dst}",
316 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
319 def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
320 "addc.b\t{$src2, $dst}",
321 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
323 def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
324 "addc.w\t{$src2, $dst}",
325 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
328 let isTwoAddress = 0 in {
329 def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
330 "addc.b\t{$src, $dst}",
331 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
333 def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
334 "addc.w\t{$src, $dst}",
335 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
338 def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
339 "addc.b\t{$src, $dst}",
340 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
342 def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
343 "addc.w\t{$src, $dst}",
344 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
347 def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
348 "addc.b\t{$src, $dst}",
349 [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
351 def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
352 "addc.w\t{$src, $dst}",
353 [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
359 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
360 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
361 "and.b\t{$src2, $dst}",
362 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
364 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
365 "and.w\t{$src2, $dst}",
366 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
370 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
371 "and.b\t{$src2, $dst}",
372 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
374 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
375 "and.w\t{$src2, $dst}",
376 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
379 def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
380 "and.b\t{$src2, $dst}",
381 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
383 def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
384 "and.w\t{$src2, $dst}",
385 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
388 let isTwoAddress = 0 in {
389 def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
390 "and.b\t{$src, $dst}",
391 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
393 def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
394 "and.w\t{$src, $dst}",
395 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
398 def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
399 "and.b\t{$src, $dst}",
400 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
402 def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
403 "and.w\t{$src, $dst}",
404 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
407 def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
408 "and.b\t{$src, $dst}",
409 [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
411 def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
412 "and.w\t{$src, $dst}",
413 [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
418 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
419 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
420 "xor.b\t{$src2, $dst}",
421 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
423 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
424 "xor.w\t{$src2, $dst}",
425 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
429 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
430 "xor.b\t{$src2, $dst}",
431 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
433 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
434 "xor.w\t{$src2, $dst}",
435 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
438 def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
439 "xor.b\t{$src2, $dst}",
440 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
442 def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
443 "xor.w\t{$src2, $dst}",
444 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
447 let isTwoAddress = 0 in {
448 def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
449 "xor.b\t{$src, $dst}",
450 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
452 def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
453 "xor.w\t{$src, $dst}",
454 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
457 def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
458 "xor.b\t{$src, $dst}",
459 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
461 def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
462 "xor.w\t{$src, $dst}",
463 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
466 def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
467 "xor.b\t{$src, $dst}",
468 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
470 def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
471 "xor.w\t{$src, $dst}",
472 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
477 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
478 "sub.b\t{$src2, $dst}",
479 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
481 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
482 "sub.w\t{$src2, $dst}",
483 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
486 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
487 "sub.b\t{$src2, $dst}",
488 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
490 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
491 "sub.w\t{$src2, $dst}",
492 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
495 def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
496 "sub.b\t{$src2, $dst}",
497 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
499 def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
500 "sub.w\t{$src2, $dst}",
501 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
504 let isTwoAddress = 0 in {
505 def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
506 "sub.b\t{$src, $dst}",
507 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
509 def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
510 "sub.w\t{$src, $dst}",
511 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
514 def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
515 "sub.b\t{$src, $dst}",
516 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
518 def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
519 "sub.w\t{$src, $dst}",
520 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
523 def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
524 "sub.b\t{$src, $dst}",
525 [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
527 def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
528 "sub.w\t{$src, $dst}",
529 [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
533 let Uses = [SRW] in {
534 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
535 "subc.b\t{$src2, $dst}",
536 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
538 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
539 "subc.w\t{$src2, $dst}",
540 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
543 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
544 "subc.b\t{$src2, $dst}",
545 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
547 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
548 "subc.w\t{$src2, $dst}",
549 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
552 def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
553 "subc.b\t{$src2, $dst}",
554 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
556 def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
557 "subc.w\t{$src2, $dst}",
558 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
561 let isTwoAddress = 0 in {
562 def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
563 "subc.b\t{$src, $dst}",
564 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
566 def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
567 "subc.w\t{$src, $dst}",
568 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
571 def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
572 "subc.b\t{$src, $dst}",
573 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
575 def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
576 "subc.w\t{$src, $dst}",
577 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
580 def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
581 "subc.b\t{$src, $dst}",
582 [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
584 def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
585 "subc.w\t{$src, $dst}",
586 [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
592 // FIXME: Provide proper encoding!
593 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
595 [(set GR16:$dst, (MSP430rra GR16:$src)),
598 def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
600 [(set GR16:$dst, (MSP430rla GR16:$src)),
603 def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
605 [(set GR16:$dst, (MSP430rrc GR16:$src)),
608 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
610 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
615 def SWPB16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
617 [(set GR16:$dst, (bswap GR16:$src))]>;
619 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
620 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
621 "bis.b\t{$src2, $dst}",
622 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
623 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
624 "bis.w\t{$src2, $dst}",
625 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
628 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
629 "bis.b\t{$src2, $dst}",
630 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
631 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
632 "bis.w\t{$src2, $dst}",
633 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
635 def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
636 "bis.b\t{$src2, $dst}",
637 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
638 def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
639 "bis.w\t{$src2, $dst}",
640 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
642 let isTwoAddress = 0 in {
643 def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
644 "bis.b\t{$src, $dst}",
645 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
647 def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
648 "bis.w\t{$src, $dst}",
649 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
652 def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
653 "bis.b\t{$src, $dst}",
654 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
656 def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
657 "bis.w\t{$src, $dst}",
658 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
661 def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
662 "bis.b\t{$src, $dst}",
663 [(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
665 def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
666 "bis.w\t{$src, $dst}",
667 [(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
671 } // isTwoAddress = 1
674 def CLRC : Pseudo<(outs), (ins),
675 "clrc", [(MSP430clrc)]>;
677 // Integer comparisons
678 let Defs = [SRW] in {
679 def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
680 "cmp.b\t{$src1, $src2}",
681 [(MSP430cmp GR8:$src1, GR8:$src2), (implicit SRW)]>;
682 def CMP16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
683 "cmp.w\t{$src1, $src2}",
684 [(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
686 def CMP8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2),
687 "cmp.b\t{$src1, $src2}",
688 [(MSP430cmp GR8:$src1, imm:$src2), (implicit SRW)]>;
689 def CMP16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
690 "cmp.w\t{$src1, $src2}",
691 [(MSP430cmp GR16:$src1, imm:$src2), (implicit SRW)]>;
693 def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
694 "cmp.b\t{$src1, $src2}",
695 [(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;
696 def CMP16rm : Pseudo<(outs), (ins GR16:$src1, memsrc:$src2),
697 "cmp.w\t{$src1, $src2}",
698 [(MSP430cmp GR16:$src1, (load addr:$src2)), (implicit SRW)]>;
700 def CMP8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
701 "cmp.b\t{$src1, $src2}",
702 [(MSP430cmp (load addr:$src1), GR8:$src2), (implicit SRW)]>;
703 def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
704 "cmp.w\t{$src1, $src2}",
705 [(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
707 def CMP8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2),
708 "cmp.b\t{$src1, $src2}",
709 [(MSP430cmp (load addr:$src1), (i8 imm:$src2)), (implicit SRW)]>;
710 def CMP16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2),
711 "cmp.w\t{$src1, $src2}",
712 [(MSP430cmp (load addr:$src1), (i16 imm:$src2)), (implicit SRW)]>;
714 def CMP8mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
715 "cmp.b\t{$src1, $src2}",
716 [(MSP430cmp (load addr:$src1), (i8 (load addr:$src2))), (implicit SRW)]>;
717 def CMP16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
718 "cmp.w\t{$src1, $src2}",
719 [(MSP430cmp (load addr:$src1), (i16 (load addr:$src2))), (implicit SRW)]>;
722 //===----------------------------------------------------------------------===//
723 // Non-Instruction Patterns
726 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
729 def : Pat<(anyext addr:$src), (MOVZX16rr8 GR8:$src)>;
732 def : Pat<(i8 (trunc GR16:$src)),
733 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
735 // GlobalAddress, ExternalSymbol
736 def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
737 def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>;
739 def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)),
740 (ADD16ri GR16:$src1, tglobaladdr:$src2)>;
741 def : Pat<(add GR16:$src1, (MSP430Wrapper texternalsym:$src2)),
742 (ADD16ri GR16:$src1, texternalsym:$src2)>;
744 def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst),
745 (MOV16mi addr:$dst, tglobaladdr:$src)>;
746 def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst),
747 (MOV16mi addr:$dst, texternalsym:$src)>;
750 def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
751 (CALLi tglobaladdr:$dst)>;
752 def : Pat<(MSP430call (i16 texternalsym:$dst)),
753 (CALLi texternalsym:$dst)>;
755 // add and sub always produce carry
756 def : Pat<(addc GR16:$src1, GR16:$src2),
757 (ADD16rr GR16:$src1, GR16:$src2)>;
758 def : Pat<(addc GR16:$src1, (load addr:$src2)),
759 (ADD16rm GR16:$src1, addr:$src2)>;
760 def : Pat<(addc GR16:$src1, imm:$src2),
761 (ADD16ri GR16:$src1, imm:$src2)>;
762 def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst),
763 (ADD16mr addr:$dst, GR16:$src)>;
764 def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
765 (ADD16mm addr:$dst, addr:$src)>;
767 def : Pat<(addc GR8:$src1, GR8:$src2),
768 (ADD8rr GR8:$src1, GR8:$src2)>;
769 def : Pat<(addc GR8:$src1, (load addr:$src2)),
770 (ADD8rm GR8:$src1, addr:$src2)>;
771 def : Pat<(addc GR8:$src1, imm:$src2),
772 (ADD8ri GR8:$src1, imm:$src2)>;
773 def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst),
774 (ADD8mr addr:$dst, GR8:$src)>;
775 def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
776 (ADD8mm addr:$dst, addr:$src)>;
778 def : Pat<(subc GR16:$src1, GR16:$src2),
779 (SUB16rr GR16:$src1, GR16:$src2)>;
780 def : Pat<(subc GR16:$src1, (load addr:$src2)),
781 (SUB16rm GR16:$src1, addr:$src2)>;
782 def : Pat<(subc GR16:$src1, imm:$src2),
783 (SUB16ri GR16:$src1, imm:$src2)>;
784 def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst),
785 (SUB16mr addr:$dst, GR16:$src)>;
786 def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
787 (SUB16mm addr:$dst, addr:$src)>;
789 def : Pat<(subc GR8:$src1, GR8:$src2),
790 (SUB8rr GR8:$src1, GR8:$src2)>;
791 def : Pat<(subc GR8:$src1, (load addr:$src2)),
792 (SUB8rm GR8:$src1, addr:$src2)>;
793 def : Pat<(subc GR8:$src1, imm:$src2),
794 (SUB8ri GR8:$src1, imm:$src2)>;
795 def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst),
796 (SUB8mr addr:$dst, GR8:$src)>;
797 def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
798 (SUB8mm addr:$dst, addr:$src)>;