1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
27 // MSP430 Specific Node Definitions.
28 //===----------------------------------------------------------------------===//
29 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
30 [SDNPHasChain, SDNPOptInFlag]>;
32 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
34 //===----------------------------------------------------------------------===//
35 // MSP430 Operand Definitions.
36 //===----------------------------------------------------------------------===//
39 def memsrc : Operand<i16> {
40 let PrintMethod = "printSrcMemOperand";
41 let MIOperandInfo = (ops i16imm, GR16);
44 def memdst : Operand<i16> {
45 let PrintMethod = "printSrcMemOperand";
46 let MIOperandInfo = (ops i16imm, GR16);
50 //===----------------------------------------------------------------------===//
51 // MSP430 Complex Pattern Definitions.
52 //===----------------------------------------------------------------------===//
54 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
56 //===----------------------------------------------------------------------===//
58 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
59 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
61 //===----------------------------------------------------------------------===//
62 // Pseudo Instructions
64 let neverHasSideEffects = 1 in
65 def NOP : Pseudo<(outs), (ins), "nop", []>;
67 //===----------------------------------------------------------------------===//
70 // FIXME: Provide proper encoding!
71 let isReturn = 1, isTerminator = 1 in {
72 def RETI : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
75 //===----------------------------------------------------------------------===//
78 // FIXME: Provide proper encoding!
79 let neverHasSideEffects = 1 in {
80 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
81 "mov.b\t{$src, $dst|$dst, $src}",
83 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
84 "mov.w\t{$src, $dst|$dst, $src}",
88 // FIXME: Provide proper encoding!
89 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
90 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
91 "mov.b\t{$src, $dst|$dst, $src}",
92 [(set GR8:$dst, imm:$src)]>;
93 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
94 "mov.w\t{$src, $dst|$dst, $src}",
95 [(set GR16:$dst, imm:$src)]>;
98 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
99 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
100 "mov.b\t{$src, $dst|$dst, $src}",
101 [(set GR8:$dst, (load addr:$src))]>;
102 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
103 "mov.w\t{$src, $dst|$dst, $src}",
104 [(set GR16:$dst, (load addr:$src))]>;
107 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
108 "mov.b\t{$src, $dst|$dst, $src}",
109 [(set GR16:$dst, (zext GR8:$src))]>;
110 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
111 "mov.b\t{$src, $dst|$dst, $src}",
112 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
114 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
115 "mov.b\t{$src, $dst|$dst, $src}",
116 [(store (i8 imm:$src), addr:$dst)]>;
117 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
118 "mov.w\t{$src, $dst|$dst, $src}",
119 [(store (i16 imm:$src), addr:$dst)]>;
121 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
122 "mov.b\t{$src, $dst|$dst, $src}",
123 [(store GR8:$src, addr:$dst)]>;
124 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
125 "mov.w\t{$src, $dst|$dst, $src}",
126 [(store GR16:$src, addr:$dst)]>;
128 //===----------------------------------------------------------------------===//
129 // Arithmetic Instructions
131 let isTwoAddress = 1 in {
133 let Defs = [SRW] in {
135 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
136 // FIXME: Provide proper encoding!
137 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
138 "add.w\t{$src2, $dst|$dst, $src2}",
139 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
142 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
143 "add.b\t{$src2, $dst|$dst, $src2}",
144 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
148 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
149 "add.w\t{$src2, $dst|$dst, $src2}",
150 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
152 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
153 "add.b\t{$src2, $dst|$dst, $src2}",
154 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
157 let Uses = [SRW] in {
159 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
160 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
161 "addc.w\t{$src2, $dst|$dst, $src2}",
162 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
164 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
165 "addc.b\t{$src2, $dst|$dst, $src2}",
166 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
170 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
171 "addc.w\t{$src2, $dst|$dst, $src2}",
172 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
174 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
175 "addc.b\t{$src2, $dst|$dst, $src2}",
176 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
180 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
181 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
182 "and.w\t{$src2, $dst|$dst, $src2}",
183 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
185 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
186 "and.b\t{$src2, $dst|$dst, $src2}",
187 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
191 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
192 "and.w\t{$src2, $dst|$dst, $src2}",
193 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
195 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
196 "and.b\t{$src2, $dst|$dst, $src2}",
197 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
200 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
201 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
202 "xor.w\t{$src2, $dst|$dst, $src2}",
203 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
205 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
206 "xor.b\t{$src2, $dst|$dst, $src2}",
207 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
211 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
212 "xor.w\t{$src2, $dst|$dst, $src2}",
213 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
215 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
216 "xor.b\t{$src2, $dst|$dst, $src2}",
217 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
221 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
222 "sub.w\t{$src2, $dst|$dst, $src2}",
223 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
225 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
226 "sub.b\t{$src2, $dst|$dst, $src2}",
227 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
230 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
231 "sub.w\t{$src2, $dst|$dst, $src2}",
232 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
234 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
235 "sub.b\t{$src2, $dst|$dst, $src2}",
236 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
239 let Uses = [SRW] in {
240 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
241 "subc.w\t{$src2, $dst|$dst, $src2}",
242 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
244 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
245 "subc.b\t{$src2, $dst|$dst, $src2}",
246 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
249 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
250 "subc.w\t{$src2, $dst|$dst, $src2}",
251 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
253 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
254 "subc.b\t{$src2, $dst|$dst, $src2}",
255 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
259 // FIXME: Provide proper encoding!
260 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
262 [(set GR16:$dst, (MSP430rra GR16:$src)),
265 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
267 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
272 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
273 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
274 "bis.w\t{$src2, $dst|$dst, $src2}",
275 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
276 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
277 "bis.b\t{$src2, $dst|$dst, $src2}",
278 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
281 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
282 "bis.w\t{$src2, $dst|$dst, $src2}",
283 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
284 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
285 "bis.b\t{$src2, $dst|$dst, $src2}",
286 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
288 } // isTwoAddress = 1
290 //===----------------------------------------------------------------------===//
291 // Non-Instruction Patterns
294 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
297 def : Pat<(i8 (trunc GR16:$src)),
298 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;