1 //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430InstrInfo.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "MSP430GenInstrInfo.inc"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/ErrorHandling.h"
28 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
29 : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
30 RI(tm, *this), TM(tm) {}
32 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
33 MachineBasicBlock::iterator MI,
34 unsigned SrcReg, bool isKill, int FrameIdx,
35 const TargetRegisterClass *RC,
36 const TargetRegisterInfo *TRI) const {
38 if (MI != MBB.end()) DL = MI->getDebugLoc();
39 MachineFunction &MF = *MBB.getParent();
40 MachineFrameInfo &MFI = *MF.getFrameInfo();
42 MachineMemOperand *MMO =
43 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
44 MachineMemOperand::MOStore, 0,
45 MFI.getObjectSize(FrameIdx),
46 MFI.getObjectAlignment(FrameIdx));
48 if (RC == &MSP430::GR16RegClass)
49 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
50 .addFrameIndex(FrameIdx).addImm(0)
51 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
52 else if (RC == &MSP430::GR8RegClass)
53 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
54 .addFrameIndex(FrameIdx).addImm(0)
55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
57 llvm_unreachable("Cannot store this register to stack slot!");
60 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MI,
62 unsigned DestReg, int FrameIdx,
63 const TargetRegisterClass *RC,
64 const TargetRegisterInfo *TRI) const{
66 if (MI != MBB.end()) DL = MI->getDebugLoc();
67 MachineFunction &MF = *MBB.getParent();
68 MachineFrameInfo &MFI = *MF.getFrameInfo();
70 MachineMemOperand *MMO =
71 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
72 MachineMemOperand::MOLoad, 0,
73 MFI.getObjectSize(FrameIdx),
74 MFI.getObjectAlignment(FrameIdx));
76 if (RC == &MSP430::GR16RegClass)
77 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
78 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
79 else if (RC == &MSP430::GR8RegClass)
80 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
81 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
83 llvm_unreachable("Cannot store this register to stack slot!");
86 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator I, DebugLoc DL,
88 unsigned DestReg, unsigned SrcReg,
91 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
92 Opc = MSP430::MOV16rr;
93 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
96 llvm_unreachable("Impossible reg-to-reg copy");
98 BuildMI(MBB, I, DL, get(Opc), DestReg)
99 .addReg(SrcReg, getKillRegState(KillSrc));
103 MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
104 unsigned &SrcReg, unsigned &DstReg,
105 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
106 SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
108 switch (MI.getOpcode()) {
112 case MSP430::MOV16rr:
113 assert(MI.getNumOperands() >= 2 &&
114 MI.getOperand(0).isReg() &&
115 MI.getOperand(1).isReg() &&
116 "invalid register-register move instruction");
117 SrcReg = MI.getOperand(1).getReg();
118 DstReg = MI.getOperand(0).getReg();
124 MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator MI,
126 const std::vector<CalleeSavedInfo> &CSI,
127 const TargetRegisterInfo *TRI) const {
132 if (MI != MBB.end()) DL = MI->getDebugLoc();
134 MachineFunction &MF = *MBB.getParent();
135 MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>();
136 MFI->setCalleeSavedFrameSize(CSI.size() * 2);
138 for (unsigned i = CSI.size(); i != 0; --i) {
139 unsigned Reg = CSI[i-1].getReg();
140 // Add the callee-saved register as live-in. It's killed at the spill.
142 BuildMI(MBB, MI, DL, get(MSP430::PUSH16r))
143 .addReg(Reg, RegState::Kill);
149 MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
150 MachineBasicBlock::iterator MI,
151 const std::vector<CalleeSavedInfo> &CSI,
152 const TargetRegisterInfo *TRI) const {
157 if (MI != MBB.end()) DL = MI->getDebugLoc();
159 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
160 BuildMI(MBB, MI, DL, get(MSP430::POP16r), CSI[i].getReg());
165 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
166 MachineBasicBlock::iterator I = MBB.end();
169 while (I != MBB.begin()) {
171 if (I->isDebugValue())
173 if (I->getOpcode() != MSP430::JMP &&
174 I->getOpcode() != MSP430::JCC &&
175 I->getOpcode() != MSP430::Br &&
176 I->getOpcode() != MSP430::Bm)
178 // Remove the branch.
179 I->eraseFromParent();
187 bool MSP430InstrInfo::
188 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
189 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
191 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
195 assert(0 && "Invalid branch condition!");
197 case MSP430CC::COND_E:
198 CC = MSP430CC::COND_NE;
200 case MSP430CC::COND_NE:
201 CC = MSP430CC::COND_E;
203 case MSP430CC::COND_L:
204 CC = MSP430CC::COND_GE;
206 case MSP430CC::COND_GE:
207 CC = MSP430CC::COND_L;
209 case MSP430CC::COND_HS:
210 CC = MSP430CC::COND_LO;
212 case MSP430CC::COND_LO:
213 CC = MSP430CC::COND_HS;
221 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
222 const TargetInstrDesc &TID = MI->getDesc();
223 if (!TID.isTerminator()) return false;
225 // Conditional branch is a special case.
226 if (TID.isBranch() && !TID.isBarrier())
228 if (!TID.isPredicable())
230 return !isPredicated(MI);
233 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
234 MachineBasicBlock *&TBB,
235 MachineBasicBlock *&FBB,
236 SmallVectorImpl<MachineOperand> &Cond,
237 bool AllowModify) const {
238 // Start from the bottom of the block and work up, examining the
239 // terminator instructions.
240 MachineBasicBlock::iterator I = MBB.end();
241 while (I != MBB.begin()) {
243 if (I->isDebugValue())
246 // Working from the bottom, when we see a non-terminator
247 // instruction, we're done.
248 if (!isUnpredicatedTerminator(I))
251 // A terminator that isn't a branch can't easily be handled
253 if (!I->getDesc().isBranch())
256 // Cannot handle indirect branches.
257 if (I->getOpcode() == MSP430::Br ||
258 I->getOpcode() == MSP430::Bm)
261 // Handle unconditional branches.
262 if (I->getOpcode() == MSP430::JMP) {
264 TBB = I->getOperand(0).getMBB();
268 // If the block has any instructions after a JMP, delete them.
269 while (llvm::next(I) != MBB.end())
270 llvm::next(I)->eraseFromParent();
274 // Delete the JMP if it's equivalent to a fall-through.
275 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
277 I->eraseFromParent();
282 // TBB is used to indicate the unconditinal destination.
283 TBB = I->getOperand(0).getMBB();
287 // Handle conditional branches.
288 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
289 MSP430CC::CondCodes BranchCode =
290 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
291 if (BranchCode == MSP430CC::COND_INVALID)
292 return true; // Can't handle weird stuff.
294 // Working from the bottom, handle the first conditional branch.
297 TBB = I->getOperand(0).getMBB();
298 Cond.push_back(MachineOperand::CreateImm(BranchCode));
302 // Handle subsequent conditional branches. Only handle the case where all
303 // conditional branches branch to the same destination.
304 assert(Cond.size() == 1);
307 // Only handle the case where all conditional branches branch to
308 // the same destination.
309 if (TBB != I->getOperand(0).getMBB())
312 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
313 // If the conditions are the same, we can leave them alone.
314 if (OldBranchCode == BranchCode)
324 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
325 MachineBasicBlock *FBB,
326 const SmallVectorImpl<MachineOperand> &Cond,
328 // Shouldn't be a fall through.
329 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
330 assert((Cond.size() == 1 || Cond.size() == 0) &&
331 "MSP430 branch conditions have one component!");
334 // Unconditional branch?
335 assert(!FBB && "Unconditional branch with multiple successors!");
336 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
340 // Conditional branch.
342 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
346 // Two-way Conditional branch. Insert the second branch.
347 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
353 /// GetInstSize - Return the number of bytes of code the specified
354 /// instruction may be. This returns the maximum number of bytes.
356 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
357 const TargetInstrDesc &Desc = MI->getDesc();
359 switch (Desc.TSFlags & MSP430II::SizeMask) {
361 switch (Desc.getOpcode()) {
363 assert(0 && "Unknown instruction size!");
364 case TargetOpcode::DBG_LABEL:
365 case TargetOpcode::EH_LABEL:
366 case TargetOpcode::IMPLICIT_DEF:
367 case TargetOpcode::KILL:
368 case TargetOpcode::DBG_VALUE:
370 case TargetOpcode::INLINEASM: {
371 const MachineFunction *MF = MI->getParent()->getParent();
372 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
373 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
374 *MF->getTarget().getMCAsmInfo());
377 case MSP430II::SizeSpecial:
378 switch (MI->getOpcode()) {
380 assert(0 && "Unknown instruction size!");
381 case MSP430::SAR8r1c:
382 case MSP430::SAR16r1c:
385 case MSP430II::Size2Bytes:
387 case MSP430II::Size4Bytes:
389 case MSP430II::Size6Bytes: