1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MSP430TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-lower"
16 #include "MSP430ISelLowering.h"
18 #include "MSP430TargetMachine.h"
19 #include "MSP430Subtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/VectorExtras.h"
48 static cl::opt<HWMultUseMode>
49 HWMultMode("msp430-hwmult-mode",
50 cl::desc("Hardware multiplier use mode"),
51 cl::init(HWMultNoIntr),
53 clEnumValN(NoHWMult, "no",
54 "Do not use hardware multiplier"),
55 clEnumValN(HWMultIntr, "interrupts",
56 "Assume hardware multiplier can be used inside interrupts"),
57 clEnumValN(HWMultNoIntr, "use",
58 "Assume hardware multiplier cannot be used inside interrupts"),
61 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
62 TargetLowering(tm, new TargetLoweringObjectFileELF()),
63 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
65 // Set up the register classes.
66 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
67 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
69 // Compute derived properties from the register classes
70 computeRegisterProperties();
72 // Provide all sorts of operation actions
74 // Division is expensive
75 setIntDivIsCheap(false);
77 // Even if we have only 1 bit shift here, we can perform
78 // shifts of the whole bitwidth 1 bit per step.
79 setShiftAmountType(MVT::i8);
81 setStackPointerRegisterToSaveRestore(MSP430::SPW);
82 setBooleanContents(ZeroOrOneBooleanContent);
83 setSchedulingPreference(SchedulingForLatency);
85 // We have post-incremented loads / stores.
86 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
87 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
89 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
91 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
95 // We don't have any truncstores
96 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
98 setOperationAction(ISD::SRA, MVT::i8, Custom);
99 setOperationAction(ISD::SHL, MVT::i8, Custom);
100 setOperationAction(ISD::SRL, MVT::i8, Custom);
101 setOperationAction(ISD::SRA, MVT::i16, Custom);
102 setOperationAction(ISD::SHL, MVT::i16, Custom);
103 setOperationAction(ISD::SRL, MVT::i16, Custom);
104 setOperationAction(ISD::ROTL, MVT::i8, Expand);
105 setOperationAction(ISD::ROTR, MVT::i8, Expand);
106 setOperationAction(ISD::ROTL, MVT::i16, Expand);
107 setOperationAction(ISD::ROTR, MVT::i16, Expand);
108 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
109 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
110 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
111 setOperationAction(ISD::BRIND, MVT::Other, Expand);
112 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
113 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
114 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
115 setOperationAction(ISD::SETCC, MVT::i8, Expand);
116 setOperationAction(ISD::SETCC, MVT::i16, Expand);
117 setOperationAction(ISD::SELECT, MVT::i8, Expand);
118 setOperationAction(ISD::SELECT, MVT::i16, Expand);
119 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
120 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
121 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
122 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
123 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
125 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
126 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
127 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
128 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
129 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
130 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
132 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
133 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
134 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
135 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
136 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
137 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
139 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
141 // FIXME: Implement efficiently multiplication by a constant
142 setOperationAction(ISD::MUL, MVT::i8, Expand);
143 setOperationAction(ISD::MULHS, MVT::i8, Expand);
144 setOperationAction(ISD::MULHU, MVT::i8, Expand);
145 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
146 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
147 setOperationAction(ISD::MUL, MVT::i16, Expand);
148 setOperationAction(ISD::MULHS, MVT::i16, Expand);
149 setOperationAction(ISD::MULHU, MVT::i16, Expand);
150 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
151 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
153 setOperationAction(ISD::UDIV, MVT::i8, Expand);
154 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
155 setOperationAction(ISD::UREM, MVT::i8, Expand);
156 setOperationAction(ISD::SDIV, MVT::i8, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
158 setOperationAction(ISD::SREM, MVT::i8, Expand);
159 setOperationAction(ISD::UDIV, MVT::i16, Expand);
160 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
161 setOperationAction(ISD::UREM, MVT::i16, Expand);
162 setOperationAction(ISD::SDIV, MVT::i16, Expand);
163 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
164 setOperationAction(ISD::SREM, MVT::i16, Expand);
167 if (HWMultMode == HWMultIntr) {
168 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw");
169 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
170 } else if (HWMultMode == HWMultNoIntr) {
171 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint");
172 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
176 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
177 switch (Op.getOpcode()) {
178 case ISD::SHL: // FALLTHROUGH
180 case ISD::SRA: return LowerShifts(Op, DAG);
181 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
182 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
183 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
184 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
185 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
187 llvm_unreachable("unimplemented operand");
192 /// getFunctionAlignment - Return the Log2 alignment of this function.
193 unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
194 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
197 //===----------------------------------------------------------------------===//
198 // MSP430 Inline Assembly Support
199 //===----------------------------------------------------------------------===//
201 /// getConstraintType - Given a constraint letter, return the type of
202 /// constraint it is for this target.
203 TargetLowering::ConstraintType
204 MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
205 if (Constraint.size() == 1) {
206 switch (Constraint[0]) {
208 return C_RegisterClass;
213 return TargetLowering::getConstraintType(Constraint);
216 std::pair<unsigned, const TargetRegisterClass*>
217 MSP430TargetLowering::
218 getRegForInlineAsmConstraint(const std::string &Constraint,
220 if (Constraint.size() == 1) {
221 // GCC Constraint Letters
222 switch (Constraint[0]) {
224 case 'r': // GENERAL_REGS
226 return std::make_pair(0U, MSP430::GR8RegisterClass);
228 return std::make_pair(0U, MSP430::GR16RegisterClass);
232 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
235 //===----------------------------------------------------------------------===//
236 // Calling Convention Implementation
237 //===----------------------------------------------------------------------===//
239 #include "MSP430GenCallingConv.inc"
242 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
243 CallingConv::ID CallConv,
245 const SmallVectorImpl<ISD::InputArg>
249 SmallVectorImpl<SDValue> &InVals) {
253 llvm_unreachable("Unsupported calling convention");
255 case CallingConv::Fast:
256 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
261 MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
262 CallingConv::ID CallConv, bool isVarArg,
264 const SmallVectorImpl<ISD::OutputArg> &Outs,
265 const SmallVectorImpl<ISD::InputArg> &Ins,
266 DebugLoc dl, SelectionDAG &DAG,
267 SmallVectorImpl<SDValue> &InVals) {
271 llvm_unreachable("Unsupported calling convention");
272 case CallingConv::Fast:
274 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
275 Outs, Ins, dl, DAG, InVals);
279 /// LowerCCCArguments - transform physical registers into virtual registers and
280 /// generate load operations for arguments places on the stack.
281 // FIXME: struct return stuff
284 MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
285 CallingConv::ID CallConv,
287 const SmallVectorImpl<ISD::InputArg>
291 SmallVectorImpl<SDValue> &InVals) {
292 MachineFunction &MF = DAG.getMachineFunction();
293 MachineFrameInfo *MFI = MF.getFrameInfo();
294 MachineRegisterInfo &RegInfo = MF.getRegInfo();
296 // Assign locations to all of the incoming arguments.
297 SmallVector<CCValAssign, 16> ArgLocs;
298 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
299 ArgLocs, *DAG.getContext());
300 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
302 assert(!isVarArg && "Varargs not supported yet");
304 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
305 CCValAssign &VA = ArgLocs[i];
307 // Arguments passed in registers
308 EVT RegVT = VA.getLocVT();
309 switch (RegVT.getSimpleVT().SimpleTy) {
313 errs() << "LowerFormalArguments Unhandled argument type: "
314 << RegVT.getSimpleVT().SimpleTy << "\n";
320 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
321 RegInfo.addLiveIn(VA.getLocReg(), VReg);
322 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
324 // If this is an 8-bit value, it is really passed promoted to 16
325 // bits. Insert an assert[sz]ext to capture this, then truncate to the
327 if (VA.getLocInfo() == CCValAssign::SExt)
328 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
329 DAG.getValueType(VA.getValVT()));
330 else if (VA.getLocInfo() == CCValAssign::ZExt)
331 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
332 DAG.getValueType(VA.getValVT()));
334 if (VA.getLocInfo() != CCValAssign::Full)
335 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
337 InVals.push_back(ArgValue);
341 assert(VA.isMemLoc());
342 // Load the argument to a virtual register
343 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
345 errs() << "LowerFormalArguments Unhandled argument type: "
346 << VA.getLocVT().getSimpleVT().SimpleTy
349 // Create the frame index object for this incoming parameter...
350 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
352 // Create the SelectionDAG nodes corresponding to a load
353 //from this parameter
354 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
355 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
356 PseudoSourceValue::getFixedStack(FI), 0));
364 MSP430TargetLowering::LowerReturn(SDValue Chain,
365 CallingConv::ID CallConv, bool isVarArg,
366 const SmallVectorImpl<ISD::OutputArg> &Outs,
367 DebugLoc dl, SelectionDAG &DAG) {
369 // CCValAssign - represent the assignment of the return value to a location
370 SmallVector<CCValAssign, 16> RVLocs;
372 // CCState - Info about the registers and stack slot.
373 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
374 RVLocs, *DAG.getContext());
376 // Analize return values.
377 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
379 // If this is the first return lowered for this function, add the regs to the
380 // liveout set for the function.
381 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
382 for (unsigned i = 0; i != RVLocs.size(); ++i)
383 if (RVLocs[i].isRegLoc())
384 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
389 // Copy the result values into the output registers.
390 for (unsigned i = 0; i != RVLocs.size(); ++i) {
391 CCValAssign &VA = RVLocs[i];
392 assert(VA.isRegLoc() && "Can only return in registers!");
394 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
397 // Guarantee that all emitted copies are stuck together,
398 // avoiding something bad.
399 Flag = Chain.getValue(1);
403 return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
406 return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
409 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
410 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
413 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
414 CallingConv::ID CallConv, bool isVarArg,
416 const SmallVectorImpl<ISD::OutputArg>
418 const SmallVectorImpl<ISD::InputArg> &Ins,
419 DebugLoc dl, SelectionDAG &DAG,
420 SmallVectorImpl<SDValue> &InVals) {
421 // Analyze operands of the call, assigning locations to each operand.
422 SmallVector<CCValAssign, 16> ArgLocs;
423 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
424 ArgLocs, *DAG.getContext());
426 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
428 // Get a count of how many bytes are to be pushed on the stack.
429 unsigned NumBytes = CCInfo.getNextStackOffset();
431 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
432 getPointerTy(), true));
434 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
435 SmallVector<SDValue, 12> MemOpChains;
438 // Walk the register/memloc assignments, inserting copies/loads.
439 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
440 CCValAssign &VA = ArgLocs[i];
442 SDValue Arg = Outs[i].Val;
444 // Promote the value if needed.
445 switch (VA.getLocInfo()) {
446 default: llvm_unreachable("Unknown loc info!");
447 case CCValAssign::Full: break;
448 case CCValAssign::SExt:
449 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
451 case CCValAssign::ZExt:
452 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
454 case CCValAssign::AExt:
455 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
459 // Arguments that can be passed on register must be kept at RegsToPass
462 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
464 assert(VA.isMemLoc());
466 if (StackPtr.getNode() == 0)
467 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
469 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
471 DAG.getIntPtrConstant(VA.getLocMemOffset()));
474 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
475 PseudoSourceValue::getStack(),
476 VA.getLocMemOffset()));
480 // Transform all store nodes into one single node because all store nodes are
481 // independent of each other.
482 if (!MemOpChains.empty())
483 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
484 &MemOpChains[0], MemOpChains.size());
486 // Build a sequence of copy-to-reg nodes chained together with token chain and
487 // flag operands which copy the outgoing args into registers. The InFlag in
488 // necessary since all emited instructions must be stuck together.
490 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
491 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
492 RegsToPass[i].second, InFlag);
493 InFlag = Chain.getValue(1);
496 // If the callee is a GlobalAddress node (quite common, every direct call is)
497 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
498 // Likewise ExternalSymbol -> TargetExternalSymbol.
499 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
500 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
501 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
502 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
504 // Returns a chain & a flag for retval copy to use.
505 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
506 SmallVector<SDValue, 8> Ops;
507 Ops.push_back(Chain);
508 Ops.push_back(Callee);
510 // Add argument registers to the end of the list so that they are
511 // known live into the call.
512 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
513 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
514 RegsToPass[i].second.getValueType()));
516 if (InFlag.getNode())
517 Ops.push_back(InFlag);
519 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
520 InFlag = Chain.getValue(1);
522 // Create the CALLSEQ_END node.
523 Chain = DAG.getCALLSEQ_END(Chain,
524 DAG.getConstant(NumBytes, getPointerTy(), true),
525 DAG.getConstant(0, getPointerTy(), true),
527 InFlag = Chain.getValue(1);
529 // Handle result values, copying them out of physregs into vregs that we
531 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
535 /// LowerCallResult - Lower the result values of a call into the
536 /// appropriate copies out of appropriate physical registers.
539 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
540 CallingConv::ID CallConv, bool isVarArg,
541 const SmallVectorImpl<ISD::InputArg> &Ins,
542 DebugLoc dl, SelectionDAG &DAG,
543 SmallVectorImpl<SDValue> &InVals) {
545 // Assign locations to each value returned by this call.
546 SmallVector<CCValAssign, 16> RVLocs;
547 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
548 RVLocs, *DAG.getContext());
550 CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
552 // Copy all of the result registers out of their specified physreg.
553 for (unsigned i = 0; i != RVLocs.size(); ++i) {
554 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
555 RVLocs[i].getValVT(), InFlag).getValue(1);
556 InFlag = Chain.getValue(2);
557 InVals.push_back(Chain.getValue(0));
563 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
565 unsigned Opc = Op.getOpcode();
566 SDNode* N = Op.getNode();
567 EVT VT = Op.getValueType();
568 DebugLoc dl = N->getDebugLoc();
570 // We currently only lower shifts of constant argument.
571 if (!isa<ConstantSDNode>(N->getOperand(1)))
574 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
576 // Expand the stuff into sequence of shifts.
577 // FIXME: for some shift amounts this might be done better!
578 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
579 SDValue Victim = N->getOperand(0);
581 if (Opc == ISD::SRL && ShiftAmount) {
582 // Emit a special goodness here:
583 // srl A, 1 => clrc; rrc A
584 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
588 while (ShiftAmount--)
589 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
595 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
596 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
597 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
599 // Create the TargetGlobalAddress node, folding in the constant offset.
600 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
601 return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
602 getPointerTy(), Result);
605 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
607 DebugLoc dl = Op.getDebugLoc();
608 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
609 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
611 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
614 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
616 DebugLoc dl, SelectionDAG &DAG) {
617 // FIXME: Handle bittests someday
618 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
620 // FIXME: Handle jump negative someday
621 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
623 default: llvm_unreachable("Invalid integer condition!");
625 TCC = MSP430CC::COND_E; // aka COND_Z
626 // Minor optimization: if RHS is a constant, swap operands, then the
627 // constant can be folded into comparison.
628 if (RHS.getOpcode() == ISD::Constant)
632 TCC = MSP430CC::COND_NE; // aka COND_NZ
633 // Minor optimization: if RHS is a constant, swap operands, then the
634 // constant can be folded into comparison.
635 if (RHS.getOpcode() == ISD::Constant)
639 std::swap(LHS, RHS); // FALLTHROUGH
641 TCC = MSP430CC::COND_HS; // aka COND_C
644 std::swap(LHS, RHS); // FALLTHROUGH
646 TCC = MSP430CC::COND_LO; // aka COND_NC
649 std::swap(LHS, RHS); // FALLTHROUGH
651 TCC = MSP430CC::COND_GE;
654 std::swap(LHS, RHS); // FALLTHROUGH
656 TCC = MSP430CC::COND_L;
660 TargetCC = DAG.getConstant(TCC, MVT::i8);
661 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
665 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
666 SDValue Chain = Op.getOperand(0);
667 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
668 SDValue LHS = Op.getOperand(2);
669 SDValue RHS = Op.getOperand(3);
670 SDValue Dest = Op.getOperand(4);
671 DebugLoc dl = Op.getDebugLoc();
674 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
676 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
677 Chain, Dest, TargetCC, Flag);
680 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
681 SDValue LHS = Op.getOperand(0);
682 SDValue RHS = Op.getOperand(1);
683 SDValue TrueV = Op.getOperand(2);
684 SDValue FalseV = Op.getOperand(3);
685 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
686 DebugLoc dl = Op.getDebugLoc();
689 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
691 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
692 SmallVector<SDValue, 4> Ops;
693 Ops.push_back(TrueV);
694 Ops.push_back(FalseV);
695 Ops.push_back(TargetCC);
698 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
701 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
703 SDValue Val = Op.getOperand(0);
704 EVT VT = Op.getValueType();
705 DebugLoc dl = Op.getDebugLoc();
707 assert(VT == MVT::i16 && "Only support i16 for now!");
709 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
710 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
711 DAG.getValueType(Val.getValueType()));
714 /// getPostIndexedAddressParts - returns true by value, base pointer and
715 /// offset pointer and addressing mode by reference if this node can be
716 /// combined with a load / store to form a post-indexed load / store.
717 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
720 ISD::MemIndexedMode &AM,
721 SelectionDAG &DAG) const {
723 LoadSDNode *LD = cast<LoadSDNode>(N);
724 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
727 EVT VT = LD->getMemoryVT();
728 if (VT != MVT::i8 && VT != MVT::i16)
731 if (Op->getOpcode() != ISD::ADD)
734 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
735 uint64_t RHSC = RHS->getZExtValue();
736 if ((VT == MVT::i16 && RHSC != 2) ||
737 (VT == MVT::i8 && RHSC != 1))
740 Base = Op->getOperand(0);
741 Offset = DAG.getConstant(RHSC, VT);
750 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
752 default: return NULL;
753 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
754 case MSP430ISD::RRA: return "MSP430ISD::RRA";
755 case MSP430ISD::RLA: return "MSP430ISD::RLA";
756 case MSP430ISD::RRC: return "MSP430ISD::RRC";
757 case MSP430ISD::CALL: return "MSP430ISD::CALL";
758 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
759 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
760 case MSP430ISD::CMP: return "MSP430ISD::CMP";
761 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
765 //===----------------------------------------------------------------------===//
766 // Other Lowering Code
767 //===----------------------------------------------------------------------===//
770 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
771 MachineBasicBlock *BB,
772 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
773 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
774 DebugLoc dl = MI->getDebugLoc();
775 assert((MI->getOpcode() == MSP430::Select16 ||
776 MI->getOpcode() == MSP430::Select8) &&
777 "Unexpected instr type to insert");
779 // To "insert" a SELECT instruction, we actually have to insert the diamond
780 // control-flow pattern. The incoming instruction knows the destination vreg
781 // to set, the condition code register to branch on, the true/false values to
782 // select between, and a branch opcode to use.
783 const BasicBlock *LLVM_BB = BB->getBasicBlock();
784 MachineFunction::iterator I = BB;
792 // fallthrough --> copy0MBB
793 MachineBasicBlock *thisMBB = BB;
794 MachineFunction *F = BB->getParent();
795 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
796 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
797 BuildMI(BB, dl, TII.get(MSP430::JCC))
799 .addImm(MI->getOperand(3).getImm());
800 F->insert(I, copy0MBB);
801 F->insert(I, copy1MBB);
802 // Inform sdisel of the edge changes.
803 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
804 SE = BB->succ_end(); SI != SE; ++SI)
805 EM->insert(std::make_pair(*SI, copy1MBB));
806 // Update machine-CFG edges by transferring all successors of the current
807 // block to the new block which will contain the Phi node for the select.
808 copy1MBB->transferSuccessors(BB);
809 // Next, add the true and fallthrough blocks as its successors.
810 BB->addSuccessor(copy0MBB);
811 BB->addSuccessor(copy1MBB);
815 // # fallthrough to copy1MBB
818 // Update machine-CFG edges
819 BB->addSuccessor(copy1MBB);
822 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
825 BuildMI(BB, dl, TII.get(MSP430::PHI),
826 MI->getOperand(0).getReg())
827 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
828 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
830 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.