1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MSP430TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-lower"
16 #include "MSP430ISelLowering.h"
18 #include "MSP430MachineFunctionInfo.h"
19 #include "MSP430TargetMachine.h"
20 #include "MSP430Subtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/GlobalAlias.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/CodeGen/SelectionDAGISel.h"
34 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/ADT/VectorExtras.h"
49 static cl::opt<HWMultUseMode>
50 HWMultMode("msp430-hwmult-mode",
51 cl::desc("Hardware multiplier use mode"),
52 cl::init(HWMultNoIntr),
54 clEnumValN(NoHWMult, "no",
55 "Do not use hardware multiplier"),
56 clEnumValN(HWMultIntr, "interrupts",
57 "Assume hardware multiplier can be used inside interrupts"),
58 clEnumValN(HWMultNoIntr, "use",
59 "Assume hardware multiplier cannot be used inside interrupts"),
62 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63 TargetLowering(tm, new TargetLoweringObjectFileELF()),
64 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
68 // Set up the register classes.
69 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
70 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
72 // Compute derived properties from the register classes
73 computeRegisterProperties();
75 // Provide all sorts of operation actions
77 // Division is expensive
78 setIntDivIsCheap(false);
80 // Even if we have only 1 bit shift here, we can perform
81 // shifts of the whole bitwidth 1 bit per step.
82 setShiftAmountType(MVT::i8);
84 setStackPointerRegisterToSaveRestore(MSP430::SPW);
85 setBooleanContents(ZeroOrOneBooleanContent);
86 setSchedulingPreference(Sched::Latency);
88 // We have post-incremented loads / stores.
89 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
90 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
92 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
95 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
96 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
98 // We don't have any truncstores
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 setOperationAction(ISD::SRA, MVT::i8, Custom);
102 setOperationAction(ISD::SHL, MVT::i8, Custom);
103 setOperationAction(ISD::SRL, MVT::i8, Custom);
104 setOperationAction(ISD::SRA, MVT::i16, Custom);
105 setOperationAction(ISD::SHL, MVT::i16, Custom);
106 setOperationAction(ISD::SRL, MVT::i16, Custom);
107 setOperationAction(ISD::ROTL, MVT::i8, Expand);
108 setOperationAction(ISD::ROTR, MVT::i8, Expand);
109 setOperationAction(ISD::ROTL, MVT::i16, Expand);
110 setOperationAction(ISD::ROTR, MVT::i16, Expand);
111 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
112 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
113 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
116 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
117 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
118 setOperationAction(ISD::SETCC, MVT::i8, Custom);
119 setOperationAction(ISD::SETCC, MVT::i16, Custom);
120 setOperationAction(ISD::SELECT, MVT::i8, Expand);
121 setOperationAction(ISD::SELECT, MVT::i16, Expand);
122 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
123 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
124 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
125 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
126 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
128 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
129 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
130 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
131 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
132 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
133 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
135 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
136 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
137 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
138 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
139 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
140 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
142 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
144 // FIXME: Implement efficiently multiplication by a constant
145 setOperationAction(ISD::MUL, MVT::i8, Expand);
146 setOperationAction(ISD::MULHS, MVT::i8, Expand);
147 setOperationAction(ISD::MULHU, MVT::i8, Expand);
148 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
149 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
150 setOperationAction(ISD::MUL, MVT::i16, Expand);
151 setOperationAction(ISD::MULHS, MVT::i16, Expand);
152 setOperationAction(ISD::MULHU, MVT::i16, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
156 setOperationAction(ISD::UDIV, MVT::i8, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
158 setOperationAction(ISD::UREM, MVT::i8, Expand);
159 setOperationAction(ISD::SDIV, MVT::i8, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
161 setOperationAction(ISD::SREM, MVT::i8, Expand);
162 setOperationAction(ISD::UDIV, MVT::i16, Expand);
163 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
164 setOperationAction(ISD::UREM, MVT::i16, Expand);
165 setOperationAction(ISD::SDIV, MVT::i16, Expand);
166 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
167 setOperationAction(ISD::SREM, MVT::i16, Expand);
170 if (HWMultMode == HWMultIntr) {
171 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw");
172 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
173 } else if (HWMultMode == HWMultNoIntr) {
174 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint");
175 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
179 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
180 SelectionDAG &DAG) const {
181 switch (Op.getOpcode()) {
182 case ISD::SHL: // FALLTHROUGH
184 case ISD::SRA: return LowerShifts(Op, DAG);
185 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
186 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
187 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
188 case ISD::SETCC: return LowerSETCC(Op, DAG);
189 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
190 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
191 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
192 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
193 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
195 llvm_unreachable("unimplemented operand");
200 /// getFunctionAlignment - Return the Log2 alignment of this function.
201 unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
202 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
205 //===----------------------------------------------------------------------===//
206 // MSP430 Inline Assembly Support
207 //===----------------------------------------------------------------------===//
209 /// getConstraintType - Given a constraint letter, return the type of
210 /// constraint it is for this target.
211 TargetLowering::ConstraintType
212 MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
213 if (Constraint.size() == 1) {
214 switch (Constraint[0]) {
216 return C_RegisterClass;
221 return TargetLowering::getConstraintType(Constraint);
224 std::pair<unsigned, const TargetRegisterClass*>
225 MSP430TargetLowering::
226 getRegForInlineAsmConstraint(const std::string &Constraint,
228 if (Constraint.size() == 1) {
229 // GCC Constraint Letters
230 switch (Constraint[0]) {
232 case 'r': // GENERAL_REGS
234 return std::make_pair(0U, MSP430::GR8RegisterClass);
236 return std::make_pair(0U, MSP430::GR16RegisterClass);
240 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
243 //===----------------------------------------------------------------------===//
244 // Calling Convention Implementation
245 //===----------------------------------------------------------------------===//
247 #include "MSP430GenCallingConv.inc"
250 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
251 CallingConv::ID CallConv,
253 const SmallVectorImpl<ISD::InputArg>
257 SmallVectorImpl<SDValue> &InVals)
262 llvm_unreachable("Unsupported calling convention");
264 case CallingConv::Fast:
265 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
266 case CallingConv::MSP430_INTR:
270 report_fatal_error("ISRs cannot have arguments");
277 MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
278 CallingConv::ID CallConv, bool isVarArg,
280 const SmallVectorImpl<ISD::OutputArg> &Outs,
281 const SmallVectorImpl<ISD::InputArg> &Ins,
282 DebugLoc dl, SelectionDAG &DAG,
283 SmallVectorImpl<SDValue> &InVals) const {
284 // MSP430 target does not yet support tail call optimization.
289 llvm_unreachable("Unsupported calling convention");
290 case CallingConv::Fast:
292 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
293 Outs, Ins, dl, DAG, InVals);
294 case CallingConv::MSP430_INTR:
295 report_fatal_error("ISRs cannot be called directly");
300 /// LowerCCCArguments - transform physical registers into virtual registers and
301 /// generate load operations for arguments places on the stack.
302 // FIXME: struct return stuff
305 MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
306 CallingConv::ID CallConv,
308 const SmallVectorImpl<ISD::InputArg>
312 SmallVectorImpl<SDValue> &InVals)
314 MachineFunction &MF = DAG.getMachineFunction();
315 MachineFrameInfo *MFI = MF.getFrameInfo();
316 MachineRegisterInfo &RegInfo = MF.getRegInfo();
318 // Assign locations to all of the incoming arguments.
319 SmallVector<CCValAssign, 16> ArgLocs;
320 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
321 ArgLocs, *DAG.getContext());
322 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
324 assert(!isVarArg && "Varargs not supported yet");
326 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
327 CCValAssign &VA = ArgLocs[i];
329 // Arguments passed in registers
330 EVT RegVT = VA.getLocVT();
331 switch (RegVT.getSimpleVT().SimpleTy) {
335 errs() << "LowerFormalArguments Unhandled argument type: "
336 << RegVT.getSimpleVT().SimpleTy << "\n";
342 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
343 RegInfo.addLiveIn(VA.getLocReg(), VReg);
344 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
346 // If this is an 8-bit value, it is really passed promoted to 16
347 // bits. Insert an assert[sz]ext to capture this, then truncate to the
349 if (VA.getLocInfo() == CCValAssign::SExt)
350 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
351 DAG.getValueType(VA.getValVT()));
352 else if (VA.getLocInfo() == CCValAssign::ZExt)
353 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
354 DAG.getValueType(VA.getValVT()));
356 if (VA.getLocInfo() != CCValAssign::Full)
357 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
359 InVals.push_back(ArgValue);
363 assert(VA.isMemLoc());
364 // Load the argument to a virtual register
365 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
367 errs() << "LowerFormalArguments Unhandled argument type: "
368 << VA.getLocVT().getSimpleVT().SimpleTy
371 // Create the frame index object for this incoming parameter...
372 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
374 // Create the SelectionDAG nodes corresponding to a load
375 //from this parameter
376 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
377 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
378 PseudoSourceValue::getFixedStack(FI), 0,
387 MSP430TargetLowering::LowerReturn(SDValue Chain,
388 CallingConv::ID CallConv, bool isVarArg,
389 const SmallVectorImpl<ISD::OutputArg> &Outs,
390 DebugLoc dl, SelectionDAG &DAG) const {
392 // CCValAssign - represent the assignment of the return value to a location
393 SmallVector<CCValAssign, 16> RVLocs;
395 // ISRs cannot return any value.
396 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
397 report_fatal_error("ISRs cannot return any value");
401 // CCState - Info about the registers and stack slot.
402 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
403 RVLocs, *DAG.getContext());
405 // Analize return values.
406 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
408 // If this is the first return lowered for this function, add the regs to the
409 // liveout set for the function.
410 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
411 for (unsigned i = 0; i != RVLocs.size(); ++i)
412 if (RVLocs[i].isRegLoc())
413 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
418 // Copy the result values into the output registers.
419 for (unsigned i = 0; i != RVLocs.size(); ++i) {
420 CCValAssign &VA = RVLocs[i];
421 assert(VA.isRegLoc() && "Can only return in registers!");
423 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
426 // Guarantee that all emitted copies are stuck together,
427 // avoiding something bad.
428 Flag = Chain.getValue(1);
431 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
432 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
435 return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
438 return DAG.getNode(Opc, dl, MVT::Other, Chain);
441 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
442 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
445 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
446 CallingConv::ID CallConv, bool isVarArg,
448 const SmallVectorImpl<ISD::OutputArg>
450 const SmallVectorImpl<ISD::InputArg> &Ins,
451 DebugLoc dl, SelectionDAG &DAG,
452 SmallVectorImpl<SDValue> &InVals) const {
453 // Analyze operands of the call, assigning locations to each operand.
454 SmallVector<CCValAssign, 16> ArgLocs;
455 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
456 ArgLocs, *DAG.getContext());
458 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
460 // Get a count of how many bytes are to be pushed on the stack.
461 unsigned NumBytes = CCInfo.getNextStackOffset();
463 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
464 getPointerTy(), true));
466 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
467 SmallVector<SDValue, 12> MemOpChains;
470 // Walk the register/memloc assignments, inserting copies/loads.
471 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
472 CCValAssign &VA = ArgLocs[i];
474 SDValue Arg = Outs[i].Val;
476 // Promote the value if needed.
477 switch (VA.getLocInfo()) {
478 default: llvm_unreachable("Unknown loc info!");
479 case CCValAssign::Full: break;
480 case CCValAssign::SExt:
481 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
483 case CCValAssign::ZExt:
484 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
486 case CCValAssign::AExt:
487 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
491 // Arguments that can be passed on register must be kept at RegsToPass
494 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
496 assert(VA.isMemLoc());
498 if (StackPtr.getNode() == 0)
499 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
501 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
503 DAG.getIntPtrConstant(VA.getLocMemOffset()));
506 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
507 PseudoSourceValue::getStack(),
508 VA.getLocMemOffset(), false, false, 0));
512 // Transform all store nodes into one single node because all store nodes are
513 // independent of each other.
514 if (!MemOpChains.empty())
515 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
516 &MemOpChains[0], MemOpChains.size());
518 // Build a sequence of copy-to-reg nodes chained together with token chain and
519 // flag operands which copy the outgoing args into registers. The InFlag in
520 // necessary since all emited instructions must be stuck together.
522 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
523 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
524 RegsToPass[i].second, InFlag);
525 InFlag = Chain.getValue(1);
528 // If the callee is a GlobalAddress node (quite common, every direct call is)
529 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
530 // Likewise ExternalSymbol -> TargetExternalSymbol.
531 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
532 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
533 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
534 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
536 // Returns a chain & a flag for retval copy to use.
537 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
538 SmallVector<SDValue, 8> Ops;
539 Ops.push_back(Chain);
540 Ops.push_back(Callee);
542 // Add argument registers to the end of the list so that they are
543 // known live into the call.
544 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
545 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
546 RegsToPass[i].second.getValueType()));
548 if (InFlag.getNode())
549 Ops.push_back(InFlag);
551 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
552 InFlag = Chain.getValue(1);
554 // Create the CALLSEQ_END node.
555 Chain = DAG.getCALLSEQ_END(Chain,
556 DAG.getConstant(NumBytes, getPointerTy(), true),
557 DAG.getConstant(0, getPointerTy(), true),
559 InFlag = Chain.getValue(1);
561 // Handle result values, copying them out of physregs into vregs that we
563 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
567 /// LowerCallResult - Lower the result values of a call into the
568 /// appropriate copies out of appropriate physical registers.
571 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
572 CallingConv::ID CallConv, bool isVarArg,
573 const SmallVectorImpl<ISD::InputArg> &Ins,
574 DebugLoc dl, SelectionDAG &DAG,
575 SmallVectorImpl<SDValue> &InVals) const {
577 // Assign locations to each value returned by this call.
578 SmallVector<CCValAssign, 16> RVLocs;
579 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
580 RVLocs, *DAG.getContext());
582 CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
584 // Copy all of the result registers out of their specified physreg.
585 for (unsigned i = 0; i != RVLocs.size(); ++i) {
586 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
587 RVLocs[i].getValVT(), InFlag).getValue(1);
588 InFlag = Chain.getValue(2);
589 InVals.push_back(Chain.getValue(0));
595 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
596 SelectionDAG &DAG) const {
597 unsigned Opc = Op.getOpcode();
598 SDNode* N = Op.getNode();
599 EVT VT = Op.getValueType();
600 DebugLoc dl = N->getDebugLoc();
602 // Expand non-constant shifts to loops:
603 if (!isa<ConstantSDNode>(N->getOperand(1)))
606 assert(0 && "Invalid shift opcode!");
608 return DAG.getNode(MSP430ISD::SHL, dl,
609 VT, N->getOperand(0), N->getOperand(1));
611 return DAG.getNode(MSP430ISD::SRA, dl,
612 VT, N->getOperand(0), N->getOperand(1));
614 return DAG.getNode(MSP430ISD::SRL, dl,
615 VT, N->getOperand(0), N->getOperand(1));
618 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
620 // Expand the stuff into sequence of shifts.
621 // FIXME: for some shift amounts this might be done better!
622 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
623 SDValue Victim = N->getOperand(0);
625 if (Opc == ISD::SRL && ShiftAmount) {
626 // Emit a special goodness here:
627 // srl A, 1 => clrc; rrc A
628 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
632 while (ShiftAmount--)
633 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
639 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
640 SelectionDAG &DAG) const {
641 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
642 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
644 // Create the TargetGlobalAddress node, folding in the constant offset.
645 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
646 return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
647 getPointerTy(), Result);
650 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
651 SelectionDAG &DAG) const {
652 DebugLoc dl = Op.getDebugLoc();
653 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
654 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
656 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
659 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
660 SelectionDAG &DAG) const {
661 DebugLoc dl = Op.getDebugLoc();
662 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
663 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
665 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
668 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
670 DebugLoc dl, SelectionDAG &DAG) {
671 // FIXME: Handle bittests someday
672 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
674 // FIXME: Handle jump negative someday
675 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
677 default: llvm_unreachable("Invalid integer condition!");
679 TCC = MSP430CC::COND_E; // aka COND_Z
680 // Minor optimization: if LHS is a constant, swap operands, then the
681 // constant can be folded into comparison.
682 if (LHS.getOpcode() == ISD::Constant)
686 TCC = MSP430CC::COND_NE; // aka COND_NZ
687 // Minor optimization: if LHS is a constant, swap operands, then the
688 // constant can be folded into comparison.
689 if (LHS.getOpcode() == ISD::Constant)
693 std::swap(LHS, RHS); // FALLTHROUGH
695 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
696 // fold constant into instruction.
697 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
699 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
700 TCC = MSP430CC::COND_LO;
703 TCC = MSP430CC::COND_HS; // aka COND_C
706 std::swap(LHS, RHS); // FALLTHROUGH
708 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
709 // fold constant into instruction.
710 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
712 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
713 TCC = MSP430CC::COND_HS;
716 TCC = MSP430CC::COND_LO; // aka COND_NC
719 std::swap(LHS, RHS); // FALLTHROUGH
721 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
722 // fold constant into instruction.
723 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
725 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
726 TCC = MSP430CC::COND_L;
729 TCC = MSP430CC::COND_GE;
732 std::swap(LHS, RHS); // FALLTHROUGH
734 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
735 // fold constant into instruction.
736 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
738 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
739 TCC = MSP430CC::COND_GE;
742 TCC = MSP430CC::COND_L;
746 TargetCC = DAG.getConstant(TCC, MVT::i8);
747 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
751 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
752 SDValue Chain = Op.getOperand(0);
753 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
754 SDValue LHS = Op.getOperand(2);
755 SDValue RHS = Op.getOperand(3);
756 SDValue Dest = Op.getOperand(4);
757 DebugLoc dl = Op.getDebugLoc();
760 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
762 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
763 Chain, Dest, TargetCC, Flag);
766 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
767 SDValue LHS = Op.getOperand(0);
768 SDValue RHS = Op.getOperand(1);
769 DebugLoc dl = Op.getDebugLoc();
771 // If we are doing an AND and testing against zero, then the CMP
772 // will not be generated. The AND (or BIT) will generate the condition codes,
773 // but they are different from CMP.
774 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
775 // lowering & isel wouldn't diverge.
777 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
778 if (RHSC->isNullValue() && LHS.hasOneUse() &&
779 (LHS.getOpcode() == ISD::AND ||
780 (LHS.getOpcode() == ISD::TRUNCATE &&
781 LHS.getOperand(0).getOpcode() == ISD::AND))) {
785 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
787 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
789 // Get the condition codes directly from the status register, if its easy.
790 // Otherwise a branch will be generated. Note that the AND and BIT
791 // instructions generate different flags than CMP, the carry bit can be used
796 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
800 case MSP430CC::COND_HS:
801 // Res = SRW & 1, no processing is required
803 case MSP430CC::COND_LO:
807 case MSP430CC::COND_NE:
809 // C = ~Z, thus Res = SRW & 1, no processing is required
811 // Res = ~((SRW >> 1) & 1)
816 case MSP430CC::COND_E:
818 // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
819 // Res = (SRW >> 1) & 1 is 1 word shorter.
822 EVT VT = Op.getValueType();
823 SDValue One = DAG.getConstant(1, VT);
825 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
828 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
829 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
830 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
832 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
835 SDValue Zero = DAG.getConstant(0, VT);
836 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
837 SmallVector<SDValue, 4> Ops;
840 Ops.push_back(TargetCC);
842 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
846 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
847 SelectionDAG &DAG) const {
848 SDValue LHS = Op.getOperand(0);
849 SDValue RHS = Op.getOperand(1);
850 SDValue TrueV = Op.getOperand(2);
851 SDValue FalseV = Op.getOperand(3);
852 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
853 DebugLoc dl = Op.getDebugLoc();
856 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
858 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
859 SmallVector<SDValue, 4> Ops;
860 Ops.push_back(TrueV);
861 Ops.push_back(FalseV);
862 Ops.push_back(TargetCC);
865 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
868 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
869 SelectionDAG &DAG) const {
870 SDValue Val = Op.getOperand(0);
871 EVT VT = Op.getValueType();
872 DebugLoc dl = Op.getDebugLoc();
874 assert(VT == MVT::i16 && "Only support i16 for now!");
876 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
877 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
878 DAG.getValueType(Val.getValueType()));
882 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
883 MachineFunction &MF = DAG.getMachineFunction();
884 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
885 int ReturnAddrIndex = FuncInfo->getRAIndex();
887 if (ReturnAddrIndex == 0) {
888 // Set up a frame object for the return address.
889 uint64_t SlotSize = TD->getPointerSize();
890 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
892 FuncInfo->setRAIndex(ReturnAddrIndex);
895 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
898 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
899 SelectionDAG &DAG) const {
900 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
901 MFI->setReturnAddressIsTaken(true);
903 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
904 DebugLoc dl = Op.getDebugLoc();
907 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
909 DAG.getConstant(TD->getPointerSize(), MVT::i16);
910 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
911 DAG.getNode(ISD::ADD, dl, getPointerTy(),
913 NULL, 0, false, false, 0);
916 // Just load the return address.
917 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
918 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
919 RetAddrFI, NULL, 0, false, false, 0);
922 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
923 SelectionDAG &DAG) const {
924 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
925 MFI->setFrameAddressIsTaken(true);
927 EVT VT = Op.getValueType();
928 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
929 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
930 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
933 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
938 /// getPostIndexedAddressParts - returns true by value, base pointer and
939 /// offset pointer and addressing mode by reference if this node can be
940 /// combined with a load / store to form a post-indexed load / store.
941 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
944 ISD::MemIndexedMode &AM,
945 SelectionDAG &DAG) const {
947 LoadSDNode *LD = cast<LoadSDNode>(N);
948 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
951 EVT VT = LD->getMemoryVT();
952 if (VT != MVT::i8 && VT != MVT::i16)
955 if (Op->getOpcode() != ISD::ADD)
958 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
959 uint64_t RHSC = RHS->getZExtValue();
960 if ((VT == MVT::i16 && RHSC != 2) ||
961 (VT == MVT::i8 && RHSC != 1))
964 Base = Op->getOperand(0);
965 Offset = DAG.getConstant(RHSC, VT);
974 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
976 default: return NULL;
977 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
978 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
979 case MSP430ISD::RRA: return "MSP430ISD::RRA";
980 case MSP430ISD::RLA: return "MSP430ISD::RLA";
981 case MSP430ISD::RRC: return "MSP430ISD::RRC";
982 case MSP430ISD::CALL: return "MSP430ISD::CALL";
983 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
984 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
985 case MSP430ISD::CMP: return "MSP430ISD::CMP";
986 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
987 case MSP430ISD::SHL: return "MSP430ISD::SHL";
988 case MSP430ISD::SRA: return "MSP430ISD::SRA";
992 bool MSP430TargetLowering::isTruncateFree(const Type *Ty1,
993 const Type *Ty2) const {
994 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
997 return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1000 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1001 if (!VT1.isInteger() || !VT2.isInteger())
1004 return (VT1.getSizeInBits() > VT2.getSizeInBits());
1007 bool MSP430TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
1008 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1009 return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1012 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1013 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1014 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1017 //===----------------------------------------------------------------------===//
1018 // Other Lowering Code
1019 //===----------------------------------------------------------------------===//
1022 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1023 MachineBasicBlock *BB) const {
1024 MachineFunction *F = BB->getParent();
1025 MachineRegisterInfo &RI = F->getRegInfo();
1026 DebugLoc dl = MI->getDebugLoc();
1027 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1030 const TargetRegisterClass * RC;
1031 switch (MI->getOpcode()) {
1033 assert(0 && "Invalid shift opcode!");
1035 Opc = MSP430::SHL8r1;
1036 RC = MSP430::GR8RegisterClass;
1039 Opc = MSP430::SHL16r1;
1040 RC = MSP430::GR16RegisterClass;
1043 Opc = MSP430::SAR8r1;
1044 RC = MSP430::GR8RegisterClass;
1047 Opc = MSP430::SAR16r1;
1048 RC = MSP430::GR16RegisterClass;
1051 Opc = MSP430::SAR8r1c;
1052 RC = MSP430::GR8RegisterClass;
1055 Opc = MSP430::SAR16r1c;
1056 RC = MSP430::GR16RegisterClass;
1060 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1061 MachineFunction::iterator I = BB;
1064 // Create loop block
1065 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1066 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1068 F->insert(I, LoopBB);
1069 F->insert(I, RemBB);
1071 // Update machine-CFG edges by transferring all successors of the current
1072 // block to the block containing instructions after shift.
1073 RemBB->splice(RemBB->begin(), BB,
1074 llvm::next(MachineBasicBlock::iterator(MI)),
1076 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1078 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1079 BB->addSuccessor(LoopBB);
1080 BB->addSuccessor(RemBB);
1081 LoopBB->addSuccessor(RemBB);
1082 LoopBB->addSuccessor(LoopBB);
1084 unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1085 unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1086 unsigned ShiftReg = RI.createVirtualRegister(RC);
1087 unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1088 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1089 unsigned SrcReg = MI->getOperand(1).getReg();
1090 unsigned DstReg = MI->getOperand(0).getReg();
1095 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1096 .addReg(ShiftAmtSrcReg).addImm(0);
1097 BuildMI(BB, dl, TII.get(MSP430::JCC))
1099 .addImm(MSP430CC::COND_E);
1102 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1103 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1104 // ShiftReg2 = shift ShiftReg
1105 // ShiftAmt2 = ShiftAmt - 1;
1106 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1107 .addReg(SrcReg).addMBB(BB)
1108 .addReg(ShiftReg2).addMBB(LoopBB);
1109 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1110 .addReg(ShiftAmtSrcReg).addMBB(BB)
1111 .addReg(ShiftAmtReg2).addMBB(LoopBB);
1112 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1114 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1115 .addReg(ShiftAmtReg).addImm(1);
1116 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1118 .addImm(MSP430CC::COND_NE);
1121 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1122 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1123 .addReg(SrcReg).addMBB(BB)
1124 .addReg(ShiftReg2).addMBB(LoopBB);
1126 MI->eraseFromParent(); // The pseudo instruction is gone now.
1131 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1132 MachineBasicBlock *BB) const {
1133 unsigned Opc = MI->getOpcode();
1135 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1136 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1137 Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1138 return EmitShiftInstr(MI, BB);
1140 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1141 DebugLoc dl = MI->getDebugLoc();
1143 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1144 "Unexpected instr type to insert");
1146 // To "insert" a SELECT instruction, we actually have to insert the diamond
1147 // control-flow pattern. The incoming instruction knows the destination vreg
1148 // to set, the condition code register to branch on, the true/false values to
1149 // select between, and a branch opcode to use.
1150 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1151 MachineFunction::iterator I = BB;
1157 // cmpTY ccX, r1, r2
1159 // fallthrough --> copy0MBB
1160 MachineBasicBlock *thisMBB = BB;
1161 MachineFunction *F = BB->getParent();
1162 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1163 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1164 F->insert(I, copy0MBB);
1165 F->insert(I, copy1MBB);
1166 // Update machine-CFG edges by transferring all successors of the current
1167 // block to the new block which will contain the Phi node for the select.
1168 copy1MBB->splice(copy1MBB->begin(), BB,
1169 llvm::next(MachineBasicBlock::iterator(MI)),
1171 copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1172 // Next, add the true and fallthrough blocks as its successors.
1173 BB->addSuccessor(copy0MBB);
1174 BB->addSuccessor(copy1MBB);
1176 BuildMI(BB, dl, TII.get(MSP430::JCC))
1178 .addImm(MI->getOperand(3).getImm());
1181 // %FalseValue = ...
1182 // # fallthrough to copy1MBB
1185 // Update machine-CFG edges
1186 BB->addSuccessor(copy1MBB);
1189 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1192 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1193 MI->getOperand(0).getReg())
1194 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1195 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1197 MI->eraseFromParent(); // The pseudo instruction is gone now.