1 //===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MSP430 target.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430ISelLowering.h"
16 #include "MSP430TargetMachine.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Intrinsics.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/Statistic.h"
40 ViewRMWDAGs("view-msp430-rmw-dags", cl::Hidden,
41 cl::desc("Pop up a window to show isel dags after RMW preprocess"));
43 static const bool ViewRMWDAGs = false;
46 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
48 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
49 /// instructions for SelectionDAG operations.
52 class MSP430DAGToDAGISel : public SelectionDAGISel {
53 MSP430TargetLowering &Lowering;
54 const MSP430Subtarget &Subtarget;
57 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
58 : SelectionDAGISel(TM, OptLevel),
59 Lowering(*TM.getTargetLowering()),
60 Subtarget(*TM.getSubtargetImpl()) { }
62 virtual void InstructionSelect();
64 virtual const char *getPassName() const {
65 return "MSP430 DAG->DAG Pattern Instruction Selection";
69 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
70 std::vector<SDValue> &OutOps);
72 // Include the pieces autogenerated from the target description.
73 #include "MSP430GenDAGISel.inc"
76 void PreprocessForRMW();
77 SDNode *Select(SDValue Op);
78 bool SelectAddr(SDValue Op, SDValue Addr, SDValue &Base, SDValue &Disp);
84 } // end anonymous namespace
86 /// createMSP430ISelDag - This pass converts a legalized DAG into a
87 /// MSP430-specific DAG, ready for instruction scheduling.
89 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
90 CodeGenOpt::Level OptLevel) {
91 return new MSP430DAGToDAGISel(TM, OptLevel);
94 // FIXME: This is pretty dummy routine and needs to be rewritten in the future.
95 bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr,
96 SDValue &Base, SDValue &Disp) {
97 // Try to match frame address first.
98 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
99 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
100 Disp = CurDAG->getTargetConstant(0, MVT::i16);
104 switch (Addr.getOpcode()) {
106 // Operand is a result from ADD with constant operand which fits into i16.
107 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
108 uint64_t CVal = CN->getZExtValue();
109 // Offset should fit into 16 bits.
110 if (((CVal << 48) >> 48) == CVal) {
111 SDValue N0 = Addr.getOperand(0);
112 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N0))
113 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
117 Disp = CurDAG->getTargetConstant(CVal, MVT::i16);
122 case MSP430ISD::Wrapper:
123 SDValue N0 = Addr.getOperand(0);
124 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
125 Base = CurDAG->getTargetGlobalAddress(G->getGlobal(),
126 MVT::i16, G->getOffset());
127 Disp = CurDAG->getTargetConstant(0, MVT::i16);
129 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(N0)) {
130 Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), MVT::i16);
131 Disp = CurDAG->getTargetConstant(0, MVT::i16);
137 Disp = CurDAG->getTargetConstant(0, MVT::i16);
143 bool MSP430DAGToDAGISel::
144 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
145 std::vector<SDValue> &OutOps) {
147 switch (ConstraintCode) {
148 default: return true;
150 if (!SelectAddr(Op, Op, Op0, Op1))
155 OutOps.push_back(Op0);
156 OutOps.push_back(Op1);
160 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
161 /// and move load below the TokenFactor. Replace store's chain operand with
162 /// load's chain result.
163 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
164 SDValue Store, SDValue TF) {
165 SmallVector<SDValue, 4> Ops;
166 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
167 if (Load.getNode() == TF.getOperand(i).getNode())
168 Ops.push_back(Load.getOperand(0));
170 Ops.push_back(TF.getOperand(i));
171 SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
172 SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
175 CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
176 Store.getOperand(2), Store.getOperand(3));
179 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
180 /// The chain produced by the load must only be used by the store's chain
181 /// operand, otherwise this may produce a cycle in the DAG.
182 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
184 if (N.getOpcode() == ISD::BIT_CONVERT)
187 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
188 if (!LD || LD->isVolatile())
190 if (LD->getAddressingMode() != ISD::UNINDEXED)
193 ISD::LoadExtType ExtType = LD->getExtensionType();
194 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
198 LD->hasNUsesOfValue(1, 1) &&
199 N.getOperand(1) == Address &&
200 LD->isOperandOf(Chain.getNode())) {
207 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
208 /// This is only run if not in -O0 mode.
209 /// This allows the instruction selector to pick more read-modify-write
210 /// instructions. This is a common case:
220 /// [TokenFactor] [Op]
227 /// The fact the store's chain operand != load's chain will prevent the
228 /// (store (op (load))) instruction from being selected. We can transform it to:
247 void MSP430DAGToDAGISel::PreprocessForRMW() {
248 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
249 E = CurDAG->allnodes_end(); I != E; ++I) {
250 if (!ISD::isNON_TRUNCStore(I))
252 SDValue Chain = I->getOperand(0);
254 if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
257 SDValue N1 = I->getOperand(1);
258 SDValue N2 = I->getOperand(2);
259 if ((N1.getValueType().isFloatingPoint() &&
260 !N1.getValueType().isVector()) ||
266 unsigned Opcode = N1.getNode()->getOpcode();
274 SDValue N10 = N1.getOperand(0);
275 SDValue N11 = N1.getOperand(1);
276 RModW = isRMWLoad(N10, Chain, N2, Load);
278 RModW = isRMWLoad(N11, Chain, N2, Load);
284 SDValue N10 = N1.getOperand(0);
285 RModW = isRMWLoad(N10, Chain, N2, Load);
291 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
297 /// InstructionSelect - This callback is invoked by
298 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
299 void MSP430DAGToDAGISel::InstructionSelect() {
300 std::string BlockName;
302 BlockName = MF->getFunction()->getNameStr() + ":" +
303 BB->getBasicBlock()->getNameStr();
307 if (ViewRMWDAGs) CurDAG->viewGraph("RMW preprocessed:" + BlockName);
309 DEBUG(errs() << "Selection DAG after RMW preprocessing:\n");
310 DEBUG(CurDAG->dump());
314 // Codegen the basic block.
315 DEBUG(errs() << "===== Instruction selection begins:\n");
318 DEBUG(errs() << "===== Instruction selection ends:\n");
320 CurDAG->RemoveDeadNodes();
323 SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
324 SDNode *Node = Op.getNode();
325 DebugLoc dl = Op.getDebugLoc();
327 // Dump information about the Node being selected
328 DEBUG(errs().indent(Indent) << "Selecting: ");
329 DEBUG(Node->dump(CurDAG));
330 DEBUG(errs() << "\n");
333 // If we have a custom node, we already have selected!
334 if (Node->isMachineOpcode()) {
335 DEBUG(errs().indent(Indent-2) << "== ";
342 // Few custom selection stuff.
343 switch (Node->getOpcode()) {
345 case ISD::FrameIndex: {
346 assert(Op.getValueType() == MVT::i16);
347 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
348 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
349 if (Node->hasOneUse())
350 return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
351 TFI, CurDAG->getTargetConstant(0, MVT::i16));
352 return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16,
353 TFI, CurDAG->getTargetConstant(0, MVT::i16));
357 // Select the default instruction
358 SDNode *ResNode = SelectCode(Op);
360 DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
361 if (ResNode == NULL || ResNode == Op.getNode())
362 DEBUG(Op.getNode()->dump(CurDAG));
364 DEBUG(ResNode->dump(CurDAG));
365 DEBUG(errs() << "\n");