1 //===- MBlazeInstrInfo.cpp - MBlaze Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MBlaze implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MBlazeInstrInfo.h"
15 #include "MBlazeTargetMachine.h"
16 #include "MBlazeMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "MBlazeGenInstrInfo.inc"
25 MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
26 : TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts)),
27 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
29 static bool isZeroImm(const MachineOperand &op) {
30 return op.isImm() && op.getImm() == 0;
33 /// isLoadFromStackSlot - If the specified machine instruction is a direct
34 /// load from a stack slot, return the virtual or physical register number of
35 /// the destination along with the FrameIndex of the loaded stack slot. If
36 /// not, return 0. This predicate must return 0 if the instruction has
37 /// any side effects other than loading from the stack slot.
38 unsigned MBlazeInstrInfo::
39 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {
40 if (MI->getOpcode() == MBlaze::LWI) {
41 if ((MI->getOperand(1).isFI()) && // is a stack slot
42 (MI->getOperand(2).isImm()) && // the imm is zero
43 (isZeroImm(MI->getOperand(2)))) {
44 FrameIndex = MI->getOperand(1).getIndex();
45 return MI->getOperand(0).getReg();
52 /// isStoreToStackSlot - If the specified machine instruction is a direct
53 /// store to a stack slot, return the virtual or physical register number of
54 /// the source reg along with the FrameIndex of the loaded stack slot. If
55 /// not, return 0. This predicate must return 0 if the instruction has
56 /// any side effects other than storing to the stack slot.
57 unsigned MBlazeInstrInfo::
58 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {
59 if (MI->getOpcode() == MBlaze::SWI) {
60 if ((MI->getOperand(1).isFI()) && // is a stack slot
61 (MI->getOperand(2).isImm()) && // the imm is zero
62 (isZeroImm(MI->getOperand(2)))) {
63 FrameIndex = MI->getOperand(1).getIndex();
64 return MI->getOperand(0).getReg();
70 /// insertNoop - If data hazard condition is found insert the target nop
72 void MBlazeInstrInfo::
73 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
75 BuildMI(MBB, MI, DL, get(MBlaze::NOP));
78 void MBlazeInstrInfo::
79 copyPhysReg(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator I, DebugLoc DL,
81 unsigned DestReg, unsigned SrcReg,
83 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADD), DestReg)
84 .addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0);
87 void MBlazeInstrInfo::
88 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
89 unsigned SrcReg, bool isKill, int FI,
90 const TargetRegisterClass *RC,
91 const TargetRegisterInfo *TRI) const {
93 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
94 .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
97 void MBlazeInstrInfo::
98 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
99 unsigned DestReg, int FI,
100 const TargetRegisterClass *RC,
101 const TargetRegisterInfo *TRI) const {
103 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
104 .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
107 //===----------------------------------------------------------------------===//
109 //===----------------------------------------------------------------------===//
110 bool MBlazeInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
111 MachineBasicBlock *&TBB,
112 MachineBasicBlock *&FBB,
113 SmallVectorImpl<MachineOperand> &Cond,
114 bool AllowModify) const {
115 // If the block has no terminators, it just falls into the block after it.
116 MachineBasicBlock::iterator I = MBB.end();
117 if (I == MBB.begin())
120 while (I->isDebugValue()) {
121 if (I == MBB.begin())
125 if (!isUnpredicatedTerminator(I))
128 // Get the last instruction in the block.
129 MachineInstr *LastInst = I;
131 // If there is only one terminator instruction, process it.
132 unsigned LastOpc = LastInst->getOpcode();
133 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
134 if (MBlaze::isUncondBranchOpcode(LastOpc)) {
135 TBB = LastInst->getOperand(0).getMBB();
138 if (MBlaze::isCondBranchOpcode(LastOpc)) {
139 // Block ends with fall-through condbranch.
140 TBB = LastInst->getOperand(1).getMBB();
141 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
142 Cond.push_back(LastInst->getOperand(0));
145 // Otherwise, don't know what this is.
149 // Get the instruction before it if it's a terminator.
150 MachineInstr *SecondLastInst = I;
152 // If there are three terminators, we don't know what sort of block this is.
153 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
156 // If the block ends with something like BEQID then BRID, handle it.
157 if (MBlaze::isCondBranchOpcode(SecondLastInst->getOpcode()) &&
158 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
159 TBB = SecondLastInst->getOperand(1).getMBB();
160 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
161 Cond.push_back(SecondLastInst->getOperand(0));
162 FBB = LastInst->getOperand(0).getMBB();
166 // If the block ends with two unconditional branches, handle it.
167 // The second one is not executed, so remove it.
168 if (MBlaze::isUncondBranchOpcode(SecondLastInst->getOpcode()) &&
169 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
170 TBB = SecondLastInst->getOperand(0).getMBB();
173 I->eraseFromParent();
177 // Otherwise, can't handle this.
181 unsigned MBlazeInstrInfo::
182 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
183 MachineBasicBlock *FBB,
184 const SmallVectorImpl<MachineOperand> &Cond,
186 // Shouldn't be a fall through.
187 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
188 assert((Cond.size() == 2 || Cond.size() == 0) &&
189 "MBlaze branch conditions have two components!");
191 unsigned Opc = MBlaze::BRID;
193 Opc = (unsigned)Cond[0].getImm();
196 if (Cond.empty()) // Unconditional branch
197 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
198 else // Conditional branch
199 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
203 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
204 BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB);
208 unsigned MBlazeInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
209 MachineBasicBlock::iterator I = MBB.end();
210 if (I == MBB.begin()) return 0;
212 while (I->isDebugValue()) {
213 if (I == MBB.begin())
218 if (!MBlaze::isUncondBranchOpcode(I->getOpcode()) &&
219 !MBlaze::isCondBranchOpcode(I->getOpcode()))
222 // Remove the branch.
223 I->eraseFromParent();
227 if (I == MBB.begin()) return 1;
229 if (!MBlaze::isCondBranchOpcode(I->getOpcode()))
232 // Remove the branch.
233 I->eraseFromParent();
238 /// getGlobalBaseReg - Return a virtual register initialized with the
239 /// the global base register value. Output instructions required to
240 /// initialize the register in the function entry block, if necessary.
242 unsigned MBlazeInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
243 MBlazeFunctionInfo *MBlazeFI = MF->getInfo<MBlazeFunctionInfo>();
244 unsigned GlobalBaseReg = MBlazeFI->getGlobalBaseReg();
245 if (GlobalBaseReg != 0)
246 return GlobalBaseReg;
248 // Insert the set of GlobalBaseReg into the first MBB of the function
249 MachineBasicBlock &FirstMBB = MF->front();
250 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
251 MachineRegisterInfo &RegInfo = MF->getRegInfo();
252 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
254 GlobalBaseReg = RegInfo.createVirtualRegister(MBlaze::GPRRegisterClass);
255 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
256 GlobalBaseReg).addReg(MBlaze::R20);
257 RegInfo.addLiveIn(MBlaze::R20);
259 MBlazeFI->setGlobalBaseReg(GlobalBaseReg);
260 return GlobalBaseReg;