1 //===- MBlazeInstrFPU.td - MBlaze FPU Instruction defs -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // MBlaze profiles and nodes
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MBlaze Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 // Memory Access Instructions
20 //===----------------------------------------------------------------------===//
21 class LoadFM<bits<6> op, string instr_asm, PatFrag OpNode> :
22 TA<op, 0x000, (outs GPR:$dst), (ins memrr:$addr),
23 !strconcat(instr_asm, " $dst, $addr"),
24 [(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IILoad>;
26 class LoadFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
27 TB<op, (outs GPR:$dst), (ins memri:$addr),
28 !strconcat(instr_asm, " $dst, $addr"),
29 [(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>;
31 class StoreFM<bits<6> op, string instr_asm, PatFrag OpNode> :
32 TA<op, 0x000, (outs), (ins GPR:$dst, memrr:$addr),
33 !strconcat(instr_asm, " $dst, $addr"),
34 [(OpNode (f32 GPR:$dst), xaddr:$addr)], IIStore>;
36 class StoreFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
37 TB<op, (outs), (ins GPR:$dst, memrr:$addr),
38 !strconcat(instr_asm, " $dst, $addr"),
39 [(OpNode (f32 GPR:$dst), iaddr:$addr)], IIStore>;
41 class ArithF<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
42 InstrItinClass itin> :
43 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
44 !strconcat(instr_asm, " $dst, $b, $c"),
45 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
47 class CmpFN<bits<6> op, bits<11> flags, string instr_asm,
48 InstrItinClass itin> :
49 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
50 !strconcat(instr_asm, " $dst, $b, $c"),
53 class ArithFR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
54 InstrItinClass itin> :
55 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
56 !strconcat(instr_asm, " $dst, $c, $b"),
57 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
59 class LogicF<bits<6> op, string instr_asm> :
60 TB<op, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
61 !strconcat(instr_asm, " $dst, $b, $c"),
64 class LogicFI<bits<6> op, string instr_asm> :
65 TB<op, (outs GPR:$dst), (ins GPR:$b, fimm:$c),
66 !strconcat(instr_asm, " $dst, $b, $c"),
70 class ArithF2<bits<6> op, bits<11> flags, string instr_asm,
71 InstrItinClass itin> :
72 TA<op, flags, (outs GPR:$dst), (ins GPR:$b),
73 !strconcat(instr_asm, " $dst, $b"),
76 class ArithIF<bits<6> op, bits<11> flags, string instr_asm,
77 InstrItinClass itin> :
78 TA<op, flags, (outs GPR:$dst), (ins GPR:$b),
79 !strconcat(instr_asm, " $dst, $b"),
82 class ArithFI<bits<6> op, bits<11> flags, string instr_asm,
83 InstrItinClass itin> :
84 TA<op, flags, (outs GPR:$dst), (ins GPR:$b),
85 !strconcat(instr_asm, " $dst, $b"),
89 //===----------------------------------------------------------------------===//
90 // Pseudo instructions
91 //===----------------------------------------------------------------------===//
93 //===----------------------------------------------------------------------===//
94 // FPU Arithmetic Instructions
95 //===----------------------------------------------------------------------===//
96 let Predicates=[HasFPU] in {
97 def FORI : LogicFI<0x28, "ori ">;
98 def FADD : ArithF<0x16, 0x000, "fadd ", fadd, IIAlu>;
99 def FRSUB : ArithFR<0x16, 0x080, "frsub ", fsub, IIAlu>;
100 def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIAlu>;
101 def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIAlu>;
103 def LWF : LoadFM<0x32, "lw ", load>;
104 def LWFI : LoadFMI<0x32, "lwi ", load>;
106 def SWF : StoreFM<0x32, "sw ", store>;
107 def SWFI : StoreFMI<0x32, "swi ", store>;
110 let Predicates=[HasFPU,HasSqrt] in {
111 def FLT : ArithIF<0x16, 0x280, "flt ", IIAlu>;
112 def FINT : ArithFI<0x16, 0x300, "fint ", IIAlu>;
113 def FSQRT : ArithF2<0x16, 0x300, "fsqrt ", IIAlu>;
116 let isAsCheapAsAMove = 1 in {
117 def FCMP_UN : CmpFN<0x16, 0x200, "fcmp.un", IIAlu>;
118 def FCMP_LT : CmpFN<0x16, 0x210, "fcmp.lt", IIAlu>;
119 def FCMP_EQ : CmpFN<0x16, 0x220, "fcmp.eq", IIAlu>;
120 def FCMP_LE : CmpFN<0x16, 0x230, "fcmp.le", IIAlu>;
121 def FCMP_GT : CmpFN<0x16, 0x240, "fcmp.gt", IIAlu>;
122 def FCMP_NE : CmpFN<0x16, 0x250, "fcmp.ne", IIAlu>;
123 def FCMP_GE : CmpFN<0x16, 0x260, "fcmp.ge", IIAlu>;
127 let usesCustomInserter = 1, isCodeGenOnly = 1 in {
128 def Select_FCC : MBlazePseudo<(outs GPR:$dst),
129 (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC),
130 "; SELECT_FCC PSEUDO!",
134 // Floating point conversions
135 let Predicates=[HasFPU] in {
136 def : Pat<(sint_to_fp GPR:$V), (FLT GPR:$V)>;
137 def : Pat<(fp_to_sint GPR:$V), (FINT GPR:$V)>;
138 def : Pat<(fsqrt GPR:$V), (FSQRT GPR:$V)>;
142 let Predicates=[HasFPU] in {
143 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
144 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
145 (FCMP_EQ GPR:$L, GPR:$R), 2)>;
146 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
147 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
148 (FCMP_EQ GPR:$L, GPR:$R), 1)>;
149 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
150 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
151 (FCMP_EQ GPR:$L, GPR:$R), 2)>;
152 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
153 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
154 (XOR (FCMP_UN GPR:$L, GPR:$R),
155 (FCMP_EQ GPR:$L, GPR:$R)), 2)>;
156 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
157 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
158 (OR (FCMP_UN GPR:$L, GPR:$R),
159 (FCMP_EQ GPR:$L, GPR:$R)), 2)>;
160 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
161 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
162 (FCMP_GT GPR:$L, GPR:$R), 2)>;
163 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
164 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
165 (FCMP_LT GPR:$L, GPR:$R), 2)>;
166 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE),
167 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
168 (FCMP_GE GPR:$L, GPR:$R), 2)>;
169 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE),
170 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
171 (FCMP_LE GPR:$L, GPR:$R), 2)>;
172 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT),
173 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
174 (FCMP_GT GPR:$L, GPR:$R), 2)>;
175 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLT),
176 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
177 (FCMP_LT GPR:$L, GPR:$R), 2)>;
178 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGE),
179 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
180 (FCMP_GE GPR:$L, GPR:$R), 2)>;
181 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLE),
182 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
183 (FCMP_LE GPR:$L, GPR:$R), 2)>;
184 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUEQ),
185 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
186 (OR (FCMP_UN GPR:$L, GPR:$R),
187 (FCMP_EQ GPR:$L, GPR:$R)), 2)>;
188 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUNE),
189 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
190 (FCMP_NE GPR:$L, GPR:$R), 2)>;
191 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGT),
192 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
193 (OR (FCMP_UN GPR:$L, GPR:$R),
194 (FCMP_GT GPR:$L, GPR:$R)), 2)>;
195 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULT),
196 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
197 (OR (FCMP_UN GPR:$L, GPR:$R),
198 (FCMP_LT GPR:$L, GPR:$R)), 2)>;
199 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGE),
200 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
201 (OR (FCMP_UN GPR:$L, GPR:$R),
202 (FCMP_GE GPR:$L, GPR:$R)), 2)>;
203 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULE),
204 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
205 (OR (FCMP_UN GPR:$L, GPR:$R),
206 (FCMP_LE GPR:$L, GPR:$R)), 2)>;
207 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETO),
208 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
209 (FCMP_UN GPR:$L, GPR:$R), 1)>;
210 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUO),
211 (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
212 (FCMP_UN GPR:$L, GPR:$R), 2)>;
216 def : Pat<(select (i32 GPR:$C), (f32 GPR:$T), (f32 GPR:$F)),
217 (Select_FCC GPR:$T, GPR:$F, GPR:$C, 2)>;
219 //===----------------------------------------------------------------------===//
220 // Patterns for Floating Point Instructions
221 //===----------------------------------------------------------------------===//
222 def : Pat<(f32 fpimm:$imm), (FORI (i32 R0), fpimm:$imm)>;