1 //===-- MBlazeISelLowering.cpp - MBlaze DAG Lowering Implementation -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that MBlaze uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mblaze-lower"
16 #include "MBlazeISelLowering.h"
17 #include "MBlazeMachineFunction.h"
18 #include "MBlazeTargetMachine.h"
19 #include "MBlazeTargetObjectFile.h"
20 #include "MBlazeSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
38 const char *MBlazeTargetLowering::getTargetNodeName(unsigned Opcode) const {
40 case MBlazeISD::JmpLink : return "MBlazeISD::JmpLink";
41 case MBlazeISD::GPRel : return "MBlazeISD::GPRel";
42 case MBlazeISD::Wrap : return "MBlazeISD::Wrap";
43 case MBlazeISD::ICmp : return "MBlazeISD::ICmp";
44 case MBlazeISD::Ret : return "MBlazeISD::Ret";
45 case MBlazeISD::Select_CC : return "MBlazeISD::Select_CC";
46 default : return NULL;
50 MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
51 : TargetLowering(TM, new MBlazeTargetObjectFile()) {
52 Subtarget = &TM.getSubtarget<MBlazeSubtarget>();
54 // MBlaze does not have i1 type, so use i32 for
55 // setcc operations results (slt, sgt, ...).
56 setBooleanContents(ZeroOrOneBooleanContent);
58 // Set up the register classes
59 addRegisterClass(MVT::i32, MBlaze::CPURegsRegisterClass);
60 if (Subtarget->hasFPU()) {
61 addRegisterClass(MVT::f32, MBlaze::FGR32RegisterClass);
62 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
65 // Floating point operations which are not supported
66 setOperationAction(ISD::FREM, MVT::f32, Expand);
67 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand);
68 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand);
69 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
70 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
71 setOperationAction(ISD::FP_ROUND, MVT::f32, Expand);
72 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
73 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
74 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
75 setOperationAction(ISD::FSIN, MVT::f32, Expand);
76 setOperationAction(ISD::FCOS, MVT::f32, Expand);
77 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
78 setOperationAction(ISD::FPOW, MVT::f32, Expand);
79 setOperationAction(ISD::FLOG, MVT::f32, Expand);
80 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
81 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
82 setOperationAction(ISD::FEXP, MVT::f32, Expand);
84 // Load extented operations for i1 types must be promoted
85 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
86 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 // MBlaze has no REM or DIVREM operations.
90 setOperationAction(ISD::UREM, MVT::i32, Expand);
91 setOperationAction(ISD::SREM, MVT::i32, Expand);
92 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
93 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
95 // If the processor doesn't support multiply then expand it
96 if (!Subtarget->hasMul()) {
97 setOperationAction(ISD::MUL, MVT::i32, Expand);
100 // If the processor doesn't support 64-bit multiply then expand
101 if (!Subtarget->hasMul() || !Subtarget->hasMul64()) {
102 setOperationAction(ISD::MULHS, MVT::i32, Expand);
103 setOperationAction(ISD::MULHS, MVT::i64, Expand);
104 setOperationAction(ISD::MULHU, MVT::i32, Expand);
105 setOperationAction(ISD::MULHU, MVT::i64, Expand);
108 // If the processor doesn't support division then expand
109 if (!Subtarget->hasDiv()) {
110 setOperationAction(ISD::UDIV, MVT::i32, Expand);
111 setOperationAction(ISD::SDIV, MVT::i32, Expand);
114 // Expand unsupported conversions
115 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
116 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
119 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
121 // MBlaze doesn't have MUL_LOHI
122 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
123 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
124 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
125 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
127 // Used by legalize types to correctly generate the setcc result.
128 // Without this, every float setcc comes with a AND/OR with the result,
129 // we don't want this, since the fpcmp result goes to a flag register,
130 // which is used implicitly by brcond and select operations.
131 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
132 AddPromotedToType(ISD::SELECT, MVT::i1, MVT::i32);
133 AddPromotedToType(ISD::SELECT_CC, MVT::i1, MVT::i32);
135 // MBlaze Custom Operations
136 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
137 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
138 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
139 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
141 // Variable Argument support
142 setOperationAction(ISD::VASTART, MVT::Other, Custom);
143 setOperationAction(ISD::VAEND, MVT::Other, Expand);
144 setOperationAction(ISD::VAARG, MVT::Other, Expand);
145 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
148 // Operations not directly supported by MBlaze.
149 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
150 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
151 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
152 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
153 setOperationAction(ISD::ROTL, MVT::i32, Expand);
154 setOperationAction(ISD::ROTR, MVT::i32, Expand);
155 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
156 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
157 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
158 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
159 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
160 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
161 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
163 // We don't have line number support yet.
164 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
166 // Use the default for now
167 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
168 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
169 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
171 // MBlaze doesn't have extending float->double load/store
172 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
173 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
175 setStackPointerRegisterToSaveRestore(MBlaze::R1);
176 computeRegisterProperties();
179 MVT::SimpleValueType MBlazeTargetLowering::getSetCCResultType(EVT VT) const {
183 /// getFunctionAlignment - Return the Log2 alignment of this function.
184 unsigned MBlazeTargetLowering::getFunctionAlignment(const Function *) const {
188 SDValue MBlazeTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
189 switch (Op.getOpcode())
191 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
192 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
193 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
194 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
195 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
196 case ISD::VASTART: return LowerVASTART(Op, DAG);
201 //===----------------------------------------------------------------------===//
202 // Lower helper functions
203 //===----------------------------------------------------------------------===//
204 MachineBasicBlock* MBlazeTargetLowering::
205 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB,
206 DenseMap<MachineBasicBlock*,
207 MachineBasicBlock*> *EM) const {
208 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
209 DebugLoc dl = MI->getDebugLoc();
211 switch (MI->getOpcode()) {
212 default: assert(false && "Unexpected instr type to insert");
213 case MBlaze::ShiftRL:
214 case MBlaze::ShiftRA:
215 case MBlaze::ShiftL: {
216 // To "insert" a shift left instruction, we actually have to insert a
217 // simple loop. The incoming instruction knows the destination vreg to
218 // set, the source vreg to operate over and the shift amount.
219 const BasicBlock *LLVM_BB = BB->getBasicBlock();
220 MachineFunction::iterator It = BB;
224 // andi samt, samt, 31
225 // beqid samt, finish
228 // addik samt, samt, -1
233 MachineFunction *F = BB->getParent();
234 MachineRegisterInfo &R = F->getRegInfo();
235 MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
236 MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB);
238 unsigned IAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
239 BuildMI(BB, dl, TII->get(MBlaze::ANDI), IAMT)
240 .addReg(MI->getOperand(2).getReg())
243 unsigned IVAL = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
244 BuildMI(BB, dl, TII->get(MBlaze::ADDI), IVAL)
245 .addReg(MI->getOperand(1).getReg())
248 BuildMI(BB, dl, TII->get(MBlaze::BEQID))
253 F->insert(It, finish);
255 // Update machine-CFG edges by first adding all successors of the current
256 // block to the new block which will contain the Phi node for the select.
257 // Also inform sdisel of the edge changes.
258 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
259 e = BB->succ_end(); i != e; ++i) {
260 EM->insert(std::make_pair(*i, finish));
261 finish->addSuccessor(*i);
264 // Next, remove all successors of the current block, and add the true
265 // and fallthrough blocks as its successors.
266 while(!BB->succ_empty())
267 BB->removeSuccessor(BB->succ_begin());
268 BB->addSuccessor(loop);
269 BB->addSuccessor(finish);
271 // Next, add the finish block as a successor of the loop block
272 loop->addSuccessor(finish);
273 loop->addSuccessor(loop);
275 unsigned DST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
276 unsigned NDST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
277 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
278 .addReg(IVAL).addMBB(BB)
279 .addReg(NDST).addMBB(loop);
281 unsigned SAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
282 unsigned NAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
283 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
284 .addReg(IAMT).addMBB(BB)
285 .addReg(NAMT).addMBB(loop);
287 if (MI->getOpcode() == MBlaze::ShiftL)
288 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
289 else if (MI->getOpcode() == MBlaze::ShiftRA)
290 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
291 else if (MI->getOpcode() == MBlaze::ShiftRL)
292 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
294 llvm_unreachable( "Cannot lower unknown shift instruction" );
296 BuildMI(loop, dl, TII->get(MBlaze::ADDI), NAMT)
300 BuildMI(loop, dl, TII->get(MBlaze::BNEID))
304 BuildMI(finish, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
305 .addReg(IVAL).addMBB(BB)
306 .addReg(NDST).addMBB(loop);
308 // The pseudo instruction is no longer needed so remove it
309 F->DeleteMachineInstr(MI);
313 case MBlaze::Select_FCC:
314 case MBlaze::Select_CC: {
315 // To "insert" a SELECT_CC instruction, we actually have to insert the
316 // diamond control-flow pattern. The incoming instruction knows the
317 // destination vreg to set, the condition code register to branch on, the
318 // true/false values to select between, and a branch opcode to use.
319 const BasicBlock *LLVM_BB = BB->getBasicBlock();
320 MachineFunction::iterator It = BB;
327 // bNE r1, r0, copy1MBB
328 // fallthrough --> copy0MBB
329 MachineFunction *F = BB->getParent();
330 MachineBasicBlock *flsBB = F->CreateMachineBasicBlock(LLVM_BB);
331 MachineBasicBlock *dneBB = F->CreateMachineBasicBlock(LLVM_BB);
334 switch (MI->getOperand(4).getImm()) {
335 default: llvm_unreachable( "Unknown branch condition" );
336 case MBlazeCC::EQ: Opc = MBlaze::BNEID; break;
337 case MBlazeCC::NE: Opc = MBlaze::BEQID; break;
338 case MBlazeCC::GT: Opc = MBlaze::BLEID; break;
339 case MBlazeCC::LT: Opc = MBlaze::BGEID; break;
340 case MBlazeCC::GE: Opc = MBlaze::BLTID; break;
341 case MBlazeCC::LE: Opc = MBlaze::BGTID; break;
344 BuildMI(BB, dl, TII->get(Opc))
345 .addReg(MI->getOperand(3).getReg())
348 F->insert(It, flsBB);
349 F->insert(It, dneBB);
351 // Update machine-CFG edges by first adding all successors of the current
352 // block to the new block which will contain the Phi node for the select.
353 // Also inform sdisel of the edge changes.
354 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
355 e = BB->succ_end(); i != e; ++i) {
356 EM->insert(std::make_pair(*i, dneBB));
357 dneBB->addSuccessor(*i);
360 // Next, remove all successors of the current block, and add the true
361 // and fallthrough blocks as its successors.
362 while(!BB->succ_empty())
363 BB->removeSuccessor(BB->succ_begin());
364 BB->addSuccessor(flsBB);
365 BB->addSuccessor(dneBB);
366 flsBB->addSuccessor(dneBB);
369 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
371 //BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
372 // .addReg(MI->getOperand(1).getReg()).addMBB(flsBB)
373 // .addReg(MI->getOperand(2).getReg()).addMBB(BB);
375 BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
376 .addReg(MI->getOperand(2).getReg()).addMBB(flsBB)
377 .addReg(MI->getOperand(1).getReg()).addMBB(BB);
379 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
385 //===----------------------------------------------------------------------===//
386 // Misc Lower Operation implementation
387 //===----------------------------------------------------------------------===//
390 SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
391 SDValue LHS = Op.getOperand(0);
392 SDValue RHS = Op.getOperand(1);
393 SDValue TrueVal = Op.getOperand(2);
394 SDValue FalseVal = Op.getOperand(3);
395 DebugLoc dl = Op.getDebugLoc();
399 if (LHS.getValueType() == MVT::i32) {
400 Opc = MBlazeISD::Select_CC;
401 CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT::i32, LHS, RHS)
404 llvm_unreachable( "Cannot lower select_cc with unknown type" );
407 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
411 SDValue MBlazeTargetLowering::
412 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
413 // FIXME there isn't actually debug info here
414 DebugLoc dl = Op.getDebugLoc();
415 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
416 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
418 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, GA);
421 SDValue MBlazeTargetLowering::
422 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
423 llvm_unreachable("TLS not implemented for MicroBlaze.");
424 return SDValue(); // Not reached
427 SDValue MBlazeTargetLowering::
428 LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
431 // FIXME there isn't actually debug info here
432 DebugLoc dl = Op.getDebugLoc();
433 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
434 unsigned char OpFlag = IsPIC ? MBlazeII::MO_GOT : MBlazeII::MO_ABS_HILO;
436 EVT PtrVT = Op.getValueType();
437 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
439 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
440 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, JTI);
444 SDValue MBlazeTargetLowering::
445 LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
447 EVT PtrVT = Op.getValueType();
448 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
449 const Constant *C = N->getConstVal();
450 SDValue Zero = DAG.getConstant(0, PtrVT);
451 DebugLoc dl = Op.getDebugLoc();
453 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
454 N->getOffset(), MBlazeII::MO_ABS_HILO);
455 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP);
458 SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
459 MachineFunction &MF = DAG.getMachineFunction();
460 MBlazeFunctionInfo *FuncInfo = MF.getInfo<MBlazeFunctionInfo>();
462 DebugLoc dl = Op.getDebugLoc();
463 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
466 // vastart just stores the address of the VarArgsFrameIndex slot into the
467 // memory location argument.
468 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
469 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), SV, 0,
473 //===----------------------------------------------------------------------===//
474 // Calling Convention Implementation
475 //===----------------------------------------------------------------------===//
477 #include "MBlazeGenCallingConv.inc"
479 static bool CC_MBlaze2(unsigned ValNo, EVT ValVT,
480 EVT LocVT, CCValAssign::LocInfo LocInfo,
481 ISD::ArgFlagsTy ArgFlags, CCState &State) {
482 static const unsigned RegsSize=6;
483 static const unsigned IntRegs[] = {
484 MBlaze::R5, MBlaze::R6, MBlaze::R7,
485 MBlaze::R8, MBlaze::R9, MBlaze::R10
488 static const unsigned FltRegs[] = {
489 MBlaze::F5, MBlaze::F6, MBlaze::F7,
490 MBlaze::F8, MBlaze::F9, MBlaze::F10
495 // Promote i8 and i16
496 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
498 if (ArgFlags.isSExt())
499 LocInfo = CCValAssign::SExt;
500 else if (ArgFlags.isZExt())
501 LocInfo = CCValAssign::ZExt;
503 LocInfo = CCValAssign::AExt;
506 if (ValVT == MVT::i32) {
507 Reg = State.AllocateReg(IntRegs, RegsSize);
509 } else if (ValVT == MVT::f32) {
510 Reg = State.AllocateReg(FltRegs, RegsSize);
515 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
516 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
517 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
519 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
520 State.AllocateStack(SizeInBytes, SizeInBytes);
521 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
524 return false; // CC must always match
527 //===----------------------------------------------------------------------===//
528 // Call Calling Convention Implementation
529 //===----------------------------------------------------------------------===//
531 /// LowerCall - functions arguments are copied from virtual regs to
532 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
533 /// TODO: isVarArg, isTailCall.
534 SDValue MBlazeTargetLowering::
535 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
536 bool isVarArg, bool &isTailCall,
537 const SmallVectorImpl<ISD::OutputArg> &Outs,
538 const SmallVectorImpl<ISD::InputArg> &Ins,
539 DebugLoc dl, SelectionDAG &DAG,
540 SmallVectorImpl<SDValue> &InVals) {
541 // MBlaze does not yet support tail call optimization
544 MachineFunction &MF = DAG.getMachineFunction();
545 MachineFrameInfo *MFI = MF.getFrameInfo();
547 // Analyze operands of the call, assigning locations to each operand.
548 SmallVector<CCValAssign, 16> ArgLocs;
549 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
551 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze2);
553 // Get a count of how many bytes are to be pushed on the stack.
554 unsigned NumBytes = CCInfo.getNextStackOffset();
555 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
557 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
558 SmallVector<SDValue, 8> MemOpChains;
560 // First/LastArgStackLoc contains the first/last
561 // "at stack" argument location.
562 int LastArgStackLoc = 0;
563 unsigned FirstStackArgLoc = 0;
565 // Walk the register/memloc assignments, inserting copies/loads.
566 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
567 CCValAssign &VA = ArgLocs[i];
568 EVT RegVT = VA.getLocVT();
569 SDValue Arg = Outs[i].Val;
571 // Promote the value if needed.
572 switch (VA.getLocInfo()) {
573 default: llvm_unreachable("Unknown loc info!");
574 case CCValAssign::Full: break;
575 case CCValAssign::SExt:
576 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
578 case CCValAssign::ZExt:
579 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
581 case CCValAssign::AExt:
582 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
586 // Arguments that can be passed on register must be kept at
589 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
591 // Register can't get to this point...
592 assert(VA.isMemLoc());
594 // Create the frame index object for this incoming parameter
595 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
596 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
597 LastArgStackLoc, true, false);
599 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
601 // emit ISD::STORE whichs stores the
602 // parameter value to a stack Location
603 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
608 // Transform all store nodes into one single node because all store
609 // nodes are independent of each other.
610 if (!MemOpChains.empty())
611 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
612 &MemOpChains[0], MemOpChains.size());
614 // Build a sequence of copy-to-reg nodes chained together with token
615 // chain and flag operands which copy the outgoing args into registers.
616 // The InFlag in necessary since all emited instructions must be
619 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
620 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
621 RegsToPass[i].second, InFlag);
622 InFlag = Chain.getValue(1);
625 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
626 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
627 // node so that legalize doesn't hack it.
628 unsigned char OpFlag = MBlazeII::MO_NO_FLAG;
629 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
630 Callee = DAG.getTargetGlobalAddress(G->getGlobal(),
631 getPointerTy(), 0, OpFlag);
632 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
633 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
634 getPointerTy(), OpFlag);
636 // MBlazeJmpLink = #chain, #target_address, #opt_in_flags...
637 // = Chain, Callee, Reg#1, Reg#2, ...
639 // Returns a chain & a flag for retval copy to use.
640 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
641 SmallVector<SDValue, 8> Ops;
642 Ops.push_back(Chain);
643 Ops.push_back(Callee);
645 // Add argument registers to the end of the list so that they are
646 // known live into the call.
647 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
648 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
649 RegsToPass[i].second.getValueType()));
652 if (InFlag.getNode())
653 Ops.push_back(InFlag);
655 Chain = DAG.getNode(MBlazeISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
656 InFlag = Chain.getValue(1);
658 // Create the CALLSEQ_END node.
659 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
660 DAG.getIntPtrConstant(0, true), InFlag);
662 InFlag = Chain.getValue(1);
664 // Handle result values, copying them out of physregs into vregs that we
666 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
667 Ins, dl, DAG, InVals);
670 /// LowerCallResult - Lower the result values of a call into the
671 /// appropriate copies out of appropriate physical registers.
672 SDValue MBlazeTargetLowering::
673 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv,
674 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins,
675 DebugLoc dl, SelectionDAG &DAG,
676 SmallVectorImpl<SDValue> &InVals) {
677 // Assign locations to each value returned by this call.
678 SmallVector<CCValAssign, 16> RVLocs;
679 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
680 RVLocs, *DAG.getContext());
682 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze);
684 // Copy all of the result registers out of their specified physreg.
685 for (unsigned i = 0; i != RVLocs.size(); ++i) {
686 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
687 RVLocs[i].getValVT(), InFlag).getValue(1);
688 InFlag = Chain.getValue(2);
689 InVals.push_back(Chain.getValue(0));
695 //===----------------------------------------------------------------------===//
696 // Formal Arguments Calling Convention Implementation
697 //===----------------------------------------------------------------------===//
699 /// LowerFormalArguments - transform physical registers into
700 /// virtual registers and generate load operations for
701 /// arguments places on the stack.
702 SDValue MBlazeTargetLowering::
703 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
704 const SmallVectorImpl<ISD::InputArg> &Ins,
705 DebugLoc dl, SelectionDAG &DAG,
706 SmallVectorImpl<SDValue> &InVals) {
707 MachineFunction &MF = DAG.getMachineFunction();
708 MachineFrameInfo *MFI = MF.getFrameInfo();
709 MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
711 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
712 MBlazeFI->setVarArgsFrameIndex(0);
714 // Used with vargs to acumulate store chains.
715 std::vector<SDValue> OutChains;
717 // Keep track of the last register used for arguments
718 unsigned ArgRegEnd = 0;
720 // Assign locations to all of the incoming arguments.
721 SmallVector<CCValAssign, 16> ArgLocs;
722 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
723 ArgLocs, *DAG.getContext());
725 CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze2);
728 unsigned FirstStackArgLoc = 0;
730 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
731 CCValAssign &VA = ArgLocs[i];
733 // Arguments stored on registers
735 EVT RegVT = VA.getLocVT();
736 ArgRegEnd = VA.getLocReg();
737 TargetRegisterClass *RC = 0;
739 if (RegVT == MVT::i32)
740 RC = MBlaze::CPURegsRegisterClass;
741 else if (RegVT == MVT::f32)
742 RC = MBlaze::FGR32RegisterClass;
744 llvm_unreachable("RegVT not supported by LowerFormalArguments");
746 // Transform the arguments stored on
747 // physical registers into virtual ones
748 unsigned Reg = MF.addLiveIn(ArgRegEnd, RC);
749 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
751 // If this is an 8 or 16-bit value, it has been passed promoted
752 // to 32 bits. Insert an assert[sz]ext to capture this, then
753 // truncate to the right size. If if is a floating point value
754 // then convert to the correct type.
755 if (VA.getLocInfo() != CCValAssign::Full) {
757 if (VA.getLocInfo() == CCValAssign::SExt)
758 Opcode = ISD::AssertSext;
759 else if (VA.getLocInfo() == CCValAssign::ZExt)
760 Opcode = ISD::AssertZext;
762 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
763 DAG.getValueType(VA.getValVT()));
764 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
767 InVals.push_back(ArgValue);
769 } else { // VA.isRegLoc()
772 assert(VA.isMemLoc());
774 // The last argument is not a register
777 // The stack pointer offset is relative to the caller stack frame.
778 // Since the real stack size is unknown here, a negative SPOffset
779 // is used so there's a way to adjust these offsets when the stack
780 // size get known (on EliminateFrameIndex). A dummy SPOffset is
781 // used instead of a direct negative address (which is recorded to
782 // be used on emitPrologue) to avoid mis-calc of the first stack
783 // offset on PEI::calculateFrameObjectOffsets.
784 // Arguments are always 32-bit.
785 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
786 int FI = MFI->CreateFixedObject(ArgSize, 0, true, false);
787 MBlazeFI->recordLoadArgsFI(FI, -(ArgSize+
788 (FirstStackArgLoc + VA.getLocMemOffset())));
790 // Create load nodes to retrieve arguments from the stack
791 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
792 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
797 // To meet ABI, when VARARGS are passed on registers, the registers
798 // must have their values written to the caller stack frame. If the last
799 // argument was placed in the stack, there's no need to save any register.
800 if ((isVarArg) && ArgRegEnd) {
801 if (StackPtr.getNode() == 0)
802 StackPtr = DAG.getRegister(StackReg, getPointerTy());
804 // The last register argument that must be saved is MBlaze::R10
805 TargetRegisterClass *RC = MBlaze::CPURegsRegisterClass;
807 unsigned Begin = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R5);
808 unsigned Start = MBlazeRegisterInfo::getRegisterNumbering(ArgRegEnd+1);
809 unsigned End = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R10);
810 unsigned StackLoc = ArgLocs.size()-1 + (Start - Begin);
812 for (; Start <= End; ++Start, ++StackLoc) {
813 unsigned Reg = MBlazeRegisterInfo::getRegisterFromNumbering(Start);
814 unsigned LiveReg = MF.addLiveIn(Reg, RC);
815 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32);
817 int FI = MFI->CreateFixedObject(4, 0, true, false);
818 MBlazeFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
819 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
820 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
823 // Record the frame index of the first variable argument
824 // which is a value necessary to VASTART.
825 if (!MBlazeFI->getVarArgsFrameIndex())
826 MBlazeFI->setVarArgsFrameIndex(FI);
830 // All stores are grouped in one node to allow the matching between
831 // the size of Ins and InVals. This only happens when on varg functions
832 if (!OutChains.empty()) {
833 OutChains.push_back(Chain);
834 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
835 &OutChains[0], OutChains.size());
841 //===----------------------------------------------------------------------===//
842 // Return Value Calling Convention Implementation
843 //===----------------------------------------------------------------------===//
845 SDValue MBlazeTargetLowering::
846 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
847 const SmallVectorImpl<ISD::OutputArg> &Outs,
848 DebugLoc dl, SelectionDAG &DAG) {
849 // CCValAssign - represent the assignment of
850 // the return value to a location
851 SmallVector<CCValAssign, 16> RVLocs;
853 // CCState - Info about the registers and stack slot.
854 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
855 RVLocs, *DAG.getContext());
857 // Analize return values.
858 CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze);
860 // If this is the first return lowered for this function, add
861 // the regs to the liveout set for the function.
862 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
863 for (unsigned i = 0; i != RVLocs.size(); ++i)
864 if (RVLocs[i].isRegLoc())
865 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
870 // Copy the result values into the output registers.
871 for (unsigned i = 0; i != RVLocs.size(); ++i) {
872 CCValAssign &VA = RVLocs[i];
873 assert(VA.isRegLoc() && "Can only return in registers!");
875 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
878 // guarantee that all emitted copies are
879 // stuck together, avoiding something bad
880 Flag = Chain.getValue(1);
883 // Return on MBlaze is always a "rtsd R15, 8"
885 return DAG.getNode(MBlazeISD::Ret, dl, MVT::Other,
886 Chain, DAG.getRegister(MBlaze::R15, MVT::i32), Flag);
888 return DAG.getNode(MBlazeISD::Ret, dl, MVT::Other,
889 Chain, DAG.getRegister(MBlaze::R15, MVT::i32));
892 //===----------------------------------------------------------------------===//
893 // MBlaze Inline Assembly Support
894 //===----------------------------------------------------------------------===//
896 /// getConstraintType - Given a constraint letter, return the type of
897 /// constraint it is for this target.
898 MBlazeTargetLowering::ConstraintType MBlazeTargetLowering::
899 getConstraintType(const std::string &Constraint) const
901 // MBlaze specific constrainy
903 // 'd' : An address register. Equivalent to r.
904 // 'y' : Equivalent to r; retained for
905 // backwards compatibility.
906 // 'f' : Floating Point registers.
907 if (Constraint.size() == 1) {
908 switch (Constraint[0]) {
913 return C_RegisterClass;
917 return TargetLowering::getConstraintType(Constraint);
920 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
921 /// return a list of registers that can be used to satisfy the constraint.
922 /// This should only be used for C_RegisterClass constraints.
923 std::pair<unsigned, const TargetRegisterClass*> MBlazeTargetLowering::
924 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
925 if (Constraint.size() == 1) {
926 switch (Constraint[0]) {
928 return std::make_pair(0U, MBlaze::CPURegsRegisterClass);
931 return std::make_pair(0U, MBlaze::FGR32RegisterClass);
934 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
937 /// Given a register class constraint, like 'r', if this corresponds directly
938 /// to an LLVM register class, return a register of 0 and the register class
940 std::vector<unsigned> MBlazeTargetLowering::
941 getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
942 if (Constraint.size() != 1)
943 return std::vector<unsigned>();
945 switch (Constraint[0]) {
948 // GCC MBlaze Constraint Letters
951 return make_vector<unsigned>(
952 MBlaze::R3, MBlaze::R4, MBlaze::R5, MBlaze::R6,
953 MBlaze::R7, MBlaze::R9, MBlaze::R10, MBlaze::R11,
954 MBlaze::R12, MBlaze::R19, MBlaze::R20, MBlaze::R21,
955 MBlaze::R22, MBlaze::R23, MBlaze::R24, MBlaze::R25,
956 MBlaze::R26, MBlaze::R27, MBlaze::R28, MBlaze::R29,
957 MBlaze::R30, MBlaze::R31, 0);
960 return make_vector<unsigned>(
961 MBlaze::F3, MBlaze::F4, MBlaze::F5, MBlaze::F6,
962 MBlaze::F7, MBlaze::F9, MBlaze::F10, MBlaze::F11,
963 MBlaze::F12, MBlaze::F19, MBlaze::F20, MBlaze::F21,
964 MBlaze::F22, MBlaze::F23, MBlaze::F24, MBlaze::F25,
965 MBlaze::F26, MBlaze::F27, MBlaze::F28, MBlaze::F29,
966 MBlaze::F30, MBlaze::F31, 0);
968 return std::vector<unsigned>();
971 bool MBlazeTargetLowering::
972 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
973 // The MBlaze target isn't yet aware of offsets.
977 bool MBlazeTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
978 return VT != MVT::f32;