1 //===-- MBlazeISelLowering.cpp - MBlaze DAG Lowering Implementation -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that MBlaze uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mblaze-lower"
16 #include "MBlazeISelLowering.h"
17 #include "MBlazeMachineFunction.h"
18 #include "MBlazeSubtarget.h"
19 #include "MBlazeTargetMachine.h"
20 #include "MBlazeTargetObjectFile.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalVariable.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
38 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
39 CCValAssign::LocInfo &LocInfo,
40 ISD::ArgFlagsTy &ArgFlags,
43 const char *MBlazeTargetLowering::getTargetNodeName(unsigned Opcode) const {
45 case MBlazeISD::JmpLink : return "MBlazeISD::JmpLink";
46 case MBlazeISD::GPRel : return "MBlazeISD::GPRel";
47 case MBlazeISD::Wrap : return "MBlazeISD::Wrap";
48 case MBlazeISD::ICmp : return "MBlazeISD::ICmp";
49 case MBlazeISD::Ret : return "MBlazeISD::Ret";
50 case MBlazeISD::Select_CC : return "MBlazeISD::Select_CC";
51 default : return NULL;
55 MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
56 : TargetLowering(TM, new MBlazeTargetObjectFile()) {
57 Subtarget = &TM.getSubtarget<MBlazeSubtarget>();
59 // MBlaze does not have i1 type, so use i32 for
60 // setcc operations results (slt, sgt, ...).
61 setBooleanContents(ZeroOrOneBooleanContent);
62 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
64 // Set up the register classes
65 addRegisterClass(MVT::i32, &MBlaze::GPRRegClass);
66 if (Subtarget->hasFPU()) {
67 addRegisterClass(MVT::f32, &MBlaze::GPRRegClass);
68 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
71 // Floating point operations which are not supported
72 setOperationAction(ISD::FREM, MVT::f32, Expand);
73 setOperationAction(ISD::FMA, MVT::f32, Expand);
74 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand);
75 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand);
76 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
77 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
78 setOperationAction(ISD::FP_ROUND, MVT::f32, Expand);
79 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
80 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
81 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
82 setOperationAction(ISD::FSIN, MVT::f32, Expand);
83 setOperationAction(ISD::FCOS, MVT::f32, Expand);
84 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
85 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
86 setOperationAction(ISD::FPOW, MVT::f32, Expand);
87 setOperationAction(ISD::FLOG, MVT::f32, Expand);
88 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
89 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
90 setOperationAction(ISD::FEXP, MVT::f32, Expand);
92 // Load extented operations for i1 types must be promoted
93 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
95 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
97 // Sign extended loads must be expanded
98 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
99 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
101 // MBlaze has no REM or DIVREM operations.
102 setOperationAction(ISD::UREM, MVT::i32, Expand);
103 setOperationAction(ISD::SREM, MVT::i32, Expand);
104 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
105 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
107 // If the processor doesn't support multiply then expand it
108 if (!Subtarget->hasMul()) {
109 setOperationAction(ISD::MUL, MVT::i32, Expand);
112 // If the processor doesn't support 64-bit multiply then expand
113 if (!Subtarget->hasMul() || !Subtarget->hasMul64()) {
114 setOperationAction(ISD::MULHS, MVT::i32, Expand);
115 setOperationAction(ISD::MULHS, MVT::i64, Expand);
116 setOperationAction(ISD::MULHU, MVT::i32, Expand);
117 setOperationAction(ISD::MULHU, MVT::i64, Expand);
120 // If the processor doesn't support division then expand
121 if (!Subtarget->hasDiv()) {
122 setOperationAction(ISD::UDIV, MVT::i32, Expand);
123 setOperationAction(ISD::SDIV, MVT::i32, Expand);
126 // Expand unsupported conversions
127 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
128 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
131 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
133 // MBlaze doesn't have MUL_LOHI
134 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
135 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
136 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
137 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
139 // Used by legalize types to correctly generate the setcc result.
140 // Without this, every float setcc comes with a AND/OR with the result,
141 // we don't want this, since the fpcmp result goes to a flag register,
142 // which is used implicitly by brcond and select operations.
143 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
144 AddPromotedToType(ISD::SELECT, MVT::i1, MVT::i32);
145 AddPromotedToType(ISD::SELECT_CC, MVT::i1, MVT::i32);
147 // MBlaze Custom Operations
148 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
149 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
150 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
151 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
153 // Variable Argument support
154 setOperationAction(ISD::VASTART, MVT::Other, Custom);
155 setOperationAction(ISD::VAEND, MVT::Other, Expand);
156 setOperationAction(ISD::VAARG, MVT::Other, Expand);
157 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
160 // Operations not directly supported by MBlaze.
161 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
162 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
163 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
164 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
166 setOperationAction(ISD::ROTL, MVT::i32, Expand);
167 setOperationAction(ISD::ROTR, MVT::i32, Expand);
168 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
169 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
170 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
171 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
172 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
173 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
174 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
175 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
176 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
178 // We don't have line number support yet.
179 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
181 // Use the default for now
182 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
183 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
185 // MBlaze doesn't have extending float->double load/store
186 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
187 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
189 setMinFunctionAlignment(2);
191 setStackPointerRegisterToSaveRestore(MBlaze::R1);
192 computeRegisterProperties();
195 EVT MBlazeTargetLowering::getSetCCResultType(LLVMContext &, EVT) const {
199 SDValue MBlazeTargetLowering::LowerOperation(SDValue Op,
200 SelectionDAG &DAG) const {
201 switch (Op.getOpcode())
203 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
204 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
205 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
206 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
207 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
208 case ISD::VASTART: return LowerVASTART(Op, DAG);
213 //===----------------------------------------------------------------------===//
214 // Lower helper functions
215 //===----------------------------------------------------------------------===//
217 MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
218 MachineBasicBlock *MBB)
220 switch (MI->getOpcode()) {
221 default: llvm_unreachable("Unexpected instr type to insert");
223 case MBlaze::ShiftRL:
224 case MBlaze::ShiftRA:
226 return EmitCustomShift(MI, MBB);
228 case MBlaze::Select_FCC:
229 case MBlaze::Select_CC:
230 return EmitCustomSelect(MI, MBB);
240 return EmitCustomAtomic(MI, MBB);
242 case MBlaze::MEMBARRIER:
243 // The Microblaze does not need memory barriers. Just delete the pseudo
244 // instruction and finish.
245 MI->eraseFromParent();
251 MBlazeTargetLowering::EmitCustomShift(MachineInstr *MI,
252 MachineBasicBlock *MBB) const {
253 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
254 DebugLoc dl = MI->getDebugLoc();
256 // To "insert" a shift left instruction, we actually have to insert a
257 // simple loop. The incoming instruction knows the destination vreg to
258 // set, the source vreg to operate over and the shift amount.
259 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
260 MachineFunction::iterator It = MBB;
264 // andi samt, samt, 31
265 // beqid samt, finish
268 // addik samt, samt, -1
273 MachineFunction *F = MBB->getParent();
274 MachineRegisterInfo &R = F->getRegInfo();
275 MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
276 MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB);
278 F->insert(It, finish);
280 // Update machine-CFG edges by transferring adding all successors and
281 // remaining instructions from the current block to the new block which
282 // will contain the Phi node for the select.
283 finish->splice(finish->begin(), MBB,
284 llvm::next(MachineBasicBlock::iterator(MI)),
286 finish->transferSuccessorsAndUpdatePHIs(MBB);
288 // Add the true and fallthrough blocks as its successors.
289 MBB->addSuccessor(loop);
290 MBB->addSuccessor(finish);
292 // Next, add the finish block as a successor of the loop block
293 loop->addSuccessor(finish);
294 loop->addSuccessor(loop);
296 unsigned IAMT = R.createVirtualRegister(&MBlaze::GPRRegClass);
297 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT)
298 .addReg(MI->getOperand(2).getReg())
301 unsigned IVAL = R.createVirtualRegister(&MBlaze::GPRRegClass);
302 BuildMI(MBB, dl, TII->get(MBlaze::ADDIK), IVAL)
303 .addReg(MI->getOperand(1).getReg())
306 BuildMI(MBB, dl, TII->get(MBlaze::BEQID))
310 unsigned DST = R.createVirtualRegister(&MBlaze::GPRRegClass);
311 unsigned NDST = R.createVirtualRegister(&MBlaze::GPRRegClass);
312 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
313 .addReg(IVAL).addMBB(MBB)
314 .addReg(NDST).addMBB(loop);
316 unsigned SAMT = R.createVirtualRegister(&MBlaze::GPRRegClass);
317 unsigned NAMT = R.createVirtualRegister(&MBlaze::GPRRegClass);
318 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
319 .addReg(IAMT).addMBB(MBB)
320 .addReg(NAMT).addMBB(loop);
322 if (MI->getOpcode() == MBlaze::ShiftL)
323 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
324 else if (MI->getOpcode() == MBlaze::ShiftRA)
325 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
326 else if (MI->getOpcode() == MBlaze::ShiftRL)
327 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
329 llvm_unreachable("Cannot lower unknown shift instruction");
331 BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
335 BuildMI(loop, dl, TII->get(MBlaze::BNEID))
339 BuildMI(*finish, finish->begin(), dl,
340 TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
341 .addReg(IVAL).addMBB(MBB)
342 .addReg(NDST).addMBB(loop);
344 // The pseudo instruction is no longer needed so remove it
345 MI->eraseFromParent();
350 MBlazeTargetLowering::EmitCustomSelect(MachineInstr *MI,
351 MachineBasicBlock *MBB) const {
352 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
353 DebugLoc dl = MI->getDebugLoc();
355 // To "insert" a SELECT_CC instruction, we actually have to insert the
356 // diamond control-flow pattern. The incoming instruction knows the
357 // destination vreg to set, the condition code register to branch on, the
358 // true/false values to select between, and a branch opcode to use.
359 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
360 MachineFunction::iterator It = MBB;
367 // bNE r1, r0, copy1MBB
368 // fallthrough --> copy0MBB
369 MachineFunction *F = MBB->getParent();
370 MachineBasicBlock *flsBB = F->CreateMachineBasicBlock(LLVM_BB);
371 MachineBasicBlock *dneBB = F->CreateMachineBasicBlock(LLVM_BB);
374 switch (MI->getOperand(4).getImm()) {
375 default: llvm_unreachable("Unknown branch condition");
376 case MBlazeCC::EQ: Opc = MBlaze::BEQID; break;
377 case MBlazeCC::NE: Opc = MBlaze::BNEID; break;
378 case MBlazeCC::GT: Opc = MBlaze::BGTID; break;
379 case MBlazeCC::LT: Opc = MBlaze::BLTID; break;
380 case MBlazeCC::GE: Opc = MBlaze::BGEID; break;
381 case MBlazeCC::LE: Opc = MBlaze::BLEID; break;
384 F->insert(It, flsBB);
385 F->insert(It, dneBB);
387 // Transfer the remainder of MBB and its successor edges to dneBB.
388 dneBB->splice(dneBB->begin(), MBB,
389 llvm::next(MachineBasicBlock::iterator(MI)),
391 dneBB->transferSuccessorsAndUpdatePHIs(MBB);
393 MBB->addSuccessor(flsBB);
394 MBB->addSuccessor(dneBB);
395 flsBB->addSuccessor(dneBB);
397 BuildMI(MBB, dl, TII->get(Opc))
398 .addReg(MI->getOperand(3).getReg())
402 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
404 //BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
405 // .addReg(MI->getOperand(1).getReg()).addMBB(flsBB)
406 // .addReg(MI->getOperand(2).getReg()).addMBB(BB);
408 BuildMI(*dneBB, dneBB->begin(), dl,
409 TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
410 .addReg(MI->getOperand(2).getReg()).addMBB(flsBB)
411 .addReg(MI->getOperand(1).getReg()).addMBB(MBB);
413 MI->eraseFromParent(); // The pseudo instruction is gone now.
418 MBlazeTargetLowering::EmitCustomAtomic(MachineInstr *MI,
419 MachineBasicBlock *MBB) const {
420 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
421 DebugLoc dl = MI->getDebugLoc();
423 // All atomic instructions on the Microblaze are implemented using the
424 // load-linked / store-conditional style atomic instruction sequences.
425 // Thus, all operations will look something like the following:
436 // To "insert" a shift left instruction, we actually have to insert a
437 // simple loop. The incoming instruction knows the destination vreg to
438 // set, the source vreg to operate over and the shift amount.
439 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
440 MachineFunction::iterator It = MBB;
444 // andi samt, samt, 31
445 // beqid samt, finish
448 // addik samt, samt, -1
453 MachineFunction *F = MBB->getParent();
454 MachineRegisterInfo &R = F->getRegInfo();
456 // Create the start and exit basic blocks for the atomic operation
457 MachineBasicBlock *start = F->CreateMachineBasicBlock(LLVM_BB);
458 MachineBasicBlock *exit = F->CreateMachineBasicBlock(LLVM_BB);
459 F->insert(It, start);
462 // Update machine-CFG edges by transferring adding all successors and
463 // remaining instructions from the current block to the new block which
464 // will contain the Phi node for the select.
465 exit->splice(exit->begin(), MBB, llvm::next(MachineBasicBlock::iterator(MI)),
467 exit->transferSuccessorsAndUpdatePHIs(MBB);
469 // Add the fallthrough block as its successors.
470 MBB->addSuccessor(start);
472 BuildMI(start, dl, TII->get(MBlaze::LWX), MI->getOperand(0).getReg())
473 .addReg(MI->getOperand(1).getReg())
476 MachineBasicBlock *final = start;
477 unsigned finalReg = 0;
479 switch (MI->getOpcode()) {
480 default: llvm_unreachable("Cannot lower unknown atomic instruction!");
483 finalReg = MI->getOperand(2).getReg();
484 start->addSuccessor(exit);
485 start->addSuccessor(start);
493 case MBlaze::LAA32: {
495 switch (MI->getOpcode()) {
496 default: llvm_unreachable("Cannot lower unknown atomic load!");
497 case MBlaze::LAA32: opcode = MBlaze::ADDIK; break;
498 case MBlaze::LAS32: opcode = MBlaze::RSUBIK; break;
499 case MBlaze::LAD32: opcode = MBlaze::AND; break;
500 case MBlaze::LAO32: opcode = MBlaze::OR; break;
501 case MBlaze::LAX32: opcode = MBlaze::XOR; break;
502 case MBlaze::LAN32: opcode = MBlaze::AND; break;
505 finalReg = R.createVirtualRegister(&MBlaze::GPRRegClass);
506 start->addSuccessor(exit);
507 start->addSuccessor(start);
509 BuildMI(start, dl, TII->get(opcode), finalReg)
510 .addReg(MI->getOperand(0).getReg())
511 .addReg(MI->getOperand(2).getReg());
513 if (MI->getOpcode() == MBlaze::LAN32) {
514 unsigned tmp = finalReg;
515 finalReg = R.createVirtualRegister(&MBlaze::GPRRegClass);
516 BuildMI(start, dl, TII->get(MBlaze::XORI), finalReg)
523 case MBlaze::CAS32: {
524 finalReg = MI->getOperand(3).getReg();
525 final = F->CreateMachineBasicBlock(LLVM_BB);
527 F->insert(It, final);
528 start->addSuccessor(exit);
529 start->addSuccessor(final);
530 final->addSuccessor(exit);
531 final->addSuccessor(start);
533 unsigned CMP = R.createVirtualRegister(&MBlaze::GPRRegClass);
534 BuildMI(start, dl, TII->get(MBlaze::CMP), CMP)
535 .addReg(MI->getOperand(0).getReg())
536 .addReg(MI->getOperand(2).getReg());
538 BuildMI(start, dl, TII->get(MBlaze::BNEID))
542 final->moveAfter(start);
543 exit->moveAfter(final);
548 unsigned CHK = R.createVirtualRegister(&MBlaze::GPRRegClass);
549 BuildMI(final, dl, TII->get(MBlaze::SWX))
551 .addReg(MI->getOperand(1).getReg())
554 BuildMI(final, dl, TII->get(MBlaze::ADDIC), CHK)
558 BuildMI(final, dl, TII->get(MBlaze::BNEID))
562 // The pseudo instruction is no longer needed so remove it
563 MI->eraseFromParent();
567 //===----------------------------------------------------------------------===//
568 // Misc Lower Operation implementation
569 //===----------------------------------------------------------------------===//
572 SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op,
573 SelectionDAG &DAG) const {
574 SDValue LHS = Op.getOperand(0);
575 SDValue RHS = Op.getOperand(1);
576 SDValue TrueVal = Op.getOperand(2);
577 SDValue FalseVal = Op.getOperand(3);
582 if (LHS.getValueType() == MVT::i32) {
583 Opc = MBlazeISD::Select_CC;
584 CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT::i32, LHS, RHS)
587 llvm_unreachable("Cannot lower select_cc with unknown type");
590 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
594 SDValue MBlazeTargetLowering::
595 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
596 // FIXME there isn't actually debug info here
598 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
599 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
601 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, GA);
604 SDValue MBlazeTargetLowering::
605 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
606 llvm_unreachable("TLS not implemented for MicroBlaze.");
609 SDValue MBlazeTargetLowering::
610 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
613 // FIXME there isn't actually debug info here
616 EVT PtrVT = Op.getValueType();
617 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
619 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 0);
620 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, JTI);
623 SDValue MBlazeTargetLowering::
624 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
626 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
627 const Constant *C = N->getConstVal();
630 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
632 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP);
635 SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op,
636 SelectionDAG &DAG) const {
637 MachineFunction &MF = DAG.getMachineFunction();
638 MBlazeFunctionInfo *FuncInfo = MF.getInfo<MBlazeFunctionInfo>();
641 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
644 // vastart just stores the address of the VarArgsFrameIndex slot into the
645 // memory location argument.
646 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
647 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
648 MachinePointerInfo(SV),
652 //===----------------------------------------------------------------------===//
653 // Calling Convention Implementation
654 //===----------------------------------------------------------------------===//
656 #include "MBlazeGenCallingConv.inc"
658 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
659 CCValAssign::LocInfo &LocInfo,
660 ISD::ArgFlagsTy &ArgFlags,
662 static const uint16_t ArgRegs[] = {
663 MBlaze::R5, MBlaze::R6, MBlaze::R7,
664 MBlaze::R8, MBlaze::R9, MBlaze::R10
667 const unsigned NumArgRegs = array_lengthof(ArgRegs);
668 unsigned Reg = State.AllocateReg(ArgRegs, NumArgRegs);
669 if (!Reg) return false;
671 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
672 State.AllocateStack(SizeInBytes, SizeInBytes);
673 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
678 //===----------------------------------------------------------------------===//
679 // Call Calling Convention Implementation
680 //===----------------------------------------------------------------------===//
682 /// LowerCall - functions arguments are copied from virtual regs to
683 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
684 /// TODO: isVarArg, isTailCall.
685 SDValue MBlazeTargetLowering::
686 LowerCall(TargetLowering::CallLoweringInfo &CLI,
687 SmallVectorImpl<SDValue> &InVals) const {
688 SelectionDAG &DAG = CLI.DAG;
690 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
691 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
692 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
693 SDValue Chain = CLI.Chain;
694 SDValue Callee = CLI.Callee;
695 bool &isTailCall = CLI.IsTailCall;
696 CallingConv::ID CallConv = CLI.CallConv;
697 bool isVarArg = CLI.IsVarArg;
699 // MBlaze does not yet support tail call optimization
702 // The MBlaze requires stack slots for arguments passed to var arg
703 // functions even if they are passed in registers.
704 bool needsRegArgSlots = isVarArg;
706 MachineFunction &MF = DAG.getMachineFunction();
707 MachineFrameInfo *MFI = MF.getFrameInfo();
708 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
710 // Analyze operands of the call, assigning locations to each operand.
711 SmallVector<CCValAssign, 16> ArgLocs;
712 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
713 getTargetMachine(), ArgLocs, *DAG.getContext());
714 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze);
716 // Get a count of how many bytes are to be pushed on the stack.
717 unsigned NumBytes = CCInfo.getNextStackOffset();
719 // Variable argument function calls require a minimum of 24-bytes of stack
720 if (isVarArg && NumBytes < 24) NumBytes = 24;
722 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
725 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
726 SmallVector<SDValue, 8> MemOpChains;
728 // Walk the register/memloc assignments, inserting copies/loads.
729 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
730 CCValAssign &VA = ArgLocs[i];
731 MVT RegVT = VA.getLocVT();
732 SDValue Arg = OutVals[i];
734 // Promote the value if needed.
735 switch (VA.getLocInfo()) {
736 default: llvm_unreachable("Unknown loc info!");
737 case CCValAssign::Full: break;
738 case CCValAssign::SExt:
739 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
741 case CCValAssign::ZExt:
742 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
744 case CCValAssign::AExt:
745 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
749 // Arguments that can be passed on register must be kept at
752 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
754 // Register can't get to this point...
755 assert(VA.isMemLoc());
757 // Since we are alread passing values on the stack we don't
758 // need to worry about creating additional slots for the
759 // values passed via registers.
760 needsRegArgSlots = false;
762 // Create the frame index object for this incoming parameter
763 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
764 unsigned StackLoc = VA.getLocMemOffset() + 4;
765 int FI = MFI->CreateFixedObject(ArgSize, StackLoc, true);
767 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
769 // emit ISD::STORE whichs stores the
770 // parameter value to a stack Location
771 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
772 MachinePointerInfo(),
777 // If we need to reserve stack space for the arguments passed via registers
778 // then create a fixed stack object at the beginning of the stack.
779 if (needsRegArgSlots && TFI.hasReservedCallFrame(MF))
780 MFI->CreateFixedObject(28,0,true);
782 // Transform all store nodes into one single node because all store
783 // nodes are independent of each other.
784 if (!MemOpChains.empty())
785 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
786 &MemOpChains[0], MemOpChains.size());
788 // Build a sequence of copy-to-reg nodes chained together with token
789 // chain and flag operands which copy the outgoing args into registers.
790 // The InFlag in necessary since all emitted instructions must be
793 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
794 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
795 RegsToPass[i].second, InFlag);
796 InFlag = Chain.getValue(1);
799 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
800 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
801 // node so that legalize doesn't hack it.
802 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
803 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
804 getPointerTy(), 0, 0);
805 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
806 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
809 // MBlazeJmpLink = #chain, #target_address, #opt_in_flags...
810 // = Chain, Callee, Reg#1, Reg#2, ...
812 // Returns a chain & a flag for retval copy to use.
813 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
814 SmallVector<SDValue, 8> Ops;
815 Ops.push_back(Chain);
816 Ops.push_back(Callee);
818 // Add argument registers to the end of the list so that they are
819 // known live into the call.
820 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
821 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
822 RegsToPass[i].second.getValueType()));
825 if (InFlag.getNode())
826 Ops.push_back(InFlag);
828 Chain = DAG.getNode(MBlazeISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
829 InFlag = Chain.getValue(1);
831 // Create the CALLSEQ_END node.
832 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
833 DAG.getIntPtrConstant(0, true), InFlag, dl);
835 InFlag = Chain.getValue(1);
837 // Handle result values, copying them out of physregs into vregs that we
839 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
840 Ins, dl, DAG, InVals);
843 /// LowerCallResult - Lower the result values of a call into the
844 /// appropriate copies out of appropriate physical registers.
845 SDValue MBlazeTargetLowering::
846 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv,
847 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins,
848 SDLoc dl, SelectionDAG &DAG,
849 SmallVectorImpl<SDValue> &InVals) const {
850 // Assign locations to each value returned by this call.
851 SmallVector<CCValAssign, 16> RVLocs;
852 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
853 getTargetMachine(), RVLocs, *DAG.getContext());
855 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze);
857 // Copy all of the result registers out of their specified physreg.
858 for (unsigned i = 0; i != RVLocs.size(); ++i) {
859 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
860 RVLocs[i].getValVT(), InFlag).getValue(1);
861 InFlag = Chain.getValue(2);
862 InVals.push_back(Chain.getValue(0));
868 //===----------------------------------------------------------------------===//
869 // Formal Arguments Calling Convention Implementation
870 //===----------------------------------------------------------------------===//
872 /// LowerFormalArguments - transform physical registers into
873 /// virtual registers and generate load operations for
874 /// arguments places on the stack.
875 SDValue MBlazeTargetLowering::
876 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
877 const SmallVectorImpl<ISD::InputArg> &Ins,
878 SDLoc dl, SelectionDAG &DAG,
879 SmallVectorImpl<SDValue> &InVals) const {
880 MachineFunction &MF = DAG.getMachineFunction();
881 MachineFrameInfo *MFI = MF.getFrameInfo();
882 MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
884 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
885 MBlazeFI->setVarArgsFrameIndex(0);
887 // Used with vargs to acumulate store chains.
888 std::vector<SDValue> OutChains;
890 // Keep track of the last register used for arguments
891 unsigned ArgRegEnd = 0;
893 // Assign locations to all of the incoming arguments.
894 SmallVector<CCValAssign, 16> ArgLocs;
895 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
896 getTargetMachine(), ArgLocs, *DAG.getContext());
898 CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze);
901 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
902 CCValAssign &VA = ArgLocs[i];
904 // Arguments stored on registers
906 MVT RegVT = VA.getLocVT();
907 ArgRegEnd = VA.getLocReg();
908 const TargetRegisterClass *RC;
910 if (RegVT == MVT::i32)
911 RC = &MBlaze::GPRRegClass;
912 else if (RegVT == MVT::f32)
913 RC = &MBlaze::GPRRegClass;
915 llvm_unreachable("RegVT not supported by LowerFormalArguments");
917 // Transform the arguments stored on
918 // physical registers into virtual ones
919 unsigned Reg = MF.addLiveIn(ArgRegEnd, RC);
920 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
922 // If this is an 8 or 16-bit value, it has been passed promoted
923 // to 32 bits. Insert an assert[sz]ext to capture this, then
924 // truncate to the right size. If if is a floating point value
925 // then convert to the correct type.
926 if (VA.getLocInfo() != CCValAssign::Full) {
928 if (VA.getLocInfo() == CCValAssign::SExt)
929 Opcode = ISD::AssertSext;
930 else if (VA.getLocInfo() == CCValAssign::ZExt)
931 Opcode = ISD::AssertZext;
933 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
934 DAG.getValueType(VA.getValVT()));
935 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
938 InVals.push_back(ArgValue);
939 } else { // VA.isRegLoc()
941 assert(VA.isMemLoc());
943 // The last argument is not a register
946 // The stack pointer offset is relative to the caller stack frame.
947 // Since the real stack size is unknown here, a negative SPOffset
948 // is used so there's a way to adjust these offsets when the stack
949 // size get known (on EliminateFrameIndex). A dummy SPOffset is
950 // used instead of a direct negative address (which is recorded to
951 // be used on emitPrologue) to avoid mis-calc of the first stack
952 // offset on PEI::calculateFrameObjectOffsets.
953 // Arguments are always 32-bit.
954 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
955 unsigned StackLoc = VA.getLocMemOffset() + 4;
956 int FI = MFI->CreateFixedObject(ArgSize, 0, true);
957 MBlazeFI->recordLoadArgsFI(FI, -StackLoc);
958 MBlazeFI->recordLiveIn(FI);
960 // Create load nodes to retrieve arguments from the stack
961 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
962 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
963 MachinePointerInfo::getFixedStack(FI),
964 false, false, false, 0));
968 // To meet ABI, when VARARGS are passed on registers, the registers
969 // must have their values written to the caller stack frame. If the last
970 // argument was placed in the stack, there's no need to save any register.
971 if ((isVarArg) && ArgRegEnd) {
972 if (StackPtr.getNode() == 0)
973 StackPtr = DAG.getRegister(StackReg, getPointerTy());
975 // The last register argument that must be saved is MBlaze::R10
976 const TargetRegisterClass *RC = &MBlaze::GPRRegClass;
978 unsigned Begin = getMBlazeRegisterNumbering(MBlaze::R5);
979 unsigned Start = getMBlazeRegisterNumbering(ArgRegEnd+1);
980 unsigned End = getMBlazeRegisterNumbering(MBlaze::R10);
981 unsigned StackLoc = Start - Begin + 1;
983 for (; Start <= End; ++Start, ++StackLoc) {
984 unsigned Reg = getMBlazeRegisterFromNumbering(Start);
985 unsigned LiveReg = MF.addLiveIn(Reg, RC);
986 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32);
988 int FI = MFI->CreateFixedObject(4, 0, true);
989 MBlazeFI->recordStoreVarArgsFI(FI, -(StackLoc*4));
990 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
991 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
992 MachinePointerInfo(),
995 // Record the frame index of the first variable argument
996 // which is a value necessary to VASTART.
997 if (!MBlazeFI->getVarArgsFrameIndex())
998 MBlazeFI->setVarArgsFrameIndex(FI);
1002 // All stores are grouped in one node to allow the matching between
1003 // the size of Ins and InVals. This only happens when on varg functions
1004 if (!OutChains.empty()) {
1005 OutChains.push_back(Chain);
1006 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1007 &OutChains[0], OutChains.size());
1013 //===----------------------------------------------------------------------===//
1014 // Return Value Calling Convention Implementation
1015 //===----------------------------------------------------------------------===//
1017 SDValue MBlazeTargetLowering::
1018 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1019 const SmallVectorImpl<ISD::OutputArg> &Outs,
1020 const SmallVectorImpl<SDValue> &OutVals,
1021 SDLoc dl, SelectionDAG &DAG) const {
1022 // CCValAssign - represent the assignment of
1023 // the return value to a location
1024 SmallVector<CCValAssign, 16> RVLocs;
1026 // CCState - Info about the registers and stack slot.
1027 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1028 getTargetMachine(), RVLocs, *DAG.getContext());
1030 // Analize return values.
1031 CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze);
1034 SmallVector<SDValue, 4> RetOps(1, Chain);
1036 // If this function is using the interrupt_handler calling convention
1037 // then use "rtid r14, 0" otherwise use "rtsd r15, 8"
1038 unsigned Ret = (CallConv == CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet
1040 unsigned Reg = (CallConv == CallingConv::MBLAZE_INTR) ? MBlaze::R14
1042 RetOps.push_back(DAG.getRegister(Reg, MVT::i32));
1045 // Copy the result values into the output registers.
1046 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1047 CCValAssign &VA = RVLocs[i];
1048 assert(VA.isRegLoc() && "Can only return in registers!");
1050 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1053 // guarantee that all emitted copies are
1054 // stuck together, avoiding something bad
1055 Flag = Chain.getValue(1);
1056 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1059 RetOps[0] = Chain; // Update chain.
1061 // Add the flag if we have it.
1063 RetOps.push_back(Flag);
1065 return DAG.getNode(Ret, dl, MVT::Other, &RetOps[0], RetOps.size());
1068 //===----------------------------------------------------------------------===//
1069 // MBlaze Inline Assembly Support
1070 //===----------------------------------------------------------------------===//
1072 /// getConstraintType - Given a constraint letter, return the type of
1073 /// constraint it is for this target.
1074 MBlazeTargetLowering::ConstraintType MBlazeTargetLowering::
1075 getConstraintType(const std::string &Constraint) const
1077 // MBlaze specific constrainy
1079 // 'd' : An address register. Equivalent to r.
1080 // 'y' : Equivalent to r; retained for
1081 // backwards compatibility.
1082 // 'f' : Floating Point registers.
1083 if (Constraint.size() == 1) {
1084 switch (Constraint[0]) {
1089 return C_RegisterClass;
1092 return TargetLowering::getConstraintType(Constraint);
1095 /// Examine constraint type and operand type and determine a weight value.
1096 /// This object must already have been set up with the operand type
1097 /// and the current alternative constraint selected.
1098 TargetLowering::ConstraintWeight
1099 MBlazeTargetLowering::getSingleConstraintMatchWeight(
1100 AsmOperandInfo &info, const char *constraint) const {
1101 ConstraintWeight weight = CW_Invalid;
1102 Value *CallOperandVal = info.CallOperandVal;
1103 // If we don't have a value, we can't do a match,
1104 // but allow it at the lowest weight.
1105 if (CallOperandVal == NULL)
1107 Type *type = CallOperandVal->getType();
1108 // Look at the constraint type.
1109 switch (*constraint) {
1111 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1115 if (type->isIntegerTy())
1116 weight = CW_Register;
1119 if (type->isFloatTy())
1120 weight = CW_Register;
1126 /// Given a register class constraint, like 'r', if this corresponds directly
1127 /// to an LLVM register class, return a register of 0 and the register class
1129 std::pair<unsigned, const TargetRegisterClass*> MBlazeTargetLowering::
1130 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
1131 if (Constraint.size() == 1) {
1132 switch (Constraint[0]) {
1134 return std::make_pair(0U, &MBlaze::GPRRegClass);
1135 // TODO: These can't possibly be right, but match what was in
1136 // getRegClassForInlineAsmConstraint.
1141 return std::make_pair(0U, &MBlaze::GPRRegClass);
1144 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1147 bool MBlazeTargetLowering::
1148 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1149 // The MBlaze target isn't yet aware of offsets.
1153 bool MBlazeTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1154 return VT != MVT::f32;