1 //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on IA64.
13 //===----------------------------------------------------------------------===//
16 #include "IA64RegisterInfo.h"
17 #include "IA64InstrBuilder.h"
18 #include "IA64MachineFunctionInfo.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/Target/TargetFrameInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/STLExtras.h"
35 IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
36 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
39 void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MI,
41 unsigned SrcReg, bool isKill,
43 const TargetRegisterClass *RC) const{
45 if (RC == IA64::FPRegisterClass) {
46 BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
47 .addReg(SrcReg, false, false, isKill);
48 } else if (RC == IA64::GRRegisterClass) {
49 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx)
50 .addReg(SrcReg, false, false, isKill);
51 } else if (RC == IA64::PRRegisterClass) {
52 /* we use IA64::r2 as a temporary register for doing this hackery. */
54 BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
55 // then conditionally add 1:
56 BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
57 .addImm(1).addReg(SrcReg, false, false, isKill);
58 // and then store it to the stack
59 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
61 "sorry, I don't know how to store this sort of reg in the stack\n");
64 void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
66 SmallVectorImpl<MachineOperand> &Addr,
67 const TargetRegisterClass *RC,
68 SmallVectorImpl<MachineInstr*> &NewMIs) const {
70 if (RC == IA64::FPRegisterClass) {
72 } else if (RC == IA64::GRRegisterClass) {
74 } else if (RC == IA64::PRRegisterClass) {
78 "sorry, I don't know how to store this sort of reg\n");
81 MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
82 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
83 MachineOperand &MO = Addr[i];
85 MIB.addReg(MO.getReg());
86 else if (MO.isImmediate())
87 MIB.addImm(MO.getImm());
89 MIB.addFrameIndex(MO.getIndex());
91 MIB.addReg(SrcReg, false, false, isKill);
92 NewMIs.push_back(MIB);
97 void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MI,
99 unsigned DestReg, int FrameIdx,
100 const TargetRegisterClass *RC)const{
102 if (RC == IA64::FPRegisterClass) {
103 BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
104 } else if (RC == IA64::GRRegisterClass) {
105 BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
106 } else if (RC == IA64::PRRegisterClass) {
107 // first we load a byte from the stack into r2, our 'predicate hackery'
109 BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
110 // then we compare it to zero. If it _is_ zero, compare-not-equal to
111 // r0 gives us 0, which is what we want, so that's nice.
112 BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
114 "sorry, I don't know how to load this sort of reg from the stack\n");
117 void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
118 SmallVectorImpl<MachineOperand> &Addr,
119 const TargetRegisterClass *RC,
120 SmallVectorImpl<MachineInstr*> &NewMIs) const {
122 if (RC == IA64::FPRegisterClass) {
124 } else if (RC == IA64::GRRegisterClass) {
126 } else if (RC == IA64::PRRegisterClass) {
130 "sorry, I don't know how to store this sort of reg\n");
133 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
134 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
135 MachineOperand &MO = Addr[i];
137 MIB.addReg(MO.getReg());
138 else if (MO.isImmediate())
139 MIB.addImm(MO.getImm());
141 MIB.addFrameIndex(MO.getIndex());
143 NewMIs.push_back(MIB);
147 void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
148 MachineBasicBlock::iterator MI,
149 unsigned DestReg, unsigned SrcReg,
150 const TargetRegisterClass *DestRC,
151 const TargetRegisterClass *SrcRC) const {
152 if (DestRC != SrcRC) {
153 cerr << "Not yet supported!";
157 if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
158 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
159 BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg)
160 .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
161 else // otherwise, MOV works (for both gen. regs and FP regs)
162 BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
165 void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
166 MachineBasicBlock::iterator I,
168 const MachineInstr *Orig) const {
169 MachineInstr *MI = Orig->clone();
170 MI->getOperand(0).setReg(DestReg);
174 const unsigned* IA64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
176 static const unsigned CalleeSavedRegs[] = {
179 return CalleeSavedRegs;
182 const TargetRegisterClass* const*
183 IA64RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
184 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
187 return CalleeSavedRegClasses;
190 BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
191 BitVector Reserved(getNumRegs());
192 Reserved.set(IA64::r0);
193 Reserved.set(IA64::r1);
194 Reserved.set(IA64::r2);
195 Reserved.set(IA64::r5);
196 Reserved.set(IA64::r12);
197 Reserved.set(IA64::r13);
198 Reserved.set(IA64::r22);
199 Reserved.set(IA64::rp);
203 //===----------------------------------------------------------------------===//
204 // Stack Frame Processing methods
205 //===----------------------------------------------------------------------===//
207 // hasFP - Return true if the specified function should have a dedicated frame
208 // pointer register. This is true if the function has variable sized allocas or
209 // if frame pointer elimination is disabled.
211 bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
212 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
215 void IA64RegisterInfo::
216 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
217 MachineBasicBlock::iterator I) const {
219 // If we have a frame pointer, turn the adjcallstackup instruction into a
220 // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
222 MachineInstr *Old = I;
223 unsigned Amount = Old->getOperand(0).getImm();
225 // We need to keep the stack aligned properly. To do this, we round the
226 // amount of space needed for the outgoing arguments up to the next
227 // alignment boundary.
228 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
229 Amount = (Amount+Align-1)/Align*Align;
232 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
233 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
236 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
237 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
241 // Replace the pseudo instruction with a new instruction...
249 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
250 int SPAdj, RegScavenger *RS)const{
251 assert(SPAdj == 0 && "Unexpected");
254 MachineInstr &MI = *II;
255 MachineBasicBlock &MBB = *MI.getParent();
256 MachineFunction &MF = *MBB.getParent();
260 while (!MI.getOperand(i).isFrameIndex()) {
262 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
265 int FrameIndex = MI.getOperand(i).getIndex();
267 // choose a base register: ( hasFP? framepointer : stack pointer )
268 unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
269 // Add the base register
270 MI.getOperand(i).ChangeToRegister(BaseRegister, false);
272 // Now add the frame object offset to the offset from r1.
273 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
275 // If we're not using a Frame Pointer that has been set to the value of the
276 // SP before having the stack size subtracted from it, then add the stack size
277 // to Offset to get the correct offset.
278 Offset += MF.getFrameInfo()->getStackSize();
280 // XXX: we use 'r22' as another hack+slash temporary register here :(
281 if (Offset <= 8191 && Offset >= -8192) { // smallish offset
283 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
285 MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22)
286 .addReg(BaseRegister).addImm(Offset);
290 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
292 nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
294 nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
301 void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
302 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
303 MachineBasicBlock::iterator MBBI = MBB.begin();
304 MachineFrameInfo *MFI = MF.getFrameInfo();
308 // first, we handle the 'alloc' instruction, that should be right up the
309 // top of any function
310 static const unsigned RegsInOrder[96] = { // there are 96 GPRs the
312 IA64::r32, IA64::r33, IA64::r34, IA64::r35,
313 IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41,
314 IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47,
315 IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53,
316 IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59,
317 IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65,
318 IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71,
319 IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77,
320 IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83,
321 IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89,
322 IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95,
323 IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101,
324 IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107,
325 IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113,
326 IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119,
327 IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125,
328 IA64::r126, IA64::r127 };
330 unsigned numStackedGPRsUsed=0;
331 for(int i=0; i<96; i++) {
332 if(MF.isPhysRegUsed(RegsInOrder[i]))
333 numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
336 unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
338 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
339 // a pseudo_alloc in the MBB)
340 unsigned dstRegOfPseudoAlloc;
341 for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
342 assert(MBBI != MBB.end());
343 if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) {
344 dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg();
349 MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \
350 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
351 MBB.insert(MBBI, MI);
353 // Get the number of bytes to allocate from the FrameInfo
354 unsigned NumBytes = MFI->getStackSize();
357 NumBytes += 8; // reserve space for the old FP
359 // Do we need to allocate space on the stack?
363 // Add 16 bytes at the bottom of the stack (scratch area)
364 // and round the size to a multiple of the alignment.
365 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
366 unsigned Size = 16 + (FP ? 8 : 0);
367 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
369 // Update frame info to pretend that this is part of the stack...
370 MFI->setStackSize(NumBytes);
372 // adjust stack pointer: r12 -= numbytes
373 if (NumBytes <= 8191) {
374 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
376 MBB.insert(MBBI, MI);
377 } else { // we use r22 as a scratch register here
378 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
379 // FIXME: MOVLSI32 expects a _u_32imm
380 MBB.insert(MBBI, MI); // first load the decrement into r22
381 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
382 MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
385 // now if we need to, save the old FP and set the new
387 MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
388 MBB.insert(MBBI, MI);
389 // this must be the last instr in the prolog ? (XXX: why??)
390 MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
391 MBB.insert(MBBI, MI);
396 void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
397 MachineBasicBlock &MBB) const {
398 const MachineFrameInfo *MFI = MF.getFrameInfo();
399 MachineBasicBlock::iterator MBBI = prior(MBB.end());
401 assert(MBBI->getOpcode() == IA64::RET &&
402 "Can only insert epilog into returning blocks");
406 // Get the number of bytes allocated from the FrameInfo...
407 unsigned NumBytes = MFI->getStackSize();
409 //now if we need to, restore the old FP
412 //copy the FP into the SP (discards allocas)
413 MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
414 MBB.insert(MBBI, MI);
416 MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
417 MBB.insert(MBBI, MI);
422 if (NumBytes <= 8191) {
423 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
425 MBB.insert(MBBI, MI);
427 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes);
428 MBB.insert(MBBI, MI);
429 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
431 MBB.insert(MBBI, MI);
437 unsigned IA64RegisterInfo::getRARegister() const {
438 assert(0 && "What is the return address register");
442 unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
443 return hasFP(MF) ? IA64::r5 : IA64::r12;
446 unsigned IA64RegisterInfo::getEHExceptionRegister() const {
447 assert(0 && "What is the exception register");
451 unsigned IA64RegisterInfo::getEHHandlerRegister() const {
452 assert(0 && "What is the exception handler register");
456 int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
457 assert(0 && "What is the dwarf register number");
461 #include "IA64GenRegisterInfo.inc"