1 //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "IA64RegisterInfo.h"
18 #include "IA64InstrBuilder.h"
19 #include "IA64MachineFunctionInfo.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Type.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/STLExtras.h"
36 IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
37 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
40 void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
41 MachineBasicBlock::iterator I,
43 const MachineInstr *Orig) const {
44 MachineInstr *MI = Orig->clone();
45 MI->getOperand(0).setReg(DestReg);
49 const unsigned* IA64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
51 static const unsigned CalleeSavedRegs[] = {
54 return CalleeSavedRegs;
57 const TargetRegisterClass* const*
58 IA64RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
59 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
62 return CalleeSavedRegClasses;
65 BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
66 BitVector Reserved(getNumRegs());
67 Reserved.set(IA64::r0);
68 Reserved.set(IA64::r1);
69 Reserved.set(IA64::r2);
70 Reserved.set(IA64::r5);
71 Reserved.set(IA64::r12);
72 Reserved.set(IA64::r13);
73 Reserved.set(IA64::r22);
74 Reserved.set(IA64::rp);
78 //===----------------------------------------------------------------------===//
79 // Stack Frame Processing methods
80 //===----------------------------------------------------------------------===//
82 // hasFP - Return true if the specified function should have a dedicated frame
83 // pointer register. This is true if the function has variable sized allocas or
84 // if frame pointer elimination is disabled.
86 bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
87 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
90 void IA64RegisterInfo::
91 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator I) const {
94 // If we have a frame pointer, turn the adjcallstackup instruction into a
95 // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
97 MachineInstr *Old = I;
98 unsigned Amount = Old->getOperand(0).getImm();
100 // We need to keep the stack aligned properly. To do this, we round the
101 // amount of space needed for the outgoing arguments up to the next
102 // alignment boundary.
103 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
104 Amount = (Amount+Align-1)/Align*Align;
107 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
108 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
111 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
112 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
116 // Replace the pseudo instruction with a new instruction...
124 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
125 int SPAdj, RegScavenger *RS)const{
126 assert(SPAdj == 0 && "Unexpected");
129 MachineInstr &MI = *II;
130 MachineBasicBlock &MBB = *MI.getParent();
131 MachineFunction &MF = *MBB.getParent();
135 while (!MI.getOperand(i).isFrameIndex()) {
137 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
140 int FrameIndex = MI.getOperand(i).getIndex();
142 // choose a base register: ( hasFP? framepointer : stack pointer )
143 unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
144 // Add the base register
145 MI.getOperand(i).ChangeToRegister(BaseRegister, false);
147 // Now add the frame object offset to the offset from r1.
148 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
150 // If we're not using a Frame Pointer that has been set to the value of the
151 // SP before having the stack size subtracted from it, then add the stack size
152 // to Offset to get the correct offset.
153 Offset += MF.getFrameInfo()->getStackSize();
155 // XXX: we use 'r22' as another hack+slash temporary register here :(
156 if (Offset <= 8191 && Offset >= -8192) { // smallish offset
158 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
160 MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22)
161 .addReg(BaseRegister).addImm(Offset);
165 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
167 nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
169 nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
176 void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
177 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
178 MachineBasicBlock::iterator MBBI = MBB.begin();
179 MachineFrameInfo *MFI = MF.getFrameInfo();
183 // first, we handle the 'alloc' instruction, that should be right up the
184 // top of any function
185 static const unsigned RegsInOrder[96] = { // there are 96 GPRs the
187 IA64::r32, IA64::r33, IA64::r34, IA64::r35,
188 IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41,
189 IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47,
190 IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53,
191 IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59,
192 IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65,
193 IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71,
194 IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77,
195 IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83,
196 IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89,
197 IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95,
198 IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101,
199 IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107,
200 IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113,
201 IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119,
202 IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125,
203 IA64::r126, IA64::r127 };
205 unsigned numStackedGPRsUsed=0;
206 for (int i=0; i != 96; i++) {
207 if (MF.getRegInfo().isPhysRegUsed(RegsInOrder[i]))
208 numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
211 unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
213 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
214 // a pseudo_alloc in the MBB)
215 unsigned dstRegOfPseudoAlloc;
216 for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
217 assert(MBBI != MBB.end());
218 if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) {
219 dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg();
224 MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \
225 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
226 MBB.insert(MBBI, MI);
228 // Get the number of bytes to allocate from the FrameInfo
229 unsigned NumBytes = MFI->getStackSize();
232 NumBytes += 8; // reserve space for the old FP
234 // Do we need to allocate space on the stack?
238 // Add 16 bytes at the bottom of the stack (scratch area)
239 // and round the size to a multiple of the alignment.
240 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
241 unsigned Size = 16 + (FP ? 8 : 0);
242 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
244 // Update frame info to pretend that this is part of the stack...
245 MFI->setStackSize(NumBytes);
247 // adjust stack pointer: r12 -= numbytes
248 if (NumBytes <= 8191) {
249 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
251 MBB.insert(MBBI, MI);
252 } else { // we use r22 as a scratch register here
253 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
254 // FIXME: MOVLSI32 expects a _u_32imm
255 MBB.insert(MBBI, MI); // first load the decrement into r22
256 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
257 MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
260 // now if we need to, save the old FP and set the new
262 MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
263 MBB.insert(MBBI, MI);
264 // this must be the last instr in the prolog ? (XXX: why??)
265 MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
266 MBB.insert(MBBI, MI);
271 void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
272 MachineBasicBlock &MBB) const {
273 const MachineFrameInfo *MFI = MF.getFrameInfo();
274 MachineBasicBlock::iterator MBBI = prior(MBB.end());
276 assert(MBBI->getOpcode() == IA64::RET &&
277 "Can only insert epilog into returning blocks");
281 // Get the number of bytes allocated from the FrameInfo...
282 unsigned NumBytes = MFI->getStackSize();
284 //now if we need to, restore the old FP
287 //copy the FP into the SP (discards allocas)
288 MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
289 MBB.insert(MBBI, MI);
291 MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
292 MBB.insert(MBBI, MI);
297 if (NumBytes <= 8191) {
298 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
300 MBB.insert(MBBI, MI);
302 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes);
303 MBB.insert(MBBI, MI);
304 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
306 MBB.insert(MBBI, MI);
312 unsigned IA64RegisterInfo::getRARegister() const {
313 assert(0 && "What is the return address register");
317 unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
318 return hasFP(MF) ? IA64::r5 : IA64::r12;
321 unsigned IA64RegisterInfo::getEHExceptionRegister() const {
322 assert(0 && "What is the exception register");
326 unsigned IA64RegisterInfo::getEHHandlerRegister() const {
327 assert(0 && "What is the exception handler register");
331 int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
332 assert(0 && "What is the dwarf register number");
336 #include "IA64GenRegisterInfo.inc"