1 //===- IA64InstrInfo.td - Describe the IA64 Instruction Set -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the IA64 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 include "IA64InstrFormats.td"
18 //===----------------------------------------------------------------------===//
19 // IA-64 specific DAG Nodes.
22 def IA64getfd : SDNode<"IA64ISD::GETFD", SDTFPToIntOp, []>;
24 def SDT_IA64RetFlag : SDTypeProfile<0, 0, []>;
25 def retflag : SDNode<"IA64ISD::RET_FLAG", SDT_IA64RetFlag,
26 [SDNPHasChain, SDNPOptInFlag]>;
30 def u2imm : Operand<i8>;
31 def u6imm : Operand<i8>;
32 def s8imm : Operand<i8> {
33 let PrintMethod = "printS8ImmOperand";
35 def s14imm : Operand<i64> {
36 let PrintMethod = "printS14ImmOperand";
38 def s22imm : Operand<i64> {
39 let PrintMethod = "printS22ImmOperand";
41 def u64imm : Operand<i64> {
42 let PrintMethod = "printU64ImmOperand";
44 def s64imm : Operand<i64> {
45 let PrintMethod = "printS64ImmOperand";
48 let PrintMethod = "printGlobalOperand" in
49 def globaladdress : Operand<i64>;
51 // the asmprinter needs to know about calls
52 let PrintMethod = "printCallOperand" in
53 def calltarget : Operand<i64>;
55 /* new daggy action!!! */
57 def is32ones : PatLeaf<(i64 imm), [{
58 // is32ones predicate - True if the immediate is 0x00000000FFFFFFFF
59 // Used to create ZXT4s appropriately
60 uint64_t v = (uint64_t)N->getValue();
61 return (v == 0x00000000FFFFFFFFLL);
64 // isMIXable predicates - True if the immediate is
65 // 0xFF00FF00FF00FF00, 0x00FF00FF00FF00FF
66 // etc, through 0x00000000FFFFFFFF
67 // Used to test for the suitability of mix*
68 def isMIX1Lable: PatLeaf<(i64 imm), [{
69 return((uint64_t)N->getValue()==0xFF00FF00FF00FF00LL);
71 def isMIX1Rable: PatLeaf<(i64 imm), [{
72 return((uint64_t)N->getValue()==0x00FF00FF00FF00FFLL);
74 def isMIX2Lable: PatLeaf<(i64 imm), [{
75 return((uint64_t)N->getValue()==0xFFFF0000FFFF0000LL);
77 def isMIX2Rable: PatLeaf<(i64 imm), [{
78 return((uint64_t)N->getValue()==0x0000FFFF0000FFFFLL);
80 def isMIX4Lable: PatLeaf<(i64 imm), [{
81 return((uint64_t)N->getValue()==0xFFFFFFFF00000000LL);
83 def isMIX4Rable: PatLeaf<(i64 imm), [{
84 return((uint64_t)N->getValue()==0x00000000FFFFFFFFLL);
87 def isSHLADDimm: PatLeaf<(i64 imm), [{
88 // isSHLADDimm predicate - True if the immediate is exactly 1, 2, 3 or 4
90 // Used to create shladd instructions appropriately
91 int64_t v = (int64_t)N->getValue();
92 return (v >= 1 && v <= 4);
95 def immSExt14 : PatLeaf<(i64 imm), [{
96 // immSExt14 predicate - True if the immediate fits in a 14-bit sign extended
97 // field. Used by instructions like 'adds'.
98 int64_t v = (int64_t)N->getValue();
99 return (v <= 8191 && v >= -8192);
102 def imm64 : PatLeaf<(i64 imm), [{
103 // imm64 predicate - True if the immediate fits in a 64-bit
104 // field - i.e., true. used to keep movl happy
108 def ADD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
109 "add $dst = $src1, $src2",
110 [(set GR:$dst, (add GR:$src1, GR:$src2))]>;
112 def ADD1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
113 "add $dst = $src1, $src2, 1",
114 [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>;
116 def ADDS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
117 "adds $dst = $imm, $src1",
118 [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>;
120 def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
122 [(set GR:$dst, imm64:$imm)]>;
124 def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, globaladdress:$imm),
125 "addl $dst = $imm, $src1",
129 def ADDL_EA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, calltarget:$imm),
130 "addl $dst = $imm, $src1",
133 def SUB : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
134 "sub $dst = $src1, $src2",
135 [(set GR:$dst, (sub GR:$src1, GR:$src2))]>;
137 def SUB1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
138 "sub $dst = $src1, $src2, 1",
139 [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>;
141 let isTwoAddress = 1 in {
142 def TPCADDIMM22 : AForm<0x03, 0x0b,
143 (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
144 "($qp) add $dst = $imm, $dst">;
145 def TPCADDS : AForm_DAG<0x03, 0x0b,
146 (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp),
147 "($qp) adds $dst = $imm, $dst",
149 def TPCMPIMM8NE : AForm<0x03, 0x0b,
150 (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
151 "($qp) cmp.ne $dst , p0 = $imm, $src2">;
154 // zero extend a bool (predicate reg) into an integer reg
155 def ZXTb : Pat<(zext PR:$src),
156 (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src)>;
158 // normal sign/zero-extends
159 def SXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src",
160 [(set GR:$dst, (sext_inreg GR:$src, i8))]>;
161 def ZXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src",
162 [(set GR:$dst, (and GR:$src, 255))]>;
163 def SXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src",
164 [(set GR:$dst, (sext_inreg GR:$src, i16))]>;
165 def ZXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src",
166 [(set GR:$dst, (and GR:$src, 65535))]>;
167 def SXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src",
168 [(set GR:$dst, (sext_inreg GR:$src, i32))]>;
169 def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src",
170 [(set GR:$dst, (and GR:$src, is32ones))]>;
172 // fixme: shrs vs shru?
173 def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
174 "mix1.l $dst = $src1, $src2",
175 [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
176 (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>;
178 def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
179 "mix2.l $dst = $src1, $src2",
180 [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
181 (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>;
183 def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
184 "mix4.l $dst = $src1, $src2",
185 [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
186 (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>;
188 def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
189 "mix1.r $dst = $src1, $src2",
190 [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable),
191 (and GR:$src2, isMIX1Rable)))]>;
193 def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
194 "mix2.r $dst = $src1, $src2",
195 [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable),
196 (and GR:$src2, isMIX2Rable)))]>;
198 def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
199 "mix4.r $dst = $src1, $src2",
200 [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable),
201 (and GR:$src2, isMIX4Rable)))]>;
203 def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src),
204 "getf.sig $dst = $src",
207 def SETFSIGD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, GR:$src),
208 "setf.sig $dst = $src",
211 def XMALD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
212 "xma.l $dst = $src1, $src2, $src3",
214 def XMAHD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
215 "xma.h $dst = $src1, $src2, $src3",
217 def XMAHUD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
218 "xma.hu $dst = $src1, $src2, $src3",
221 // pseudocode for integer multiplication
222 def : Pat<(mul GR:$src1, GR:$src2),
223 (GETFSIGD (XMALD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
224 def : Pat<(mulhs GR:$src1, GR:$src2),
225 (GETFSIGD (XMAHD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
226 def : Pat<(mulhu GR:$src1, GR:$src2),
227 (GETFSIGD (XMAHUD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
229 // TODO: addp4 (addp4 dst = src, r0 is a 32-bit add)
232 // def ADDS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
233 // "adds $dst = $imm, $src1">;
235 def AND : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
236 "and $dst = $src1, $src2",
237 [(set GR:$dst, (and GR:$src1, GR:$src2))]>;
238 def ANDCM : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
239 "andcm $dst = $src1, $src2",
240 [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>;
241 // TODO: and/andcm/or/xor/add/sub/shift immediate forms
242 def OR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
243 "or $dst = $src1, $src2",
244 [(set GR:$dst, (or GR:$src1, GR:$src2))]>;
246 def pOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2, PR:$qp),
247 "($qp) or $dst = $src1, $src2">;
249 // the following are all a bit unfortunate: we throw away the complement
251 def CMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
252 "cmp.eq $dst, p0 = $src1, $src2",
253 [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>;
254 def CMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
255 "cmp.gt $dst, p0 = $src1, $src2",
256 [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>;
257 def CMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
258 "cmp.ge $dst, p0 = $src1, $src2",
259 [(set PR:$dst, (setge GR:$src1, GR:$src2))]>;
260 def CMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
261 "cmp.lt $dst, p0 = $src1, $src2",
262 [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>;
263 def CMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
264 "cmp.le $dst, p0 = $src1, $src2",
265 [(set PR:$dst, (setle GR:$src1, GR:$src2))]>;
266 def CMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
267 "cmp.ne $dst, p0 = $src1, $src2",
268 [(set PR:$dst, (setne GR:$src1, GR:$src2))]>;
269 def CMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
270 "cmp.ltu $dst, p0 = $src1, $src2",
271 [(set PR:$dst, (setult GR:$src1, GR:$src2))]>;
272 def CMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
273 "cmp.gtu $dst, p0 = $src1, $src2",
274 [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>;
275 def CMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
276 "cmp.leu $dst, p0 = $src1, $src2",
277 [(set PR:$dst, (setule GR:$src1, GR:$src2))]>;
278 def CMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
279 "cmp.geu $dst, p0 = $src1, $src2",
280 [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>;
282 // and we do the whole thing again for FP compares!
283 def FCMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
284 "fcmp.eq $dst, p0 = $src1, $src2",
285 [(set PR:$dst, (seteq FP:$src1, FP:$src2))]>;
286 def FCMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
287 "fcmp.gt $dst, p0 = $src1, $src2",
288 [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>;
289 def FCMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
290 "fcmp.ge $dst, p0 = $src1, $src2",
291 [(set PR:$dst, (setge FP:$src1, FP:$src2))]>;
292 def FCMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
293 "fcmp.lt $dst, p0 = $src1, $src2",
294 [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>;
295 def FCMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
296 "fcmp.le $dst, p0 = $src1, $src2",
297 [(set PR:$dst, (setle FP:$src1, FP:$src2))]>;
298 def FCMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
299 "fcmp.neq $dst, p0 = $src1, $src2",
300 [(set PR:$dst, (setne FP:$src1, FP:$src2))]>;
301 def FCMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
302 "fcmp.ltu $dst, p0 = $src1, $src2",
303 [(set PR:$dst, (setult FP:$src1, FP:$src2))]>;
304 def FCMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
305 "fcmp.gtu $dst, p0 = $src1, $src2",
306 [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>;
307 def FCMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
308 "fcmp.leu $dst, p0 = $src1, $src2",
309 [(set PR:$dst, (setule FP:$src1, FP:$src2))]>;
310 def FCMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
311 "fcmp.geu $dst, p0 = $src1, $src2",
312 [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>;
314 def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$qp),
315 "($qp) cmp.eq.unc $dst, p0 = r0, r0">;
317 def : Pat<(trunc GR:$src), // truncate i64 to i1
318 (CMPNE GR:$src, r0)>; // $src!=0? If so, PR:$dst=true
320 let isTwoAddress=1 in {
321 def TPCMPEQR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
322 "($qp) cmp.eq $dst, p0 = r0, r0">;
323 def TPCMPNER0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
324 "($qp) cmp.ne $dst, p0 = r0, r0">;
327 /* our pseudocode for OR on predicates is:
330 (pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
332 (pB) cmp.eq pC,p0 = r0,r0 // if (pB) pC = 1 */
334 def bOR : Pat<(or PR:$src1, PR:$src2),
335 (TPCMPEQR0R0 (PCMPEQUNCR0R0 PR:$src1), PR:$src2)>;
337 /* our pseudocode for AND on predicates is:
339 (pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
340 cmp.eq pTemp,p0 = r0,r0 // pTemp = NOT pB
342 (pB) cmp.ne pTemp,p0 = r0,r0
344 (pTemp)cmp.ne pC,p0 = r0,r0 // if (NOT pB) pC = 0 */
346 def bAND : Pat<(and PR:$src1, PR:$src2),
347 ( TPCMPNER0R0 (PCMPEQUNCR0R0 PR:$src1),
348 (TPCMPNER0R0 (CMPEQ r0, r0), PR:$src2) )>;
350 /* one possible routine for XOR on predicates is:
352 // Compute px = py ^ pz
353 // using sum of products: px = (py & !pz) | (pz & !py)
354 // Uses 5 instructions in 3 cycles.
356 (pz) cmp.eq.unc px = r0, r0 // px = pz
357 (py) cmp.eq.unc pt = r0, r0 // pt = py
360 (pt) cmp.ne.and px = r0, r0 // px = px & !pt (px = pz & !pt)
361 (pz) cmp.ne.and pt = r0, r0 // pt = pt & !pz
365 (pt) cmp.eq.or px = r0, r0 // px = px | pt
367 *** Another, which we use here, requires one scratch GR. it is:
369 mov rt = 0 // initialize rt off critical path
373 (pz) cmp.eq.unc px = r0, r0 // px = pz
374 (pz) mov rt = 1 // rt = pz
377 (py) cmp.ne px = 1, rt // if (py) px = !pz
379 .. these routines kindly provided by Jim Hull
382 def bXOR : Pat<(xor PR:$src1, PR:$src2),
383 (TPCMPIMM8NE (PCMPEQUNCR0R0 PR:$src2), 1,
384 (TPCADDS (ADDS r0, 0), 1, PR:$src2),
387 def XOR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
388 "xor $dst = $src1, $src2",
389 [(set GR:$dst, (xor GR:$src1, GR:$src2))]>;
391 def SHLADD: AForm_DAG<0x03, 0x0b, (ops GR:$dst,GR:$src1,s64imm:$imm,GR:$src2),
392 "shladd $dst = $src1, $imm, $src2",
393 [(set GR:$dst, (add GR:$src2, (shl GR:$src1, isSHLADDimm:$imm)))]>;
395 def SHL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
396 "shl $dst = $src1, $src2",
397 [(set GR:$dst, (shl GR:$src1, GR:$src2))]>;
399 def SHRU : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
400 "shr.u $dst = $src1, $src2",
401 [(set GR:$dst, (srl GR:$src1, GR:$src2))]>;
403 def SHRS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
404 "shr $dst = $src1, $src2",
405 [(set GR:$dst, (sra GR:$src1, GR:$src2))]>;
407 def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src">;
408 def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
409 "mov $dst = $src">; // XXX: there _is_ no fmov
410 def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
411 "($qp) mov $dst = $src">;
413 def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (ops GR:$dst),
415 def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (ops GR:$src),
418 let isTwoAddress = 1 in {
419 def CMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
420 "($qp) mov $dst = $src">;
423 def PFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
424 "($qp) mov $dst = $src">;
426 let isTwoAddress = 1 in {
427 def CFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
428 "($qp) mov $dst = $src">;
431 def SELECTINT : Pat<(select PR:$which, GR:$src1, GR:$src2),
432 (CMOV (MOV GR:$src2), GR:$src1, PR:$which)>; // note order!
433 def SELECTFP : Pat<(select PR:$which, FP:$src1, FP:$src2),
434 (CFMOV (FMOV FP:$src2), FP:$src1, PR:$which)>; // note order!
435 // TODO: can do this faster, w/o using any integer regs (see pattern isel)
436 def SELECTBOOL : Pat<(select PR:$which, PR:$src1, PR:$src2), // note order!
438 (MOV (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src2)),
439 (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src1), PR:$which), r0)>;
441 // load constants of various sizes // FIXME: prettyprint -ve constants
442 def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
443 def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>;
444 def : Pat<(i1 -1), (CMPEQ r0, r0)>; // TODO: this should just be a ref to p0
445 def : Pat<(i1 0), (CMPNE r0, r0)>; // TODO: any instruction actually *using*
446 // this predicate should be killed!
448 // TODO: support postincrement (reg, imm9) loads+stores - this needs more
451 def PHI : PseudoInstIA64<(ops variable_ops), "PHI">;
452 def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">;
454 def IDEF_GR_D : PseudoInstIA64_DAG<(ops GR:$reg), "// $reg = IDEF",
455 [(set GR:$reg, (undef))]>;
456 def IDEF_FP_D : PseudoInstIA64_DAG<(ops FP:$reg), "// $reg = IDEF",
457 [(set FP:$reg, (undef))]>;
458 def IDEF_PR_D : PseudoInstIA64_DAG<(ops PR:$reg), "// $reg = IDEF",
459 [(set PR:$reg, (undef))]>;
461 def IUSE : PseudoInstIA64<(ops variable_ops), "// IUSE">;
462 def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops variable_ops),
463 "// ADJUSTCALLSTACKUP">;
464 def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops variable_ops),
465 "// ADJUSTCALLSTACKDOWN">;
466 def PSEUDO_ALLOC : PseudoInstIA64<(ops GR:$foo), "// PSEUDO_ALLOC">;
468 def ALLOC : AForm<0x03, 0x0b,
469 (ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
470 "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating">;
472 let isTwoAddress = 1 in {
473 def TCMPNE : AForm<0x03, 0x0b,
474 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4),
475 "cmp.ne $dst, p0 = $src3, $src4">;
477 def TPCMPEQOR : AForm<0x03, 0x0b,
478 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
479 "($qp) cmp.eq.or $dst, p0 = $src3, $src4">;
481 def TPCMPNE : AForm<0x03, 0x0b,
482 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
483 "($qp) cmp.ne $dst, p0 = $src3, $src4">;
485 def TPCMPEQ : AForm<0x03, 0x0b,
486 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
487 "($qp) cmp.eq $dst, p0 = $src3, $src4">;
490 def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm),
492 def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm),
494 def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
497 def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
498 "shl $dst = $src1, $imm">;
499 def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
500 "shr.u $dst = $src1, $imm">;
501 def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
502 "shr $dst = $src1, $imm">;
504 def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
505 "extr.u $dst = $src1, $imm1, $imm2">;
507 def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2">;
509 def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
510 "($qp) cmp.eq.or $dst, p0 = $src1, $src2">;
511 def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
512 "($qp) cmp.eq.unc $dst, p0 = $src1, $src2">;
513 def PCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
514 "($qp) cmp.ne $dst, p0 = $src1, $src2">;
517 def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2),
518 "cmp.eq $dst1, dst2 = $src1, $src2">;
520 def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
521 "adds $dst = $imm, $src1">;
523 def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm),
524 "add $dst = $imm, $src1">;
525 def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
526 "($qp) add $dst = $imm, $src1">;
528 def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
529 "sub $dst = $imm, $src2">;
531 let isStore = 1, noResults = 1 in {
532 def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
533 "st1 [$dstPtr] = $value">;
534 def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
535 "st2 [$dstPtr] = $value">;
536 def ST4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
537 "st4 [$dstPtr] = $value">;
538 def ST8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
539 "st8 [$dstPtr] = $value">;
540 def STF4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
541 "stfs [$dstPtr] = $value">;
542 def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
543 "stfd [$dstPtr] = $value">;
544 def STF_SPILL : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
545 "stf.spill [$dstPtr] = $value">;
549 def LD1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
550 "ld1 $dst = [$srcPtr]">;
551 def LD2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
552 "ld2 $dst = [$srcPtr]">;
553 def LD4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
554 "ld4 $dst = [$srcPtr]">;
555 def LD8 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
556 "ld8 $dst = [$srcPtr]">;
557 def LDF4 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
558 "ldfs $dst = [$srcPtr]">;
559 def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
560 "ldfd $dst = [$srcPtr]">;
561 def LDF_FILL : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
562 "ldf.fill $dst = [$srcPtr]">;
565 def POPCNT : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src),
566 "popcnt $dst = $src",
567 [(set GR:$dst, (ctpop GR:$src))]>;
569 // some FP stuff: // TODO: single-precision stuff?
570 def FADD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
571 "fadd $dst = $src1, $src2",
572 [(set FP:$dst, (fadd FP:$src1, FP:$src2))]>;
573 def FADDS: AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
574 "fadd.s $dst = $src1, $src2">;
575 def FSUB : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
576 "fsub $dst = $src1, $src2",
577 [(set FP:$dst, (fsub FP:$src1, FP:$src2))]>;
578 def FMPY : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
579 "fmpy $dst = $src1, $src2",
580 [(set FP:$dst, (fmul FP:$src1, FP:$src2))]>;
581 def FMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
582 "fma $dst = $src1, $src2, $src3",
583 [(set FP:$dst, (fadd (fmul FP:$src1, FP:$src2), FP:$src3))]>;
584 def FMS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
585 "fms $dst = $src1, $src2, $src3",
586 [(set FP:$dst, (fsub (fmul FP:$src1, FP:$src2), FP:$src3))]>;
587 def FNMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
588 "fnma $dst = $src1, $src2, $src3",
589 [(set FP:$dst, (fneg (fadd (fmul FP:$src1, FP:$src2), FP:$src3)))]>;
590 def FABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
592 [(set FP:$dst, (fabs FP:$src))]>;
593 def FNEG : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
595 [(set FP:$dst, (fneg FP:$src))]>;
596 def FNEGABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
597 "fnegabs $dst = $src",
598 [(set FP:$dst, (fneg (fabs FP:$src)))]>;
600 let isTwoAddress=1 in {
601 def TCFMAS1 : AForm<0x03, 0x0b,
602 (ops FP:$dst, FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
603 "($qp) fma.s1 $dst = $src1, $src2, $src3">;
604 def TCFMADS0 : AForm<0x03, 0x0b,
605 (ops FP:$dst, FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
606 "($qp) fma.d.s0 $dst = $src1, $src2, $src3">;
609 def CFMAS1 : AForm<0x03, 0x0b,
610 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
611 "($qp) fma.s1 $dst = $src1, $src2, $src3">;
612 def CFNMAS1 : AForm<0x03, 0x0b,
613 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
614 "($qp) fnma.s1 $dst = $src1, $src2, $src3">;
616 def CFMADS1 : AForm<0x03, 0x0b,
617 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
618 "($qp) fma.d.s1 $dst = $src1, $src2, $src3">;
619 def CFMADS0 : AForm<0x03, 0x0b,
620 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
621 "($qp) fma.d.s0 $dst = $src1, $src2, $src3">;
622 def CFNMADS1 : AForm<0x03, 0x0b,
623 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
624 "($qp) fnma.d.s1 $dst = $src1, $src2, $src3">;
626 def FRCPAS0 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
627 "frcpa.s0 $dstFR, $dstPR = $src1, $src2">;
628 def FRCPAS1 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
629 "frcpa.s1 $dstFR, $dstPR = $src1, $src2">;
631 def XMAL : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
632 "xma.l $dst = $src1, $src2, $src3">;
634 def FCVTXF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
635 "fcvt.xf $dst = $src">;
636 def FCVTXUF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
637 "fcvt.xuf $dst = $src">;
638 def FCVTXUFS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
639 "fcvt.xuf.s1 $dst = $src">;
640 def FCVTFX : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
641 "fcvt.fx $dst = $src">;
642 def FCVTFXU : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
643 "fcvt.fxu $dst = $src">;
645 def FCVTFXTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
646 "fcvt.fx.trunc $dst = $src">;
647 def FCVTFXUTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
648 "fcvt.fxu.trunc $dst = $src">;
650 def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
651 "fcvt.fx.trunc.s1 $dst = $src">;
652 def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
653 "fcvt.fxu.trunc.s1 $dst = $src">;
655 def FNORMD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
656 "fnorm.d $dst = $src">;
658 def GETFD : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
659 "getf.d $dst = $src">;
660 def SETFD : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
661 "setf.d $dst = $src">;
663 def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
664 "getf.sig $dst = $src">;
665 def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
666 "setf.sig $dst = $src">;
668 // these four FP<->int conversion patterns need checking/cleaning
669 def SINT_TO_FP : Pat<(sint_to_fp GR:$src),
670 (FNORMD (FCVTXF (SETFSIG GR:$src)))>;
671 def UINT_TO_FP : Pat<(uint_to_fp GR:$src),
672 (FNORMD (FCVTXUF (SETFSIG GR:$src)))>;
673 def FP_TO_SINT : Pat<(i64 (fp_to_sint FP:$src)),
674 (GETFSIG (FCVTFXTRUNC FP:$src))>;
675 def FP_TO_UINT : Pat<(i64 (fp_to_uint FP:$src)),
676 (GETFSIG (FCVTFXUTRUNC FP:$src))>;
679 let isTerminator = 1, isBranch = 1, noResults = 1 in {
680 def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
681 "(p0) brl.cond.sptk $dst">;
682 def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
683 "($qp) brl.cond.sptk $dst">;
684 def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
685 "($qp) br.cond.sptk $dst">;
688 let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
689 Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
690 // all calls clobber non-callee-saved registers, and for now, they are these:
691 Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
692 r25,r26,r27,r28,r29,r30,r31,
693 p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,
694 F6,F7,F8,F9,F10,F11,F12,F13,F14,F15,
695 F32,F33,F34,F35,F36,F37,F38,F39,F40,F41,F42,F43,F44,F45,F46,F47,F48,F49,
696 F50,F51,F52,F53,F54,F55,F56,
697 F57,F58,F59,F60,F61,F62,F63,F64,F65,F66,F67,F68,F69,F70,F71,F72,F73,F74,
698 F75,F76,F77,F78,F79,F80,F81,
699 F82,F83,F84,F85,F86,F87,F88,F89,F90,F91,F92,F93,F94,F95,F96,F97,F98,F99,
700 F100,F101,F102,F103,F104,F105,
701 F106,F107,F108,F109,F110,F111,F112,F113,F114,F115,F116,F117,F118,F119,
702 F120,F121,F122,F123,F124,F125,F126,F127,
703 out0,out1,out2,out3,out4,out5,out6,out7] in {
705 def BRCALL: RawForm<0x03, 0xb0, (ops calltarget:$dst),
706 "br.call.sptk rp = $dst">; // FIXME: teach llvm about branch regs?
709 // calls a globaladdress
710 def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (ops calltarget:$dst),
711 "br.call.sptk rp = $dst">; // FIXME: teach llvm about branch regs?
712 // calls an externalsymbol
713 def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (ops calltarget:$dst),
714 "br.call.sptk rp = $dst">; // FIXME: teach llvm about branch regs?
715 // calls through a function descriptor
716 def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg),
717 "br.call.sptk rp = $branchreg">; // FIXME: teach llvm about branch regs?
718 def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
719 "($qp) brl.cond.call.sptk $dst">;
720 def BRCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
721 "($qp) br.cond.call.sptk $dst">;
725 let isTerminator = 1, isReturn = 1, noResults = 1 in
726 def RET : AForm_DAG<0x03, 0x0b, (ops),
727 "br.ret.sptk.many rp",
728 [(retflag)]>; // return
729 def : Pat<(ret), (RET)>;
731 // the evil stop bit of despair
732 def STOP : PseudoInstIA64<(ops variable_ops), ";;">;