1 //===- IA64InstrInfo.cpp - IA64 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64InstrInfo.h"
16 #include "IA64InstrBuilder.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "IA64GenInstrInfo.inc"
23 IA64InstrInfo::IA64InstrInfo()
24 : TargetInstrInfoImpl(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
29 bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
32 unsigned& SrcSR, unsigned& DstSR) const {
33 SrcSR = DstSR = 0; // No sub-registers.
35 unsigned oc = MI.getOpcode();
36 if (oc == IA64::MOV || oc == IA64::FMOV) {
37 // TODO: this doesn't detect predicate moves
38 assert(MI.getNumOperands() >= 2 &&
39 /* MI.getOperand(0).isReg() &&
40 MI.getOperand(1).isReg() && */
41 "invalid register-register move instruction");
42 if (MI.getOperand(0).isReg() &&
43 MI.getOperand(1).isReg()) {
44 // if both operands of the MOV/FMOV are registers, then
45 // yes, this is a move instruction
46 sourceReg = MI.getOperand(1).getReg();
47 destReg = MI.getOperand(0).getReg();
51 return false; // we don't consider e.g. %regN = MOV <FrameIndex #x> a
56 IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
57 MachineBasicBlock *FBB,
58 const SmallVectorImpl<MachineOperand> &Cond)const {
59 // FIXME this should probably have a DebugLoc argument
60 DebugLoc dl = DebugLoc::getUnknownLoc();
61 // Can only insert uncond branches so far.
62 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
63 BuildMI(&MBB, dl, get(IA64::BRL_NOTCALL)).addMBB(TBB);
67 bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator MI,
69 unsigned DestReg, unsigned SrcReg,
70 const TargetRegisterClass *DestRC,
71 const TargetRegisterClass *SrcRC) const {
72 if (DestRC != SrcRC) {
77 DebugLoc DL = DebugLoc::getUnknownLoc();
78 if (MI != MBB.end()) DL = MI->getDebugLoc();
80 if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
81 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
82 BuildMI(MBB, MI, DL, get(IA64::PCMPEQUNC), DestReg)
83 .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
84 else // otherwise, MOV works (for both gen. regs and FP regs)
85 BuildMI(MBB, MI, DL, get(IA64::MOV), DestReg).addReg(SrcReg);
90 void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator MI,
92 unsigned SrcReg, bool isKill,
94 const TargetRegisterClass *RC) const{
95 DebugLoc DL = DebugLoc::getUnknownLoc();
96 if (MI != MBB.end()) DL = MI->getDebugLoc();
98 if (RC == IA64::FPRegisterClass) {
99 BuildMI(MBB, MI, DL, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
100 .addReg(SrcReg, getKillRegState(isKill));
101 } else if (RC == IA64::GRRegisterClass) {
102 BuildMI(MBB, MI, DL, get(IA64::ST8)).addFrameIndex(FrameIdx)
103 .addReg(SrcReg, getKillRegState(isKill));
104 } else if (RC == IA64::PRRegisterClass) {
105 /* we use IA64::r2 as a temporary register for doing this hackery. */
107 BuildMI(MBB, MI, DL, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
108 // then conditionally add 1:
109 BuildMI(MBB, MI, DL, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
110 .addImm(1).addReg(SrcReg, getKillRegState(isKill));
111 // and then store it to the stack
112 BuildMI(MBB, MI, DL, get(IA64::ST8))
113 .addFrameIndex(FrameIdx)
116 llvm_unreachable("sorry, I don't know how to store this sort of reg"
120 void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
122 SmallVectorImpl<MachineOperand> &Addr,
123 const TargetRegisterClass *RC,
124 SmallVectorImpl<MachineInstr*> &NewMIs) const {
126 if (RC == IA64::FPRegisterClass) {
128 } else if (RC == IA64::GRRegisterClass) {
130 } else if (RC == IA64::PRRegisterClass) {
133 llvm_unreachable("sorry, I don't know how to store this sort of reg");
136 DebugLoc DL = DebugLoc::getUnknownLoc();
137 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
138 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
139 MIB.addOperand(Addr[i]);
140 MIB.addReg(SrcReg, getKillRegState(isKill));
141 NewMIs.push_back(MIB);
146 void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator MI,
148 unsigned DestReg, int FrameIdx,
149 const TargetRegisterClass *RC)const{
150 DebugLoc DL = DebugLoc::getUnknownLoc();
151 if (MI != MBB.end()) DL = MI->getDebugLoc();
153 if (RC == IA64::FPRegisterClass) {
154 BuildMI(MBB, MI, DL, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
155 } else if (RC == IA64::GRRegisterClass) {
156 BuildMI(MBB, MI, DL, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
157 } else if (RC == IA64::PRRegisterClass) {
158 // first we load a byte from the stack into r2, our 'predicate hackery'
160 BuildMI(MBB, MI, DL, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
161 // then we compare it to zero. If it _is_ zero, compare-not-equal to
162 // r0 gives us 0, which is what we want, so that's nice.
163 BuildMI(MBB, MI, DL, get(IA64::CMPNE), DestReg)
167 llvm_unreachable("sorry, I don't know how to load this sort of reg"
172 void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
173 SmallVectorImpl<MachineOperand> &Addr,
174 const TargetRegisterClass *RC,
175 SmallVectorImpl<MachineInstr*> &NewMIs) const {
177 if (RC == IA64::FPRegisterClass) {
179 } else if (RC == IA64::GRRegisterClass) {
181 } else if (RC == IA64::PRRegisterClass) {
184 llvm_unreachable("sorry, I don't know how to load this sort of reg");
187 DebugLoc DL = DebugLoc::getUnknownLoc();
188 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
189 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
190 MIB.addOperand(Addr[i]);
191 NewMIs.push_back(MIB);