1 //===-- IA64ISelPattern.cpp - A pattern matching inst selector for IA64 ---===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64.
12 //===----------------------------------------------------------------------===//
15 #include "IA64InstrBuilder.h"
16 #include "IA64RegisterInfo.h"
17 #include "IA64MachineFunctionInfo.h"
18 #include "llvm/Constants.h" // FIXME: REMOVE
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/MathExtras.h"
29 #include "llvm/ADT/Statistic.h"
35 //===----------------------------------------------------------------------===//
36 // IA64TargetLowering - IA64 Implementation of the TargetLowering interface
38 class IA64TargetLowering : public TargetLowering {
39 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
41 //int ReturnAddrIndex; // FrameIndex for return slot.
42 unsigned GP, SP, RP; // FIXME - clean this mess up
45 unsigned VirtGPR; // this is public so it can be accessed in the selector
46 // for ISD::RET down below. add an accessor instead? FIXME
48 IA64TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
50 // register class for general registers
51 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
53 // register class for FP registers
54 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
56 // register class for predicate registers
57 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
59 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
60 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
61 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
63 setSetCCResultType(MVT::i1);
64 setShiftAmountType(MVT::i64);
66 setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
68 setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
70 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
71 setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
72 setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
73 setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand);
75 setOperationAction(ISD::FREM , MVT::f32 , Expand);
76 setOperationAction(ISD::FREM , MVT::f64 , Expand);
78 setOperationAction(ISD::UREM , MVT::f32 , Expand);
79 setOperationAction(ISD::UREM , MVT::f64 , Expand);
81 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
85 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
86 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
88 // We don't support sin/cos/sqrt
89 setOperationAction(ISD::FSIN , MVT::f64, Expand);
90 setOperationAction(ISD::FCOS , MVT::f64, Expand);
91 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
92 setOperationAction(ISD::FSIN , MVT::f32, Expand);
93 setOperationAction(ISD::FCOS , MVT::f32, Expand);
94 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
96 //IA64 has these, but they are not implemented
97 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
98 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
99 // FIXME: implement mulhs (xma.h) and mulhu (xma.hu)
100 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
101 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
103 computeRegisterProperties();
105 addLegalFPImmediate(+0.0);
106 addLegalFPImmediate(+1.0);
107 addLegalFPImmediate(-0.0);
108 addLegalFPImmediate(-1.0);
111 /// LowerArguments - This hook must be implemented to indicate how we should
112 /// lower the arguments for the specified function, into the specified DAG.
113 virtual std::vector<SDOperand>
114 LowerArguments(Function &F, SelectionDAG &DAG);
116 /// LowerCallTo - This hook lowers an abstract call to a function into an
118 virtual std::pair<SDOperand, SDOperand>
119 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
120 bool isTailCall, SDOperand Callee, ArgListTy &Args,
123 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
124 Value *VAListV, SelectionDAG &DAG);
125 virtual std::pair<SDOperand,SDOperand>
126 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
127 const Type *ArgTy, SelectionDAG &DAG);
129 void restoreGP_SP_RP(MachineBasicBlock* BB)
131 BuildMI(BB, IA64::MOV, 1, IA64::r1).addReg(GP);
132 BuildMI(BB, IA64::MOV, 1, IA64::r12).addReg(SP);
133 BuildMI(BB, IA64::MOV, 1, IA64::rp).addReg(RP);
136 void restoreSP_RP(MachineBasicBlock* BB)
138 BuildMI(BB, IA64::MOV, 1, IA64::r12).addReg(SP);
139 BuildMI(BB, IA64::MOV, 1, IA64::rp).addReg(RP);
142 void restoreRP(MachineBasicBlock* BB)
144 BuildMI(BB, IA64::MOV, 1, IA64::rp).addReg(RP);
147 void restoreGP(MachineBasicBlock* BB)
149 BuildMI(BB, IA64::MOV, 1, IA64::r1).addReg(GP);
156 std::vector<SDOperand>
157 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
158 std::vector<SDOperand> ArgValues;
161 // add beautiful description of IA64 stack frame format
162 // here (from intel 24535803.pdf most likely)
164 MachineFunction &MF = DAG.getMachineFunction();
165 MachineFrameInfo *MFI = MF.getFrameInfo();
167 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
168 SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
169 RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
171 MachineBasicBlock& BB = MF.front();
173 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
174 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
176 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
177 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
183 unsigned used_FPArgs = 0; // how many FP args have been used so far?
185 unsigned ArgOffset = 0;
188 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
190 SDOperand newroot, argt;
191 if(count < 8) { // need to fix this logic? maybe.
193 switch (getValueType(I->getType())) {
195 std::cerr << "ERROR in LowerArgs: unknown type "
196 << getValueType(I->getType()) << "\n";
199 // fixme? (well, will need to for weird FP structy stuff,
200 // see intel ABI docs)
202 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
203 MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
204 // floating point args go into f8..f15 as-needed, the increment
205 argVreg[count] = // is below..:
206 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
207 // FP args go into f8..f15 as needed: (hence the ++)
208 argPreg[count] = args_FP[used_FPArgs++];
209 argOpc[count] = IA64::FMOV;
210 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
212 if (I->getType() == Type::FloatTy)
213 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
215 case MVT::i1: // NOTE: as far as C abi stuff goes,
216 // bools are just boring old ints
221 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
222 MF.addLiveIn(args_int[count]); // mark this register as liveIn
224 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
225 argPreg[count] = args_int[count];
226 argOpc[count] = IA64::MOV;
228 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
229 if ( getValueType(I->getType()) != MVT::i64)
230 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
234 } else { // more than 8 args go into the frame
235 // Create the frame index object for this incoming parameter...
236 ArgOffset = 16 + 8 * (count - 8);
237 int FI = MFI->CreateFixedObject(8, ArgOffset);
239 // Create the SelectionDAG nodes corresponding to a load
240 //from this parameter
241 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
242 argt = newroot = DAG.getLoad(getValueType(I->getType()),
243 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
246 DAG.setRoot(newroot.getValue(1));
247 ArgValues.push_back(argt);
251 // Create a vreg to hold the output of (what will become)
252 // the "alloc" instruction
253 VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
254 BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
255 // we create a PSEUDO_ALLOC (pseudo)instruction for now
257 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
260 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
261 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
264 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
267 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
268 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
271 unsigned tempOffset=0;
273 // if this is a varargs function, we simply lower llvm.va_start by
274 // pointing to the first entry
277 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
280 // here we actually do the moving of args, and store them to the stack
281 // too if this is a varargs function:
282 for (int i = 0; i < count && i < 8; ++i) {
283 BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
285 // if this is a varargs function, we copy the input registers to the stack
286 int FI = MFI->CreateFixedObject(8, tempOffset);
287 tempOffset+=8; //XXX: is it safe to use r22 like this?
288 BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
289 // FIXME: we should use st8.spill here, one day
290 BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
294 // Finally, inform the code generator which regs we return values in.
295 // (see the ISD::RET: case down below)
296 switch (getValueType(F.getReturnType())) {
297 default: assert(0 && "i have no idea where to return this type!");
298 case MVT::isVoid: break;
304 MF.addLiveOut(IA64::r8);
308 MF.addLiveOut(IA64::F8);
315 std::pair<SDOperand, SDOperand>
316 IA64TargetLowering::LowerCallTo(SDOperand Chain,
317 const Type *RetTy, bool isVarArg,
318 unsigned CallingConv, bool isTailCall,
319 SDOperand Callee, ArgListTy &Args,
322 MachineFunction &MF = DAG.getMachineFunction();
324 unsigned NumBytes = 16;
325 unsigned outRegsUsed = 0;
327 if (Args.size() > 8) {
328 NumBytes += (Args.size() - 8) * 8;
331 outRegsUsed = Args.size();
334 // FIXME? this WILL fail if we ever try to pass around an arg that
335 // consumes more than a single output slot (a 'real' double, int128
336 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
337 // registers we use. Hopefully, the assembler will notice.
338 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
339 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
341 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
342 DAG.getConstant(NumBytes, getPointerTy()));
344 std::vector<SDOperand> args_to_use;
345 for (unsigned i = 0, e = Args.size(); i != e; ++i)
347 switch (getValueType(Args[i].second)) {
348 default: assert(0 && "unexpected argument type!");
353 //promote to 64-bits, sign/zero extending based on type
355 if(Args[i].second->isSigned())
356 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64,
359 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64,
364 Args[i].first = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Args[i].first);
369 args_to_use.push_back(Args[i].first);
372 std::vector<MVT::ValueType> RetVals;
373 MVT::ValueType RetTyVT = getValueType(RetTy);
374 if (RetTyVT != MVT::isVoid)
375 RetVals.push_back(RetTyVT);
376 RetVals.push_back(MVT::Other);
378 SDOperand TheCall = SDOperand(DAG.getCall(RetVals, Chain,
379 Callee, args_to_use), 0);
380 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
381 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
382 DAG.getConstant(NumBytes, getPointerTy()));
383 return std::make_pair(TheCall, Chain);
387 IA64TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
388 Value *VAListV, SelectionDAG &DAG) {
389 // vastart just stores the address of the VarArgsFrameIndex slot.
390 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
391 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR,
392 VAListP, DAG.getSrcValue(VAListV));
395 std::pair<SDOperand,SDOperand> IA64TargetLowering::
396 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
397 const Type *ArgTy, SelectionDAG &DAG) {
399 MVT::ValueType ArgVT = getValueType(ArgTy);
400 SDOperand Val = DAG.getLoad(MVT::i64, Chain,
401 VAListP, DAG.getSrcValue(VAListV));
402 SDOperand Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), Val,
403 DAG.getSrcValue(NULL));
405 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
408 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
409 "Other types should have been promoted for varargs!");
412 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
413 DAG.getConstant(Amt, Val.getValueType()));
414 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
415 Val, VAListP, DAG.getSrcValue(VAListV));
416 return std::make_pair(Result, Chain);
421 //===--------------------------------------------------------------------===//
422 /// ISel - IA64 specific code to select IA64 machine instructions for
423 /// SelectionDAG operations.
425 class ISel : public SelectionDAGISel {
426 /// IA64Lowering - This object fully describes how to lower LLVM code to an
427 /// IA64-specific SelectionDAG.
428 IA64TargetLowering IA64Lowering;
429 SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
430 // for sdiv and udiv until it is put into the future
433 /// ExprMap - As shared expressions are codegen'd, we keep track of which
434 /// vreg the value is produced in, so we only emit one copy of each compiled
436 std::map<SDOperand, unsigned> ExprMap;
437 std::set<SDOperand> LoweredTokens;
440 ISel(TargetMachine &TM) : SelectionDAGISel(IA64Lowering), IA64Lowering(TM),
443 /// InstructionSelectBasicBlock - This callback is invoked by
444 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
445 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
447 unsigned SelectExpr(SDOperand N);
448 void Select(SDOperand N);
449 // a dag->dag to transform mul-by-constant-int to shifts+adds/subs
450 SDOperand BuildConstmulSequence(SDOperand N);
452 const char *getPassName() const { return "IA64 Instruction Selector"; }
456 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
457 /// when it has created a SelectionDAG for us to codegen.
458 void ISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
460 // Codegen the basic block.
462 Select(DAG.getRoot());
464 // Clear state used for selection.
466 LoweredTokens.clear();
470 // strip leading '0' characters from a string
471 void munchLeadingZeros(std::string& inString) {
472 while(inString.c_str()[0]=='0') {
473 inString.erase(0, 1);
477 // strip trailing '0' characters from a string
478 void munchTrailingZeros(std::string& inString) {
479 int curPos=inString.length()-1;
481 while(inString.c_str()[curPos]=='0') {
482 inString.erase(curPos, 1);
487 // return how many consecutive '0' characters are at the end of a string
488 unsigned int countTrailingZeros(std::string& inString) {
489 int curPos=inString.length()-1;
490 unsigned int zeroCount=0;
492 while(inString.c_str()[curPos--]=='0') {
498 // booth encode a string of '1' and '0' characters (returns string of 'P' (+1)
499 // '0' and 'N' (-1) characters)
500 void boothEncode(std::string inString, std::string& boothEncodedString) {
504 int lim=inString.size();
507 if(inString[curpos]=='1') { // if we see a '1', look for a run of them
509 std::string replaceString="N";
511 // find the run length
512 for(;inString[curpos+runlength]=='1';runlength++) ;
514 for(int i=0; i<runlength-1; i++)
519 inString.replace(curpos, runlength+1, replaceString);
523 } else { // a zero, we just keep chugging along
528 // clean up (trim the string, reverse it and turn '1's into 'P's)
529 munchTrailingZeros(inString);
530 boothEncodedString="";
532 for(int i=inString.size()-1;i>=0;i--)
534 boothEncodedString+="P";
536 boothEncodedString+=inString[i];
540 struct shiftaddblob { // this encodes stuff like (x=) "A << B [+-] C << D"
541 unsigned firstVal; // A
542 unsigned firstShift; // B
543 unsigned secondVal; // C
544 unsigned secondShift; // D
548 /* this implements Lefevre's "pattern-based" constant multiplication,
549 * see "Multiplication by an Integer Constant", INRIA report 1999-06
551 * TODO: implement a method to try rewriting P0N<->0PP / N0P<->0NN
552 * to get better booth encodings - this does help in practice
553 * TODO: weight shifts appropriately (most architectures can't
554 * fuse a shift and an add for arbitrary shift amounts) */
555 unsigned lefevre(const std::string inString,
556 std::vector<struct shiftaddblob> &ops) {
557 std::string retstring;
558 std::string s = inString;
559 munchTrailingZeros(s);
561 int length=s.length()-1;
567 std::vector<int> p,n;
569 for(int i=0; i<=length; i++) {
570 if (s.c_str()[length-i]=='P') {
572 } else if (s.c_str()[length-i]=='N') {
580 std::map<const int, int> w;
582 for(unsigned i=0; i<p.size(); i++) {
583 for(unsigned j=0; j<i; j++) {
588 for(unsigned i=1; i<n.size(); i++) {
589 for(unsigned j=0; j<i; j++) {
594 for(unsigned i=0; i<p.size(); i++) {
595 for(unsigned j=0; j<n.size(); j++) {
596 w[-abs(p[i]-n[j])]++;
600 std::map<const int, int>::const_iterator ii;
602 std::multimap<int, int> sorted_by_value;
604 for(ii = w.begin(); ii!=w.end(); ii++)
605 sorted_by_value.insert(std::pair<int, int>((*ii).second,(*ii).first));
607 for (std::multimap<int, int>::iterator it = sorted_by_value.begin();
608 it != sorted_by_value.end(); ++it) {
609 d.push_back((*it).second);
615 while(d.size()>0 && (w[int_d=d.back()] > int_W)) {
623 for(unsigned base=0; base<retstring.size(); base++) {
624 if( ((base+z+1) < retstring.size()) &&
625 retstring.c_str()[base]=='P' &&
626 retstring.c_str()[base+z+1]=='P')
630 retstring.replace(base, 1, "0");
631 retstring.replace(base+z+1, 1, "p");
635 for(unsigned base=0; base<retstring.size(); base++) {
636 if( ((base+z+1) < retstring.size()) &&
637 retstring.c_str()[base]=='N' &&
638 retstring.c_str()[base+z+1]=='N')
642 retstring.replace(base, 1, "0");
643 retstring.replace(base+z+1, 1, "n");
648 for(unsigned base=0; base<retstring.size(); base++) {
649 if( ((base+z+1) < retstring.size()) &&
650 ((retstring.c_str()[base]=='P' &&
651 retstring.c_str()[base+z+1]=='N') ||
652 (retstring.c_str()[base]=='N' &&
653 retstring.c_str()[base+z+1]=='P')) ) {
657 if(retstring.c_str()[base]=='P') {
658 retstring.replace(base, 1, "0");
659 retstring.replace(base+z+1, 1, "p");
660 } else { // retstring[base]=='N'
661 retstring.replace(base, 1, "0");
662 retstring.replace(base+z+1, 1, "n");
674 } d.pop_back(); // hmm
678 for(unsigned i=0; i<t.length(); i++) {
679 if(t.c_str()[i]=='p' || t.c_str()[i]=='n')
680 t.replace(i, 1, "0");
683 for(unsigned i=0; i<u.length(); i++) {
684 if(u[i]=='P' || u[i]=='N')
685 u.replace(i, 1, "0");
687 u.replace(i, 1, "P");
689 u.replace(i, 1, "N");
702 bool hit=(u[pos]=='N');
707 for(unsigned p=0; p<u.length(); p++) {
708 bool isP=(u[p]=='P');
709 bool isN=(u[p]=='N');
712 u.replace(p, 1, "N");
714 u.replace(p, 1, "P");
718 munchLeadingZeros(u);
720 int i = lefevre(u, ops);
724 blob.firstVal=i; blob.firstShift=c;
726 blob.secondVal=i; blob.secondShift=0;
732 munchLeadingZeros(t);
737 if(t.c_str()[0]!='P') {
739 for(unsigned p=0; p<t.length(); p++) {
740 bool isP=(t.c_str()[p]=='P');
741 bool isN=(t.c_str()[p]=='N');
744 t.replace(p, 1, "N");
746 t.replace(p, 1, "P");
750 int j = lefevre(t, ops);
752 int trail=countTrailingZeros(u);
753 blob.secondVal=i; blob.secondShift=trail;
755 trail=countTrailingZeros(t);
756 blob.firstVal=j; blob.firstShift=trail;
760 blob.isSub=false; // first + second
763 blob.isSub=true; // first - second
766 blob.isSub=true; // second - first
767 int tmpval, tmpshift;
768 tmpval=blob.firstVal;
769 tmpshift=blob.firstShift;
770 blob.firstVal=blob.secondVal;
771 blob.firstShift=blob.secondShift;
772 blob.secondVal=tmpval;
773 blob.secondShift=tmpshift;
782 SDOperand ISel::BuildConstmulSequence(SDOperand N) {
783 //FIXME: we should shortcut this stuff for multiplies by 2^n+1
784 // in particular, *3 is nicer as *2+1, not *4-1
785 int64_t constant=cast<ConstantSDNode>(N.getOperand(1))->getValue();
788 unsigned preliminaryShift=0;
790 assert(constant != 0 && "erk, you're trying to multiply by constant zero\n");
792 // first, we make the constant to multiply by positive
800 // next, we make it odd.
801 for(; (constant%2==0); preliminaryShift++)
804 //OK, we have a positive, odd number of 64 bits or less. Convert it
805 //to a binary string, constantString[0] is the LSB
806 char constantString[65];
807 for(int i=0; i<64; i++)
808 constantString[i]='0'+((constant>>i)&0x1);
809 constantString[64]=0;
811 // now, Booth encode it
812 std::string boothEncodedString;
813 boothEncode(constantString, boothEncodedString);
815 std::vector<struct shiftaddblob> ops;
816 // do the transformation, filling out 'ops'
817 lefevre(boothEncodedString, ops);
819 assert(ops.size() < 80 && "constmul code has gone haywire\n");
820 SDOperand results[80]; // temporary results (of adds/subs of shifts)
822 // now turn 'ops' into DAG bits
823 for(unsigned i=0; i<ops.size(); i++) {
824 SDOperand amt = ISelDAG->getConstant(ops[i].firstShift, MVT::i64);
825 SDOperand val = (ops[i].firstVal == 0) ? N.getOperand(0) :
826 results[ops[i].firstVal-1];
827 SDOperand left = ISelDAG->getNode(ISD::SHL, MVT::i64, val, amt);
828 amt = ISelDAG->getConstant(ops[i].secondShift, MVT::i64);
829 val = (ops[i].secondVal == 0) ? N.getOperand(0) :
830 results[ops[i].secondVal-1];
831 SDOperand right = ISelDAG->getNode(ISD::SHL, MVT::i64, val, amt);
833 results[i] = ISelDAG->getNode(ISD::SUB, MVT::i64, left, right);
835 results[i] = ISelDAG->getNode(ISD::ADD, MVT::i64, left, right);
838 // don't forget flippedSign and preliminaryShift!
839 SDOperand shiftedresult;
840 if(preliminaryShift) {
841 SDOperand finalshift = ISelDAG->getConstant(preliminaryShift, MVT::i64);
842 shiftedresult = ISelDAG->getNode(ISD::SHL, MVT::i64,
843 results[ops.size()-1], finalshift);
844 } else { // there was no preliminary divide-by-power-of-2 required
845 shiftedresult = results[ops.size()-1];
848 SDOperand finalresult;
849 if(flippedSign) { // if we were multiplying by a negative constant:
850 SDOperand zero = ISelDAG->getConstant(0, MVT::i64);
851 // subtract the result from 0 to flip its sign
852 finalresult = ISelDAG->getNode(ISD::SUB, MVT::i64, zero, shiftedresult);
853 } else { // there was no preliminary multiply by -1 required
854 finalresult = shiftedresult;
860 /// ponderIntegerDivisionBy - When handling integer divides, if the divide
861 /// is by a constant such that we can efficiently codegen it, this
862 /// function says what to do. Currently, it returns 0 if the division must
863 /// become a genuine divide, and 1 if the division can be turned into a
865 static unsigned ponderIntegerDivisionBy(SDOperand N, bool isSigned,
867 if (N.getOpcode() != ISD::Constant) return 0; // if not a divide by
868 // a constant, give up.
870 int64_t v = (int64_t)cast<ConstantSDNode>(N)->getSignExtended();
872 if (isPowerOf2_64(v)) { // if a division by a power of two, say so
877 return 0; // fallthrough
880 static unsigned ponderIntegerAndWith(SDOperand N, unsigned& Imm) {
881 if (N.getOpcode() != ISD::Constant) return 0; // if not ANDing with
882 // a constant, give up.
884 int64_t v = (int64_t)cast<ConstantSDNode>(N)->getSignExtended();
886 if (isMask_64(v)) { // if ANDing with ((2^n)-1) for some n
887 Imm = Log2_64(v) + 1;
891 return 0; // fallthrough
894 static unsigned ponderIntegerAdditionWith(SDOperand N, unsigned& Imm) {
895 if (N.getOpcode() != ISD::Constant) return 0; // if not adding a
896 // constant, give up.
897 int64_t v = (int64_t)cast<ConstantSDNode>(N)->getSignExtended();
899 if (v <= 8191 && v >= -8192) { // if this constants fits in 14 bits, say so
900 Imm = v & 0x3FFF; // 14 bits
903 return 0; // fallthrough
906 static unsigned ponderIntegerSubtractionFrom(SDOperand N, unsigned& Imm) {
907 if (N.getOpcode() != ISD::Constant) return 0; // if not subtracting a
908 // constant, give up.
909 int64_t v = (int64_t)cast<ConstantSDNode>(N)->getSignExtended();
911 if (v <= 127 && v >= -128) { // if this constants fits in 8 bits, say so
912 Imm = v & 0xFF; // 8 bits
915 return 0; // fallthrough
918 unsigned ISel::SelectExpr(SDOperand N) {
920 unsigned Tmp1, Tmp2, Tmp3;
922 MVT::ValueType DestType = N.getValueType();
924 unsigned opcode = N.getOpcode();
926 SDNode *Node = N.Val;
929 if (Node->getOpcode() == ISD::CopyFromReg)
930 // Just use the specified register as our input.
931 return cast<RegisterSDNode>(Node->getOperand(1))->getReg();
933 unsigned &Reg = ExprMap[N];
936 if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::TAILCALL)
937 Reg = Result = (N.getValueType() != MVT::Other) ?
938 MakeReg(N.getValueType()) : 1;
940 // If this is a call instruction, make sure to prepare ALL of the result
941 // values as well as the chain.
942 if (Node->getNumValues() == 1)
943 Reg = Result = 1; // Void call, just a chain.
945 Result = MakeReg(Node->getValueType(0));
946 ExprMap[N.getValue(0)] = Result;
947 for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
948 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
949 ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
953 switch (N.getOpcode()) {
956 assert(0 && "Node not handled!\n");
958 case ISD::FrameIndex: {
959 Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
960 BuildMI(BB, IA64::MOV, 1, Result).addFrameIndex(Tmp1);
964 case ISD::ConstantPool: {
965 Tmp1 = BB->getParent()->getConstantPool()->
966 getConstantPoolIndex(cast<ConstantPoolSDNode>(N)->get());
967 IA64Lowering.restoreGP(BB); // FIXME: do i really need this?
968 BuildMI(BB, IA64::ADD, 2, Result).addConstantPoolIndex(Tmp1)
973 case ISD::ConstantFP: {
974 Tmp1 = Result; // Intermediate Register
975 if (cast<ConstantFPSDNode>(N)->getValue() < 0.0 ||
976 cast<ConstantFPSDNode>(N)->isExactlyValue(-0.0))
977 Tmp1 = MakeReg(MVT::f64);
979 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0) ||
980 cast<ConstantFPSDNode>(N)->isExactlyValue(-0.0))
981 BuildMI(BB, IA64::FMOV, 1, Tmp1).addReg(IA64::F0); // load 0.0
982 else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0) ||
983 cast<ConstantFPSDNode>(N)->isExactlyValue(-1.0))
984 BuildMI(BB, IA64::FMOV, 1, Tmp1).addReg(IA64::F1); // load 1.0
986 assert(0 && "Unexpected FP constant!");
988 // we multiply by +1.0, negate (this is FNMA), and then add 0.0
989 BuildMI(BB, IA64::FNMA, 3, Result).addReg(Tmp1).addReg(IA64::F1)
994 case ISD::DYNAMIC_STACKALLOC: {
995 // Generate both result values.
997 ExprMap[N.getValue(1)] = 1; // Generate the token
999 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1001 // FIXME: We are currently ignoring the requested alignment for handling
1002 // greater than the stack alignment. This will need to be revisited at some
1003 // point. Align = N.getOperand(2);
1005 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
1006 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
1007 std::cerr << "Cannot allocate stack object with greater alignment than"
1008 << " the stack alignment yet!";
1013 Select(N.getOperand(0));
1014 if (ConstantSDNode* CN = dyn_cast<ConstantSDNode>(N.getOperand(1)))
1016 if (CN->getValue() < 32000)
1018 BuildMI(BB, IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
1019 .addImm(-CN->getValue());
1021 Tmp1 = SelectExpr(N.getOperand(1));
1022 // Subtract size from stack pointer, thereby allocating some space.
1023 BuildMI(BB, IA64::SUB, 2, IA64::r12).addReg(IA64::r12).addReg(Tmp1);
1026 Tmp1 = SelectExpr(N.getOperand(1));
1027 // Subtract size from stack pointer, thereby allocating some space.
1028 BuildMI(BB, IA64::SUB, 2, IA64::r12).addReg(IA64::r12).addReg(Tmp1);
1031 Select(N.getOperand(0));
1032 Tmp1 = SelectExpr(N.getOperand(1));
1033 // Subtract size from stack pointer, thereby allocating some space.
1034 BuildMI(BB, IA64::SUB, 2, IA64::r12).addReg(IA64::r12).addReg(Tmp1);
1035 // Put a pointer to the space into the result register, by copying the
1037 BuildMI(BB, IA64::MOV, 1, Result).addReg(IA64::r12);
1042 Tmp1 = SelectExpr(N.getOperand(0)); //Cond
1043 Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
1044 Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
1046 unsigned bogoResult;
1048 switch (N.getOperand(1).getValueType()) {
1049 default: assert(0 &&
1050 "ISD::SELECT: 'select'ing something other than i1, i64 or f64!\n");
1051 // for i1, we load the condition into an integer register, then
1052 // conditionally copy Tmp2 and Tmp3 to Tmp1 in parallel (only one
1053 // of them will go through, since the integer register will hold
1056 bogoResult=MakeReg(MVT::i1);
1058 // load the condition into an integer register
1059 unsigned condReg=MakeReg(MVT::i64);
1060 unsigned dummy=MakeReg(MVT::i64);
1061 BuildMI(BB, IA64::MOV, 1, dummy).addReg(IA64::r0);
1062 BuildMI(BB, IA64::TPCADDIMM22, 2, condReg).addReg(dummy)
1063 .addImm(1).addReg(Tmp1);
1065 // initialize Result (bool) to false (hence UNC) and if
1066 // the select condition (condReg) is false (0), copy Tmp3
1067 BuildMI(BB, IA64::PCMPEQUNC, 3, bogoResult)
1068 .addReg(condReg).addReg(IA64::r0).addReg(Tmp3);
1070 // now, if the selection condition is true, write 1 to the
1071 // result if Tmp2 is 1
1072 BuildMI(BB, IA64::TPCMPNE, 3, Result).addReg(bogoResult)
1073 .addReg(condReg).addReg(IA64::r0).addReg(Tmp2);
1076 // for i64/f64, we just copy Tmp3 and then conditionally overwrite it
1077 // with Tmp2 if Tmp1 is true
1079 bogoResult=MakeReg(MVT::i64);
1080 BuildMI(BB, IA64::MOV, 1, bogoResult).addReg(Tmp3);
1081 BuildMI(BB, IA64::CMOV, 2, Result).addReg(bogoResult).addReg(Tmp2)
1085 bogoResult=MakeReg(MVT::f64);
1086 BuildMI(BB, IA64::FMOV, 1, bogoResult).addReg(Tmp3);
1087 BuildMI(BB, IA64::CFMOV, 2, Result).addReg(bogoResult).addReg(Tmp2)
1095 case ISD::Constant: {
1096 unsigned depositPos=0;
1097 unsigned depositLen=0;
1098 switch (N.getValueType()) {
1099 default: assert(0 && "Cannot use constants of this type!");
1100 case MVT::i1: { // if a bool, we don't 'load' so much as generate
1102 if(cast<ConstantSDNode>(N)->getValue()) // true:
1103 BuildMI(BB, IA64::CMPEQ, 2, Result).addReg(IA64::r0).addReg(IA64::r0);
1105 BuildMI(BB, IA64::CMPNE, 2, Result).addReg(IA64::r0).addReg(IA64::r0);
1106 return Result; // early exit
1108 case MVT::i64: break;
1111 int64_t immediate = cast<ConstantSDNode>(N)->getValue();
1113 if(immediate==0) { // if the constant is just zero,
1114 BuildMI(BB, IA64::MOV, 1, Result).addReg(IA64::r0); // just copy r0
1115 return Result; // early exit
1118 if (immediate <= 8191 && immediate >= -8192) {
1119 // if this constants fits in 14 bits, we use a mov the assembler will
1120 // turn into: "adds rDest=imm,r0" (and _not_ "andl"...)
1121 BuildMI(BB, IA64::MOVSIMM14, 1, Result).addSImm(immediate);
1122 return Result; // early exit
1125 if (immediate <= 2097151 && immediate >= -2097152) {
1126 // if this constants fits in 22 bits, we use a mov the assembler will
1127 // turn into: "addl rDest=imm,r0"
1128 BuildMI(BB, IA64::MOVSIMM22, 1, Result).addSImm(immediate);
1129 return Result; // early exit
1132 /* otherwise, our immediate is big, so we use movl */
1133 uint64_t Imm = immediate;
1134 BuildMI(BB, IA64::MOVLIMM64, 1, Result).addImm64(Imm);
1139 BuildMI(BB, IA64::IDEF, 0, Result);
1143 case ISD::GlobalAddress: {
1144 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
1145 unsigned Tmp1 = MakeReg(MVT::i64);
1147 BuildMI(BB, IA64::ADD, 2, Tmp1).addGlobalAddress(GV).addReg(IA64::r1);
1148 BuildMI(BB, IA64::LD8, 1, Result).addReg(Tmp1);
1153 case ISD::ExternalSymbol: {
1154 const char *Sym = cast<ExternalSymbolSDNode>(N)->getSymbol();
1155 // assert(0 && "sorry, but what did you want an ExternalSymbol for again?");
1156 BuildMI(BB, IA64::MOV, 1, Result).addExternalSymbol(Sym); // XXX
1160 case ISD::FP_EXTEND: {
1161 Tmp1 = SelectExpr(N.getOperand(0));
1162 BuildMI(BB, IA64::FMOV, 1, Result).addReg(Tmp1);
1166 case ISD::ANY_EXTEND:
1167 case ISD::ZERO_EXTEND: {
1168 Tmp1 = SelectExpr(N.getOperand(0)); // value
1170 assert(N.getOperand(0).getValueType() == MVT::i1 &&
1171 "Cannot zero-extend this type!");
1173 // if the predicate reg has 1, we want a '1' in our GR.
1174 unsigned dummy = MakeReg(MVT::i64);
1176 BuildMI(BB, IA64::MOV, 1, dummy).addReg(IA64::r0);
1177 // ...then conditionally (PR:Tmp1) add 1:
1178 BuildMI(BB, IA64::TPCADDIMM22, 2, Result).addReg(dummy)
1179 .addImm(1).addReg(Tmp1);
1180 return Result; // XXX early exit!
1183 case ISD::SIGN_EXTEND:
1184 assert(N.getOperand(0).getValueType() == MVT::i1 &&
1185 "Cannot zero-extend this type!");
1187 Tmp1 = SelectExpr(N.getOperand(0)); // value
1188 assert(0 && "don't know how to sign_extend from bool yet!");
1192 // we use the funky dep.z (deposit (zero)) instruction to deposit bits
1193 // of R0 appropriately.
1194 assert(N.getOperand(0).getValueType() == MVT::i64 &&
1195 N.getValueType() == MVT::i1 && "Unknown truncate!");
1196 Tmp1 = SelectExpr(N.getOperand(0));
1198 // if input (normal reg) is 0, 0!=0 -> false (0), if 1, 1!=0 ->true (1):
1199 BuildMI(BB, IA64::CMPNE, 2, Result).addReg(Tmp1).addReg(IA64::r0);
1200 return Result; // XXX early exit!
1203 case ISD::FP_ROUND: {
1204 assert (DestType == MVT::f32 && N.getOperand(0).getValueType() == MVT::f64 &&
1205 "error: trying to FP_ROUND something other than f64 -> f32!\n");
1206 Tmp1 = SelectExpr(N.getOperand(0));
1207 BuildMI(BB, IA64::FADDS, 2, Result).addReg(Tmp1).addReg(IA64::F0);
1208 // we add 0.0 using a single precision add to do rounding
1213 // FIXME: the following 4 cases need cleaning
1214 case ISD::SINT_TO_FP: {
1215 Tmp1 = SelectExpr(N.getOperand(0));
1216 Tmp2 = MakeReg(MVT::f64);
1217 unsigned dummy = MakeReg(MVT::f64);
1218 BuildMI(BB, IA64::SETFSIG, 1, Tmp2).addReg(Tmp1);
1219 BuildMI(BB, IA64::FCVTXF, 1, dummy).addReg(Tmp2);
1220 BuildMI(BB, IA64::FNORMD, 1, Result).addReg(dummy);
1224 case ISD::UINT_TO_FP: {
1225 Tmp1 = SelectExpr(N.getOperand(0));
1226 Tmp2 = MakeReg(MVT::f64);
1227 unsigned dummy = MakeReg(MVT::f64);
1228 BuildMI(BB, IA64::SETFSIG, 1, Tmp2).addReg(Tmp1);
1229 BuildMI(BB, IA64::FCVTXUF, 1, dummy).addReg(Tmp2);
1230 BuildMI(BB, IA64::FNORMD, 1, Result).addReg(dummy);
1234 case ISD::FP_TO_SINT: {
1235 Tmp1 = SelectExpr(N.getOperand(0));
1236 Tmp2 = MakeReg(MVT::f64);
1237 BuildMI(BB, IA64::FCVTFXTRUNC, 1, Tmp2).addReg(Tmp1);
1238 BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(Tmp2);
1242 case ISD::FP_TO_UINT: {
1243 Tmp1 = SelectExpr(N.getOperand(0));
1244 Tmp2 = MakeReg(MVT::f64);
1245 BuildMI(BB, IA64::FCVTFXUTRUNC, 1, Tmp2).addReg(Tmp1);
1246 BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(Tmp2);
1251 if (N.getOperand(0).getOpcode() == ISD::FMUL &&
1252 N.getOperand(0).Val->hasOneUse()) { // if we can fold this add
1253 // into an fma, do so:
1254 // ++FusedFP; // Statistic
1255 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1256 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1257 Tmp3 = SelectExpr(N.getOperand(1));
1258 BuildMI(BB, IA64::FMA, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1259 return Result; // early exit
1262 //else, fallthrough:
1263 Tmp1 = SelectExpr(N.getOperand(0));
1264 Tmp2 = SelectExpr(N.getOperand(1));
1265 BuildMI(BB, IA64::FADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
1270 if (N.getOperand(0).getOpcode() == ISD::SHL &&
1271 N.getOperand(0).Val->hasOneUse()) { // if we might be able to fold
1272 // this add into a shladd, try:
1273 ConstantSDNode *CSD = NULL;
1274 if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) &&
1275 (CSD->getValue() >= 1) && (CSD->getValue() <= 4) ) { // we can:
1277 // ++FusedSHLADD; // Statistic
1278 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1279 int shl_amt = CSD->getValue();
1280 Tmp3 = SelectExpr(N.getOperand(1));
1282 BuildMI(BB, IA64::SHLADD, 3, Result)
1283 .addReg(Tmp1).addImm(shl_amt).addReg(Tmp3);
1284 return Result; // early exit
1288 //else, fallthrough:
1289 Tmp1 = SelectExpr(N.getOperand(0));
1290 switch (ponderIntegerAdditionWith(N.getOperand(1), Tmp3)) {
1291 case 1: // adding a constant that's 14 bits
1292 BuildMI(BB, IA64::ADDIMM14, 2, Result).addReg(Tmp1).addSImm(Tmp3);
1293 return Result; // early exit
1294 } // fallthrough and emit a reg+reg ADD:
1295 Tmp2 = SelectExpr(N.getOperand(1));
1296 BuildMI(BB, IA64::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
1301 Tmp1 = SelectExpr(N.getOperand(0));
1302 Tmp2 = SelectExpr(N.getOperand(1));
1303 BuildMI(BB, IA64::FMPY, 2, Result).addReg(Tmp1).addReg(Tmp2);
1309 /* FIXME if(N.getOperand(1).getOpcode() != ISD::Constant) { // if not a const mul
1311 // boring old integer multiply with xma
1312 Tmp1 = SelectExpr(N.getOperand(0));
1313 Tmp2 = SelectExpr(N.getOperand(1));
1315 unsigned TempFR1=MakeReg(MVT::f64);
1316 unsigned TempFR2=MakeReg(MVT::f64);
1317 unsigned TempFR3=MakeReg(MVT::f64);
1318 BuildMI(BB, IA64::SETFSIG, 1, TempFR1).addReg(Tmp1);
1319 BuildMI(BB, IA64::SETFSIG, 1, TempFR2).addReg(Tmp2);
1320 BuildMI(BB, IA64::XMAL, 1, TempFR3).addReg(TempFR1).addReg(TempFR2)
1322 BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(TempFR3);
1323 return Result; // early exit
1324 /* FIXME } else { // we are multiplying by an integer constant! yay
1325 return Reg = SelectExpr(BuildConstmulSequence(N)); // avert your eyes!
1330 if(N.getOperand(0).getOpcode() == ISD::FMUL &&
1331 N.getOperand(0).Val->hasOneUse()) { // if we can fold this sub
1332 // into an fms, do so:
1333 // ++FusedFP; // Statistic
1334 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1335 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1336 Tmp3 = SelectExpr(N.getOperand(1));
1337 BuildMI(BB, IA64::FMS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1338 return Result; // early exit
1341 Tmp2 = SelectExpr(N.getOperand(1));
1342 Tmp1 = SelectExpr(N.getOperand(0));
1343 BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
1347 Tmp2 = SelectExpr(N.getOperand(1));
1348 switch (ponderIntegerSubtractionFrom(N.getOperand(0), Tmp3)) {
1349 case 1: // subtracting *from* an 8 bit constant:
1350 BuildMI(BB, IA64::SUBIMM8, 2, Result).addSImm(Tmp3).addReg(Tmp2);
1351 return Result; // early exit
1352 } // fallthrough and emit a reg+reg SUB:
1353 Tmp1 = SelectExpr(N.getOperand(0));
1354 BuildMI(BB, IA64::SUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
1359 Tmp1 = SelectExpr(N.getOperand(0));
1360 assert(DestType == MVT::f64 && "trying to fabs something other than f64?");
1361 BuildMI(BB, IA64::FABS, 1, Result).addReg(Tmp1);
1366 assert(DestType == MVT::f64 && "trying to fneg something other than f64?");
1368 if (ISD::FABS == N.getOperand(0).getOpcode()) { // && hasOneUse()?
1369 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1370 BuildMI(BB, IA64::FNEGABS, 1, Result).addReg(Tmp1); // fold in abs
1372 Tmp1 = SelectExpr(N.getOperand(0));
1373 BuildMI(BB, IA64::FNEG, 1, Result).addReg(Tmp1); // plain old fneg
1380 switch (N.getValueType()) {
1381 default: assert(0 && "Cannot AND this type!");
1382 case MVT::i1: { // if a bool, we emit a pseudocode AND
1383 unsigned pA = SelectExpr(N.getOperand(0));
1384 unsigned pB = SelectExpr(N.getOperand(1));
1386 /* our pseudocode for AND is:
1388 (pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
1389 cmp.eq pTemp,p0 = r0,r0 // pTemp = NOT pB
1391 (pB) cmp.ne pTemp,p0 = r0,r0
1393 (pTemp)cmp.ne pC,p0 = r0,r0 // if (NOT pB) pC = 0
1396 unsigned pTemp = MakeReg(MVT::i1);
1398 unsigned bogusTemp1 = MakeReg(MVT::i1);
1399 unsigned bogusTemp2 = MakeReg(MVT::i1);
1400 unsigned bogusTemp3 = MakeReg(MVT::i1);
1401 unsigned bogusTemp4 = MakeReg(MVT::i1);
1403 BuildMI(BB, IA64::PCMPEQUNC, 3, bogusTemp1)
1404 .addReg(IA64::r0).addReg(IA64::r0).addReg(pA);
1405 BuildMI(BB, IA64::CMPEQ, 2, bogusTemp2)
1406 .addReg(IA64::r0).addReg(IA64::r0);
1407 BuildMI(BB, IA64::TPCMPNE, 3, pTemp)
1408 .addReg(bogusTemp2).addReg(IA64::r0).addReg(IA64::r0).addReg(pB);
1409 BuildMI(BB, IA64::TPCMPNE, 3, Result)
1410 .addReg(bogusTemp1).addReg(IA64::r0).addReg(IA64::r0).addReg(pTemp);
1414 // if not a bool, we just AND away:
1419 Tmp1 = SelectExpr(N.getOperand(0));
1420 switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
1421 case 1: // ANDing a constant that is 2^n-1 for some n
1423 case 8: // if AND 0x00000000000000FF, be quaint and use zxt1
1424 BuildMI(BB, IA64::ZXT1, 1, Result).addReg(Tmp1);
1426 case 16: // if AND 0x000000000000FFFF, be quaint and use zxt2
1427 BuildMI(BB, IA64::ZXT2, 1, Result).addReg(Tmp1);
1429 case 32: // if AND 0x00000000FFFFFFFF, be quaint and use zxt4
1430 BuildMI(BB, IA64::ZXT4, 1, Result).addReg(Tmp1);
1432 default: // otherwise, use dep.z to paste zeros
1433 // FIXME: assert the dep.z is in bounds
1434 BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
1435 .addImm(0).addImm(Tmp3);
1438 return Result; // early exit
1439 } // fallthrough and emit a simple AND:
1440 Tmp2 = SelectExpr(N.getOperand(1));
1441 BuildMI(BB, IA64::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
1448 switch (N.getValueType()) {
1449 default: assert(0 && "Cannot OR this type!");
1450 case MVT::i1: { // if a bool, we emit a pseudocode OR
1451 unsigned pA = SelectExpr(N.getOperand(0));
1452 unsigned pB = SelectExpr(N.getOperand(1));
1454 unsigned pTemp1 = MakeReg(MVT::i1);
1456 /* our pseudocode for OR is:
1462 (pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
1464 (pB) cmp.eq pC,p0 = r0,r0 // if (pB) pC = 1
1467 BuildMI(BB, IA64::PCMPEQUNC, 3, pTemp1)
1468 .addReg(IA64::r0).addReg(IA64::r0).addReg(pA);
1469 BuildMI(BB, IA64::TPCMPEQ, 4, Result)
1470 .addReg(pTemp1).addReg(IA64::r0).addReg(IA64::r0).addReg(pB);
1473 // if not a bool, we just OR away:
1478 Tmp1 = SelectExpr(N.getOperand(0));
1479 Tmp2 = SelectExpr(N.getOperand(1));
1480 BuildMI(BB, IA64::OR, 2, Result).addReg(Tmp1).addReg(Tmp2);
1488 switch (N.getValueType()) {
1489 default: assert(0 && "Cannot XOR this type!");
1490 case MVT::i1: { // if a bool, we emit a pseudocode XOR
1491 unsigned pY = SelectExpr(N.getOperand(0));
1492 unsigned pZ = SelectExpr(N.getOperand(1));
1494 /* one possible routine for XOR is:
1496 // Compute px = py ^ pz
1497 // using sum of products: px = (py & !pz) | (pz & !py)
1498 // Uses 5 instructions in 3 cycles.
1500 (pz) cmp.eq.unc px = r0, r0 // px = pz
1501 (py) cmp.eq.unc pt = r0, r0 // pt = py
1504 (pt) cmp.ne.and px = r0, r0 // px = px & !pt (px = pz & !pt)
1505 (pz) cmp.ne.and pt = r0, r0 // pt = pt & !pz
1509 (pt) cmp.eq.or px = r0, r0 // px = px | pt
1511 *** Another, which we use here, requires one scratch GR. it is:
1513 mov rt = 0 // initialize rt off critical path
1517 (pz) cmp.eq.unc px = r0, r0 // px = pz
1518 (pz) mov rt = 1 // rt = pz
1521 (py) cmp.ne px = 1, rt // if (py) px = !pz
1523 .. these routines kindly provided by Jim Hull
1525 unsigned rt = MakeReg(MVT::i64);
1527 // these two temporaries will never actually appear,
1528 // due to the two-address form of some of the instructions below
1529 unsigned bogoPR = MakeReg(MVT::i1); // becomes Result
1530 unsigned bogoGR = MakeReg(MVT::i64); // becomes rt
1532 BuildMI(BB, IA64::MOV, 1, bogoGR).addReg(IA64::r0);
1533 BuildMI(BB, IA64::PCMPEQUNC, 3, bogoPR)
1534 .addReg(IA64::r0).addReg(IA64::r0).addReg(pZ);
1535 BuildMI(BB, IA64::TPCADDIMM22, 2, rt)
1536 .addReg(bogoGR).addImm(1).addReg(pZ);
1537 BuildMI(BB, IA64::TPCMPIMM8NE, 3, Result)
1538 .addReg(bogoPR).addImm(1).addReg(rt).addReg(pY);
1541 // if not a bool, we just XOR away:
1546 Tmp1 = SelectExpr(N.getOperand(0));
1547 Tmp2 = SelectExpr(N.getOperand(1));
1548 BuildMI(BB, IA64::XOR, 2, Result).addReg(Tmp1).addReg(Tmp2);
1556 Tmp1 = SelectExpr(N.getOperand(0));
1557 BuildMI(BB, IA64::POPCNT, 1, Result).addReg(Tmp1);
1562 Tmp1 = SelectExpr(N.getOperand(0));
1563 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1564 Tmp2 = CN->getValue();
1565 BuildMI(BB, IA64::SHLI, 2, Result).addReg(Tmp1).addImm(Tmp2);
1567 Tmp2 = SelectExpr(N.getOperand(1));
1568 BuildMI(BB, IA64::SHL, 2, Result).addReg(Tmp1).addReg(Tmp2);
1574 Tmp1 = SelectExpr(N.getOperand(0));
1575 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1576 Tmp2 = CN->getValue();
1577 BuildMI(BB, IA64::SHRUI, 2, Result).addReg(Tmp1).addImm(Tmp2);
1579 Tmp2 = SelectExpr(N.getOperand(1));
1580 BuildMI(BB, IA64::SHRU, 2, Result).addReg(Tmp1).addReg(Tmp2);
1586 Tmp1 = SelectExpr(N.getOperand(0));
1587 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1588 Tmp2 = CN->getValue();
1589 BuildMI(BB, IA64::SHRSI, 2, Result).addReg(Tmp1).addImm(Tmp2);
1591 Tmp2 = SelectExpr(N.getOperand(1));
1592 BuildMI(BB, IA64::SHRS, 2, Result).addReg(Tmp1).addReg(Tmp2);
1603 Tmp1 = SelectExpr(N.getOperand(0));
1604 Tmp2 = SelectExpr(N.getOperand(1));
1608 if(DestType == MVT::f64) // XXX: we're not gonna be fed MVT::f32, are we?
1611 bool isModulus=false; // is it a division or a modulus?
1612 bool isSigned=false;
1614 switch(N.getOpcode()) {
1616 case ISD::SDIV: isModulus=false; isSigned=true; break;
1617 case ISD::UDIV: isModulus=false; isSigned=false; break;
1619 case ISD::SREM: isModulus=true; isSigned=true; break;
1620 case ISD::UREM: isModulus=true; isSigned=false; break;
1623 if(!isModulus && !isFP) { // if this is an integer divide,
1624 switch (ponderIntegerDivisionBy(N.getOperand(1), isSigned, Tmp3)) {
1625 case 1: // division by a constant that's a power of 2
1626 Tmp1 = SelectExpr(N.getOperand(0));
1627 if(isSigned) { // argument could be negative, so emit some code:
1628 unsigned divAmt=Tmp3;
1629 unsigned tempGR1=MakeReg(MVT::i64);
1630 unsigned tempGR2=MakeReg(MVT::i64);
1631 unsigned tempGR3=MakeReg(MVT::i64);
1632 BuildMI(BB, IA64::SHRS, 2, tempGR1)
1633 .addReg(Tmp1).addImm(divAmt-1);
1634 BuildMI(BB, IA64::EXTRU, 3, tempGR2)
1635 .addReg(tempGR1).addImm(64-divAmt).addImm(divAmt);
1636 BuildMI(BB, IA64::ADD, 2, tempGR3)
1637 .addReg(Tmp1).addReg(tempGR2);
1638 BuildMI(BB, IA64::SHRS, 2, Result)
1639 .addReg(tempGR3).addImm(divAmt);
1641 else // unsigned div-by-power-of-2 becomes a simple shift right:
1642 BuildMI(BB, IA64::SHRU, 2, Result).addReg(Tmp1).addImm(Tmp3);
1643 return Result; // early exit
1647 unsigned TmpPR=MakeReg(MVT::i1); // we need two scratch
1648 unsigned TmpPR2=MakeReg(MVT::i1); // predicate registers,
1649 unsigned TmpF1=MakeReg(MVT::f64); // and one metric truckload of FP regs.
1650 unsigned TmpF2=MakeReg(MVT::f64); // lucky we have IA64?
1651 unsigned TmpF3=MakeReg(MVT::f64); // well, the real FIXME is to have
1652 unsigned TmpF4=MakeReg(MVT::f64); // isTwoAddress forms of these
1653 unsigned TmpF5=MakeReg(MVT::f64); // FP instructions so we can end up with
1654 unsigned TmpF6=MakeReg(MVT::f64); // stuff like setf.sig f10=f10 etc.
1655 unsigned TmpF7=MakeReg(MVT::f64);
1656 unsigned TmpF8=MakeReg(MVT::f64);
1657 unsigned TmpF9=MakeReg(MVT::f64);
1658 unsigned TmpF10=MakeReg(MVT::f64);
1659 unsigned TmpF11=MakeReg(MVT::f64);
1660 unsigned TmpF12=MakeReg(MVT::f64);
1661 unsigned TmpF13=MakeReg(MVT::f64);
1662 unsigned TmpF14=MakeReg(MVT::f64);
1663 unsigned TmpF15=MakeReg(MVT::f64);
1665 // OK, emit some code:
1668 // first, load the inputs into FP regs.
1669 BuildMI(BB, IA64::SETFSIG, 1, TmpF1).addReg(Tmp1);
1670 BuildMI(BB, IA64::SETFSIG, 1, TmpF2).addReg(Tmp2);
1672 // next, convert the inputs to FP
1674 BuildMI(BB, IA64::FCVTXF, 1, TmpF3).addReg(TmpF1);
1675 BuildMI(BB, IA64::FCVTXF, 1, TmpF4).addReg(TmpF2);
1677 BuildMI(BB, IA64::FCVTXUFS1, 1, TmpF3).addReg(TmpF1);
1678 BuildMI(BB, IA64::FCVTXUFS1, 1, TmpF4).addReg(TmpF2);
1681 } else { // this is an FP divide/remainder, so we 'leak' some temp
1682 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
1687 // we start by computing an approximate reciprocal (good to 9 bits?)
1688 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
1689 BuildMI(BB, IA64::FRCPAS1, 4)
1690 .addReg(TmpF5, MachineOperand::Def)
1691 .addReg(TmpPR, MachineOperand::Def)
1692 .addReg(TmpF3).addReg(TmpF4);
1694 if(!isModulus) { // if this is a divide, we worry about div-by-zero
1695 unsigned bogusPR=MakeReg(MVT::i1); // won't appear, due to twoAddress
1697 BuildMI(BB, IA64::CMPEQ, 2, bogusPR).addReg(IA64::r0).addReg(IA64::r0);
1698 BuildMI(BB, IA64::TPCMPNE, 3, TmpPR2).addReg(bogusPR)
1699 .addReg(IA64::r0).addReg(IA64::r0).addReg(TmpPR);
1702 // now we apply newton's method, thrice! (FIXME: this is ~72 bits of
1703 // precision, don't need this much for f32/i32)
1704 BuildMI(BB, IA64::CFNMAS1, 4, TmpF6)
1705 .addReg(TmpF4).addReg(TmpF5).addReg(IA64::F1).addReg(TmpPR);
1706 BuildMI(BB, IA64::CFMAS1, 4, TmpF7)
1707 .addReg(TmpF3).addReg(TmpF5).addReg(IA64::F0).addReg(TmpPR);
1708 BuildMI(BB, IA64::CFMAS1, 4, TmpF8)
1709 .addReg(TmpF6).addReg(TmpF6).addReg(IA64::F0).addReg(TmpPR);
1710 BuildMI(BB, IA64::CFMAS1, 4, TmpF9)
1711 .addReg(TmpF6).addReg(TmpF7).addReg(TmpF7).addReg(TmpPR);
1712 BuildMI(BB, IA64::CFMAS1, 4,TmpF10)
1713 .addReg(TmpF6).addReg(TmpF5).addReg(TmpF5).addReg(TmpPR);
1714 BuildMI(BB, IA64::CFMAS1, 4,TmpF11)
1715 .addReg(TmpF8).addReg(TmpF9).addReg(TmpF9).addReg(TmpPR);
1716 BuildMI(BB, IA64::CFMAS1, 4,TmpF12)
1717 .addReg(TmpF8).addReg(TmpF10).addReg(TmpF10).addReg(TmpPR);
1718 BuildMI(BB, IA64::CFNMAS1, 4,TmpF13)
1719 .addReg(TmpF4).addReg(TmpF11).addReg(TmpF3).addReg(TmpPR);
1721 // FIXME: this is unfortunate :(
1722 // the story is that the dest reg of the fnma above and the fma below
1723 // (and therefore possibly the src of the fcvt.fx[u] as well) cannot
1724 // be the same register, or this code breaks if the first argument is
1725 // zero. (e.g. without this hack, 0%8 yields -64, not 0.)
1726 BuildMI(BB, IA64::CFMAS1, 4,TmpF14)
1727 .addReg(TmpF13).addReg(TmpF12).addReg(TmpF11).addReg(TmpPR);
1729 if(isModulus) { // XXX: fragile! fixes _only_ mod, *breaks* div! !
1730 BuildMI(BB, IA64::IUSE, 1).addReg(TmpF13); // hack :(
1734 // round to an integer
1736 BuildMI(BB, IA64::FCVTFXTRUNCS1, 1, TmpF15).addReg(TmpF14);
1738 BuildMI(BB, IA64::FCVTFXUTRUNCS1, 1, TmpF15).addReg(TmpF14);
1740 BuildMI(BB, IA64::FMOV, 1, TmpF15).addReg(TmpF14);
1741 // EXERCISE: can you see why TmpF15=TmpF14 does not work here, and
1742 // we really do need the above FMOV? ;)
1746 if(isFP) { // extra worrying about div-by-zero
1747 unsigned bogoResult=MakeReg(MVT::f64);
1749 // we do a 'conditional fmov' (of the correct result, depending
1750 // on how the frcpa predicate turned out)
1751 BuildMI(BB, IA64::PFMOV, 2, bogoResult)
1752 .addReg(TmpF12).addReg(TmpPR2);
1753 BuildMI(BB, IA64::CFMOV, 2, Result)
1754 .addReg(bogoResult).addReg(TmpF15).addReg(TmpPR);
1757 BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(TmpF15);
1759 } else { // this is a modulus
1761 // answer = q * (-b) + a
1762 unsigned ModulusResult = MakeReg(MVT::f64);
1763 unsigned TmpF = MakeReg(MVT::f64);
1764 unsigned TmpI = MakeReg(MVT::i64);
1766 BuildMI(BB, IA64::SUB, 2, TmpI).addReg(IA64::r0).addReg(Tmp2);
1767 BuildMI(BB, IA64::SETFSIG, 1, TmpF).addReg(TmpI);
1768 BuildMI(BB, IA64::XMAL, 3, ModulusResult)
1769 .addReg(TmpF15).addReg(TmpF).addReg(TmpF1);
1770 BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(ModulusResult);
1771 } else { // FP modulus! The horror... the horror....
1772 assert(0 && "sorry, no FP modulus just yet!\n!\n");
1779 case ISD::SIGN_EXTEND_INREG: {
1780 Tmp1 = SelectExpr(N.getOperand(0));
1781 switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) {
1784 assert(0 && "don't know how to sign extend this type");
1786 case MVT::i8: Opc = IA64::SXT1; break;
1787 case MVT::i16: Opc = IA64::SXT2; break;
1788 case MVT::i32: Opc = IA64::SXT4; break;
1790 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
1795 Tmp1 = SelectExpr(N.getOperand(0));
1796 ISD::CondCode CC = cast<CondCodeSDNode>(Node->getOperand(2))->get();
1797 if (MVT::isInteger(N.getOperand(0).getValueType())) {
1799 if(ConstantSDNode *CSDN =
1800 dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1801 // if we are comparing against a constant zero
1802 if(CSDN->getValue()==0)
1803 Tmp2 = IA64::r0; // then we can just compare against r0
1805 Tmp2 = SelectExpr(N.getOperand(1));
1806 } else // not comparing against a constant
1807 Tmp2 = SelectExpr(N.getOperand(1));
1810 default: assert(0 && "Unknown integer comparison!");
1812 BuildMI(BB, IA64::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
1815 BuildMI(BB, IA64::CMPGT, 2, Result).addReg(Tmp1).addReg(Tmp2);
1818 BuildMI(BB, IA64::CMPGE, 2, Result).addReg(Tmp1).addReg(Tmp2);
1821 BuildMI(BB, IA64::CMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
1824 BuildMI(BB, IA64::CMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
1827 BuildMI(BB, IA64::CMPNE, 2, Result).addReg(Tmp1).addReg(Tmp2);
1830 BuildMI(BB, IA64::CMPLTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
1833 BuildMI(BB, IA64::CMPGTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
1836 BuildMI(BB, IA64::CMPLEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
1839 BuildMI(BB, IA64::CMPGEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
1842 } else { // if not integer, should be FP.
1843 assert(N.getOperand(0).getValueType() != MVT::f32 &&
1844 "error: SETCC should have had incoming f32 promoted to f64!\n");
1846 if(ConstantFPSDNode *CFPSDN =
1847 dyn_cast<ConstantFPSDNode>(N.getOperand(1))) {
1849 // if we are comparing against a constant +0.0 or +1.0
1850 if(CFPSDN->isExactlyValue(+0.0))
1851 Tmp2 = IA64::F0; // then we can just compare against f0
1852 else if(CFPSDN->isExactlyValue(+1.0))
1853 Tmp2 = IA64::F1; // or f1
1855 Tmp2 = SelectExpr(N.getOperand(1));
1856 } else // not comparing against a constant
1857 Tmp2 = SelectExpr(N.getOperand(1));
1860 default: assert(0 && "Unknown FP comparison!");
1862 BuildMI(BB, IA64::FCMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
1865 BuildMI(BB, IA64::FCMPGT, 2, Result).addReg(Tmp1).addReg(Tmp2);
1868 BuildMI(BB, IA64::FCMPGE, 2, Result).addReg(Tmp1).addReg(Tmp2);
1871 BuildMI(BB, IA64::FCMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
1874 BuildMI(BB, IA64::FCMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
1877 BuildMI(BB, IA64::FCMPNE, 2, Result).addReg(Tmp1).addReg(Tmp2);
1880 BuildMI(BB, IA64::FCMPLTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
1883 BuildMI(BB, IA64::FCMPGTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
1886 BuildMI(BB, IA64::FCMPLEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
1889 BuildMI(BB, IA64::FCMPGEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
1899 // Make sure we generate both values.
1901 ExprMap[N.getValue(1)] = 1; // Generate the token
1903 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1907 if(opcode == ISD::LOAD) { // this is a LOAD
1908 switch (Node->getValueType(0)) {
1909 default: assert(0 && "Cannot load this type!");
1910 case MVT::i1: Opc = IA64::LD1; isBool=true; break;
1911 // FIXME: for now, we treat bool loads the same as i8 loads */
1912 case MVT::i8: Opc = IA64::LD1; break;
1913 case MVT::i16: Opc = IA64::LD2; break;
1914 case MVT::i32: Opc = IA64::LD4; break;
1915 case MVT::i64: Opc = IA64::LD8; break;
1917 case MVT::f32: Opc = IA64::LDF4; break;
1918 case MVT::f64: Opc = IA64::LDF8; break;
1920 } else { // this is an EXTLOAD or ZEXTLOAD
1921 MVT::ValueType TypeBeingLoaded =
1922 cast<VTSDNode>(Node->getOperand(3))->getVT();
1923 switch (TypeBeingLoaded) {
1924 default: assert(0 && "Cannot extload/zextload this type!");
1926 case MVT::i8: Opc = IA64::LD1; break;
1927 case MVT::i16: Opc = IA64::LD2; break;
1928 case MVT::i32: Opc = IA64::LD4; break;
1929 case MVT::f32: Opc = IA64::LDF4; break;
1933 SDOperand Chain = N.getOperand(0);
1934 SDOperand Address = N.getOperand(1);
1936 if(Address.getOpcode() == ISD::GlobalAddress) {
1938 unsigned dummy = MakeReg(MVT::i64);
1939 unsigned dummy2 = MakeReg(MVT::i64);
1940 BuildMI(BB, IA64::ADD, 2, dummy)
1941 .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal())
1943 BuildMI(BB, IA64::LD8, 1, dummy2).addReg(dummy);
1945 BuildMI(BB, Opc, 1, Result).addReg(dummy2);
1946 else { // emit a little pseudocode to load a bool (stored in one byte)
1947 // into a predicate register
1948 assert(Opc==IA64::LD1 && "problem loading a bool");
1949 unsigned dummy3 = MakeReg(MVT::i64);
1950 BuildMI(BB, Opc, 1, dummy3).addReg(dummy2);
1951 // we compare to 0. true? 0. false? 1.
1952 BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy3).addReg(IA64::r0);
1954 } else if(ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
1955 unsigned CPIdx = BB->getParent()->getConstantPool()->
1956 getConstantPoolIndex(CP->get());
1958 IA64Lowering.restoreGP(BB);
1959 unsigned dummy = MakeReg(MVT::i64);
1960 unsigned dummy2 = MakeReg(MVT::i64);
1961 BuildMI(BB, IA64::MOVLIMM64, 1, dummy2).addConstantPoolIndex(CPIdx);
1962 BuildMI(BB, IA64::ADD, 2, dummy).addReg(dummy2).addReg(IA64::r1); //CPI+GP
1965 // OLD BuildMI(BB, IA64::ADD, 2, dummy).addConstantPoolIndex(CPIdx)
1966 // (FIXME!) .addReg(IA64::r1); // CPI+GP
1968 BuildMI(BB, Opc, 1, Result).addReg(dummy);
1969 else { // emit a little pseudocode to load a bool (stored in one byte)
1970 // into a predicate register
1971 assert(Opc==IA64::LD1 && "problem loading a bool");
1972 unsigned dummy3 = MakeReg(MVT::i64);
1973 BuildMI(BB, Opc, 1, dummy3).addReg(dummy);
1974 // we compare to 0. true? 0. false? 1.
1975 BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy3).addReg(IA64::r0);
1977 } else if(Address.getOpcode() == ISD::FrameIndex) {
1978 Select(Chain); // FIXME ? what about bools?
1979 unsigned dummy = MakeReg(MVT::i64);
1980 BuildMI(BB, IA64::MOV, 1, dummy)
1981 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex());
1983 BuildMI(BB, Opc, 1, Result).addReg(dummy);
1984 else { // emit a little pseudocode to load a bool (stored in one byte)
1985 // into a predicate register
1986 assert(Opc==IA64::LD1 && "problem loading a bool");
1987 unsigned dummy3 = MakeReg(MVT::i64);
1988 BuildMI(BB, Opc, 1, dummy3).addReg(dummy);
1989 // we compare to 0. true? 0. false? 1.
1990 BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy3).addReg(IA64::r0);
1992 } else { // none of the above...
1994 Tmp2 = SelectExpr(Address);
1996 BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
1997 else { // emit a little pseudocode to load a bool (stored in one byte)
1998 // into a predicate register
1999 assert(Opc==IA64::LD1 && "problem loading a bool");
2000 unsigned dummy = MakeReg(MVT::i64);
2001 BuildMI(BB, Opc, 1, dummy).addReg(Tmp2);
2002 // we compare to 0. true? 0. false? 1.
2003 BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy).addReg(IA64::r0);
2010 case ISD::CopyFromReg: {
2012 Result = ExprMap[N.getValue(0)] =
2013 MakeReg(N.getValue(0).getValueType());
2015 SDOperand Chain = N.getOperand(0);
2018 unsigned r = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
2020 if(N.getValueType() == MVT::i1) // if a bool, we use pseudocode
2021 BuildMI(BB, IA64::PCMPEQUNC, 3, Result)
2022 .addReg(IA64::r0).addReg(IA64::r0).addReg(r);
2023 // (r) Result =cmp.eq.unc(r0,r0)
2025 BuildMI(BB, IA64::MOV, 1, Result).addReg(r); // otherwise MOV
2031 Select(N.getOperand(0));
2033 // The chain for this call is now lowered.
2034 ExprMap.insert(std::make_pair(N.getValue(Node->getNumValues()-1), 1));
2036 //grab the arguments
2037 std::vector<unsigned> argvregs;
2039 for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
2040 argvregs.push_back(SelectExpr(N.getOperand(i)));
2042 // see section 8.5.8 of "Itanium Software Conventions and
2043 // Runtime Architecture Guide to see some examples of what's going
2044 // on here. (in short: int args get mapped 1:1 'slot-wise' to out0->out7,
2045 // while FP args get mapped to F8->F15 as needed)
2047 unsigned used_FPArgs=0; // how many FP Args have been used so far?
2050 for(int i = 0, e = std::min(8, (int)argvregs.size()); i < e; ++i)
2052 unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
2053 IA64::out4, IA64::out5, IA64::out6, IA64::out7 };
2054 unsigned FPArgs[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
2055 IA64::F12, IA64::F13, IA64::F14, IA64::F15 };
2057 switch(N.getOperand(i+2).getValueType())
2059 default: // XXX do we need to support MVT::i1 here?
2061 N.getOperand(i).Val->dump();
2062 std::cerr << "Type for " << i << " is: " <<
2063 N.getOperand(i+2).getValueType() << std::endl;
2064 assert(0 && "Unknown value type for call");
2066 BuildMI(BB, IA64::MOV, 1, intArgs[i]).addReg(argvregs[i]);
2069 BuildMI(BB, IA64::FMOV, 1, FPArgs[used_FPArgs++])
2070 .addReg(argvregs[i]);
2071 // FIXME: we don't need to do this _all_ the time:
2072 BuildMI(BB, IA64::GETFD, 1, intArgs[i]).addReg(argvregs[i]);
2078 for (int i = 8, e = argvregs.size(); i < e; ++i)
2080 unsigned tempAddr = MakeReg(MVT::i64);
2082 switch(N.getOperand(i+2).getValueType()) {
2085 N.getOperand(i).Val->dump();
2086 std::cerr << "Type for " << i << " is: " <<
2087 N.getOperand(i+2).getValueType() << "\n";
2088 assert(0 && "Unknown value type for call");
2089 case MVT::i1: // FIXME?
2094 BuildMI(BB, IA64::ADDIMM22, 2, tempAddr)
2095 .addReg(IA64::r12).addImm(16 + (i - 8) * 8); // r12 is SP
2096 BuildMI(BB, IA64::ST8, 2).addReg(tempAddr).addReg(argvregs[i]);
2100 BuildMI(BB, IA64::ADDIMM22, 2, tempAddr)
2101 .addReg(IA64::r12).addImm(16 + (i - 8) * 8); // r12 is SP
2102 BuildMI(BB, IA64::STF8, 2).addReg(tempAddr).addReg(argvregs[i]);
2107 // build the right kind of call. if we can branch directly, do so:
2108 if (GlobalAddressSDNode *GASD =
2109 dyn_cast<GlobalAddressSDNode>(N.getOperand(1)))
2111 BuildMI(BB, IA64::BRCALL, 1).addGlobalAddress(GASD->getGlobal(),true);
2112 IA64Lowering.restoreGP_SP_RP(BB);
2114 if (ExternalSymbolSDNode *ESSDN =
2115 dyn_cast<ExternalSymbolSDNode>(N.getOperand(1)))
2116 { // FIXME : currently need this case for correctness, to avoid
2117 // "non-pic code with imm relocation against dynamic symbol" errors
2118 BuildMI(BB, IA64::BRCALL, 1)
2119 .addExternalSymbol(ESSDN->getSymbol(), true);
2120 IA64Lowering.restoreGP_SP_RP(BB);
2122 else { // otherwise we need to get the function descriptor
2123 // load the branch target (function)'s entry point and
2125 Tmp1 = SelectExpr(N.getOperand(1));
2127 unsigned targetEntryPoint=MakeReg(MVT::i64);
2128 unsigned targetGPAddr=MakeReg(MVT::i64);
2129 unsigned currentGP=MakeReg(MVT::i64);
2131 // b6 is a scratch branch register, we load the target entry point
2132 // from the base of the function descriptor
2133 BuildMI(BB, IA64::LD8, 1, targetEntryPoint).addReg(Tmp1);
2134 BuildMI(BB, IA64::MOV, 1, IA64::B6).addReg(targetEntryPoint);
2136 // save the current GP:
2137 BuildMI(BB, IA64::MOV, 1, currentGP).addReg(IA64::r1);
2139 /* TODO: we need to make sure doing this never, ever loads a
2140 * bogus value into r1 (GP). */
2141 // load the target GP (which is at mem[functiondescriptor+8])
2142 BuildMI(BB, IA64::ADDIMM22, 2, targetGPAddr)
2143 .addReg(Tmp1).addImm(8); // FIXME: addimm22? why not postincrement ld
2144 BuildMI(BB, IA64::LD8, 1, IA64::r1).addReg(targetGPAddr);
2146 // and then jump: (well, call)
2147 BuildMI(BB, IA64::BRCALL, 1).addReg(IA64::B6);
2148 // and finally restore the old GP
2149 BuildMI(BB, IA64::MOV, 1, IA64::r1).addReg(currentGP);
2150 IA64Lowering.restoreSP_RP(BB);
2153 switch (Node->getValueType(0)) {
2154 default: assert(0 && "Unknown value type for call result!");
2155 case MVT::Other: return 1;
2157 BuildMI(BB, IA64::CMPNE, 2, Result)
2158 .addReg(IA64::r8).addReg(IA64::r0);
2164 BuildMI(BB, IA64::MOV, 1, Result).addReg(IA64::r8);
2167 BuildMI(BB, IA64::FMOV, 1, Result).addReg(IA64::F8);
2170 return Result+N.ResNo;
2177 void ISel::Select(SDOperand N) {
2178 unsigned Tmp1, Tmp2, Opc;
2179 unsigned opcode = N.getOpcode();
2181 if (!LoweredTokens.insert(N).second)
2182 return; // Already selected.
2184 SDNode *Node = N.Val;
2186 switch (Node->getOpcode()) {
2188 Node->dump(); std::cerr << "\n";
2189 assert(0 && "Node not handled yet!");
2191 case ISD::EntryToken: return; // Noop
2193 case ISD::TokenFactor: {
2194 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
2195 Select(Node->getOperand(i));
2199 case ISD::CopyToReg: {
2200 Select(N.getOperand(0));
2201 Tmp1 = SelectExpr(N.getOperand(2));
2202 Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
2205 // if a bool, we use pseudocode
2206 if (N.getOperand(2).getValueType() == MVT::i1)
2207 BuildMI(BB, IA64::PCMPEQUNC, 3, Tmp2)
2208 .addReg(IA64::r0).addReg(IA64::r0).addReg(Tmp1);
2209 // (Tmp1) Tmp2 = cmp.eq.unc(r0,r0)
2211 BuildMI(BB, IA64::MOV, 1, Tmp2).addReg(Tmp1);
2212 // XXX is this the right way 'round? ;)
2213 // FIXME: WHAT ABOUT FLOATING POINT?
2220 /* what the heck is going on here:
2222 <_sabre_> ret with two operands is obvious: chain and value
2224 <_sabre_> ret with 3 values happens when 'expansion' occurs
2225 <_sabre_> e.g. i64 gets split into 2x i32
2227 <_sabre_> you don't have this case on ia64
2229 <_sabre_> so the two returned values go into EAX/EDX on ia32
2230 <camel_> ahhh *memories*
2232 <camel_> ok, thanks :)
2233 <_sabre_> so yeah, everything that has a side effect takes a 'token chain'
2234 <_sabre_> this is the first operand always
2235 <_sabre_> these operand often define chains, they are the last operand
2236 <_sabre_> they are printed as 'ch' if you do DAG.dump()
2239 switch (N.getNumOperands()) {
2241 assert(0 && "Unknown return instruction!");
2243 Select(N.getOperand(0));
2244 Tmp1 = SelectExpr(N.getOperand(1));
2245 switch (N.getOperand(1).getValueType()) {
2246 default: assert(0 && "All other types should have been promoted!!");
2247 // FIXME: do I need to add support for bools here?
2248 // (return '0' or '1' r8, basically...)
2250 // FIXME: need to round floats - 80 bits is bad, the tester
2253 // we mark r8 as live on exit up above in LowerArguments()
2254 BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
2257 // we mark F8 as live on exit up above in LowerArguments()
2258 BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
2262 Select(N.getOperand(0));
2265 // before returning, restore the ar.pfs register (set by the 'alloc' up top)
2266 BuildMI(BB, IA64::MOV, 1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
2267 BuildMI(BB, IA64::RET, 0); // and then just emit a 'ret' instruction
2272 Select(N.getOperand(0));
2273 MachineBasicBlock *Dest =
2274 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
2275 BuildMI(BB, IA64::BRLCOND_NOTCALL, 1).addReg(IA64::p0).addMBB(Dest);
2276 // XXX HACK! we do _not_ need long branches all the time
2280 case ISD::ImplicitDef: {
2281 Select(N.getOperand(0));
2282 BuildMI(BB, IA64::IDEF, 0,
2283 cast<RegisterSDNode>(N.getOperand(1))->getReg());
2288 MachineBasicBlock *Dest =
2289 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
2291 Select(N.getOperand(0));
2292 Tmp1 = SelectExpr(N.getOperand(1));
2293 BuildMI(BB, IA64::BRLCOND_NOTCALL, 1).addReg(Tmp1).addMBB(Dest);
2294 // XXX HACK! we do _not_ need long branches all the time
2304 case ISD::CopyFromReg:
2305 case ISD::DYNAMIC_STACKALLOC:
2309 case ISD::TRUNCSTORE:
2311 Select(N.getOperand(0));
2312 Tmp1 = SelectExpr(N.getOperand(1)); // value
2316 if(opcode == ISD::STORE) {
2317 switch (N.getOperand(1).getValueType()) {
2318 default: assert(0 && "Cannot store this type!");
2319 case MVT::i1: Opc = IA64::ST1; isBool=true; break;
2320 // FIXME?: for now, we treat bool loads the same as i8 stores */
2321 case MVT::i8: Opc = IA64::ST1; break;
2322 case MVT::i16: Opc = IA64::ST2; break;
2323 case MVT::i32: Opc = IA64::ST4; break;
2324 case MVT::i64: Opc = IA64::ST8; break;
2326 case MVT::f32: Opc = IA64::STF4; break;
2327 case MVT::f64: Opc = IA64::STF8; break;
2329 } else { // truncstore
2330 switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
2331 default: assert(0 && "unknown type in truncstore");
2332 case MVT::i1: Opc = IA64::ST1; isBool=true; break;
2333 //FIXME: DAG does not promote this load?
2334 case MVT::i8: Opc = IA64::ST1; break;
2335 case MVT::i16: Opc = IA64::ST2; break;
2336 case MVT::i32: Opc = IA64::ST4; break;
2337 case MVT::f32: Opc = IA64::STF4; break;
2341 if(N.getOperand(2).getOpcode() == ISD::GlobalAddress) {
2342 unsigned dummy = MakeReg(MVT::i64);
2343 unsigned dummy2 = MakeReg(MVT::i64);
2344 BuildMI(BB, IA64::ADD, 2, dummy)
2345 .addGlobalAddress(cast<GlobalAddressSDNode>
2346 (N.getOperand(2))->getGlobal()).addReg(IA64::r1);
2347 BuildMI(BB, IA64::LD8, 1, dummy2).addReg(dummy);
2350 BuildMI(BB, Opc, 2).addReg(dummy2).addReg(Tmp1);
2351 else { // we are storing a bool, so emit a little pseudocode
2352 // to store a predicate register as one byte
2353 assert(Opc==IA64::ST1);
2354 unsigned dummy3 = MakeReg(MVT::i64);
2355 unsigned dummy4 = MakeReg(MVT::i64);
2356 BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0);
2357 BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4)
2358 .addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1;
2359 BuildMI(BB, Opc, 2).addReg(dummy2).addReg(dummy4);
2361 } else if(N.getOperand(2).getOpcode() == ISD::FrameIndex) {
2363 // FIXME? (what about bools?)
2365 unsigned dummy = MakeReg(MVT::i64);
2366 BuildMI(BB, IA64::MOV, 1, dummy)
2367 .addFrameIndex(cast<FrameIndexSDNode>(N.getOperand(2))->getIndex());
2368 BuildMI(BB, Opc, 2).addReg(dummy).addReg(Tmp1);
2369 } else { // otherwise
2370 Tmp2 = SelectExpr(N.getOperand(2)); //address
2372 BuildMI(BB, Opc, 2).addReg(Tmp2).addReg(Tmp1);
2373 else { // we are storing a bool, so emit a little pseudocode
2374 // to store a predicate register as one byte
2375 assert(Opc==IA64::ST1);
2376 unsigned dummy3 = MakeReg(MVT::i64);
2377 unsigned dummy4 = MakeReg(MVT::i64);
2378 BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0);
2379 BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4)
2380 .addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1;
2381 BuildMI(BB, Opc, 2).addReg(Tmp2).addReg(dummy4);
2387 case ISD::CALLSEQ_START:
2388 case ISD::CALLSEQ_END: {
2389 Select(N.getOperand(0));
2390 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
2392 Opc = N.getOpcode() == ISD::CALLSEQ_START ? IA64::ADJUSTCALLSTACKDOWN :
2393 IA64::ADJUSTCALLSTACKUP;
2394 BuildMI(BB, Opc, 1).addImm(Tmp1);
2400 assert(0 && "GAME OVER. INSERT COIN?");
2404 /// createIA64PatternInstructionSelector - This pass converts an LLVM function
2405 /// into a machine code representation using pattern matching and a machine
2406 /// description file.
2408 FunctionPass *llvm::createIA64PatternInstructionSelector(TargetMachine &TM) {
2409 return new ISel(TM);