1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
26 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
27 : TargetLowering(TM) {
29 // register class for general registers
30 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
32 // register class for FP registers
33 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
35 // register class for predicate registers
36 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
38 setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote);
40 setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Promote);
42 setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Promote);
43 setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand);
44 setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand);
45 setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand);
47 setOperationAction(ISD::BRIND , MVT::Other, Expand);
48 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
49 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
50 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
52 // ia64 uses SELECT not SELECT_CC
53 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
55 // We need to handle ISD::RET for void functions ourselves,
56 // so we get a chance to restore ar.pfs before adding a
58 setOperationAction(ISD::RET, MVT::Other, Custom);
60 setSetCCResultType(MVT::i1);
61 setShiftAmountType(MVT::i64);
63 setOperationAction(ISD::FREM , MVT::f32 , Expand);
64 setOperationAction(ISD::FREM , MVT::f64 , Expand);
66 setOperationAction(ISD::UREM , MVT::f32 , Expand);
67 setOperationAction(ISD::UREM , MVT::f64 , Expand);
69 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
70 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
71 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
73 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
74 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
76 // We don't support sin/cos/sqrt/pow
77 setOperationAction(ISD::FSIN , MVT::f64, Expand);
78 setOperationAction(ISD::FCOS , MVT::f64, Expand);
79 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
80 setOperationAction(ISD::FPOW , MVT::f64, Expand);
81 setOperationAction(ISD::FSIN , MVT::f32, Expand);
82 setOperationAction(ISD::FCOS , MVT::f32, Expand);
83 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
84 setOperationAction(ISD::FPOW , MVT::f32, Expand);
86 // FIXME: IA64 supports fcopysign natively!
87 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
88 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
90 // We don't have line number support yet.
91 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
92 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
93 setOperationAction(ISD::LABEL, MVT::Other, Expand);
95 //IA64 has these, but they are not implemented
96 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
97 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
98 setOperationAction(ISD::ROTL , MVT::i64 , Expand);
99 setOperationAction(ISD::ROTR , MVT::i64 , Expand);
100 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev
102 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
103 setOperationAction(ISD::VAARG , MVT::Other, Custom);
104 setOperationAction(ISD::VASTART , MVT::Other, Custom);
106 // Use the default implementation.
107 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
108 setOperationAction(ISD::VAEND , MVT::Other, Expand);
109 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
110 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
111 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
113 // Thread Local Storage
114 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
116 setStackPointerRegisterToSaveRestore(IA64::r12);
118 setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
119 setJumpBufAlignment(16); // ...and must be 16-byte aligned
121 computeRegisterProperties();
123 addLegalFPImmediate(APFloat(+0.0));
124 addLegalFPImmediate(APFloat(-0.0));
125 addLegalFPImmediate(APFloat(+1.0));
126 addLegalFPImmediate(APFloat(-1.0));
129 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
132 case IA64ISD::GETFD: return "IA64ISD::GETFD";
133 case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
134 case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
139 std::vector<SDOperand>
140 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
141 std::vector<SDOperand> ArgValues;
143 // add beautiful description of IA64 stack frame format
144 // here (from intel 24535803.pdf most likely)
146 MachineFunction &MF = DAG.getMachineFunction();
147 MachineFrameInfo *MFI = MF.getFrameInfo();
148 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
150 GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
151 SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
152 RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
154 MachineBasicBlock& BB = MF.front();
156 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
157 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
159 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
160 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
166 unsigned used_FPArgs = 0; // how many FP args have been used so far?
168 unsigned ArgOffset = 0;
171 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
173 SDOperand newroot, argt;
174 if(count < 8) { // need to fix this logic? maybe.
176 switch (getValueType(I->getType())) {
178 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
180 // fixme? (well, will need to for weird FP structy stuff,
181 // see intel ABI docs)
183 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
184 MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]);
185 // mark this reg as liveIn
186 // floating point args go into f8..f15 as-needed, the increment
187 argVreg[count] = // is below..:
188 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64));
189 // FP args go into f8..f15 as needed: (hence the ++)
190 argPreg[count] = args_FP[used_FPArgs++];
191 argOpc[count] = IA64::FMOV;
192 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
194 if (I->getType() == Type::FloatTy)
195 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt,
196 DAG.getIntPtrConstant(0));
198 case MVT::i1: // NOTE: as far as C abi stuff goes,
199 // bools are just boring old ints
204 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
205 MF.getRegInfo().addLiveIn(args_int[count]);
206 // mark this register as liveIn
208 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
209 argPreg[count] = args_int[count];
210 argOpc[count] = IA64::MOV;
212 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
213 if ( getValueType(I->getType()) != MVT::i64)
214 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
218 } else { // more than 8 args go into the frame
219 // Create the frame index object for this incoming parameter...
220 ArgOffset = 16 + 8 * (count - 8);
221 int FI = MFI->CreateFixedObject(8, ArgOffset);
223 // Create the SelectionDAG nodes corresponding to a load
224 //from this parameter
225 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
226 argt = newroot = DAG.getLoad(getValueType(I->getType()),
227 DAG.getEntryNode(), FIN, NULL, 0);
230 DAG.setRoot(newroot.getValue(1));
231 ArgValues.push_back(argt);
235 // Create a vreg to hold the output of (what will become)
236 // the "alloc" instruction
237 VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
238 BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
239 // we create a PSEUDO_ALLOC (pseudo)instruction for now
241 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
244 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
245 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
248 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
251 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
252 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
256 unsigned tempOffset=0;
258 // if this is a varargs function, we simply lower llvm.va_start by
259 // pointing to the first entry
262 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
265 // here we actually do the moving of args, and store them to the stack
266 // too if this is a varargs function:
267 for (int i = 0; i < count && i < 8; ++i) {
268 BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
270 // if this is a varargs function, we copy the input registers to the stack
271 int FI = MFI->CreateFixedObject(8, tempOffset);
272 tempOffset+=8; //XXX: is it safe to use r22 like this?
273 BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
274 // FIXME: we should use st8.spill here, one day
275 BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
279 // Finally, inform the code generator which regs we return values in.
280 // (see the ISD::RET: case in the instruction selector)
281 switch (getValueType(F.getReturnType())) {
282 default: assert(0 && "i have no idea where to return this type!");
283 case MVT::isVoid: break;
289 MF.getRegInfo().addLiveOut(IA64::r8);
293 MF.getRegInfo().addLiveOut(IA64::F8);
300 std::pair<SDOperand, SDOperand>
301 IA64TargetLowering::LowerCallTo(SDOperand Chain,
302 const Type *RetTy, bool RetTyIsSigned,
303 bool isVarArg, unsigned CallingConv,
304 bool isTailCall, SDOperand Callee,
305 ArgListTy &Args, SelectionDAG &DAG) {
307 MachineFunction &MF = DAG.getMachineFunction();
309 unsigned NumBytes = 16;
310 unsigned outRegsUsed = 0;
312 if (Args.size() > 8) {
313 NumBytes += (Args.size() - 8) * 8;
316 outRegsUsed = Args.size();
319 // FIXME? this WILL fail if we ever try to pass around an arg that
320 // consumes more than a single output slot (a 'real' double, int128
321 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
322 // registers we use. Hopefully, the assembler will notice.
323 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
324 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
326 // keep stack frame 16-byte aligned
327 // assert(NumBytes==((NumBytes+15) & ~15) &&
328 // "stack frame not 16-byte aligned!");
329 NumBytes = (NumBytes+15) & ~15;
331 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
334 std::vector<SDOperand> Stores;
335 std::vector<SDOperand> Converts;
336 std::vector<SDOperand> RegValuesToPass;
337 unsigned ArgOffset = 16;
339 for (unsigned i = 0, e = Args.size(); i != e; ++i)
341 SDOperand Val = Args[i].Node;
342 MVT::ValueType ObjectVT = Val.getValueType();
343 SDOperand ValToStore(0, 0), ValToConvert(0, 0);
346 default: assert(0 && "unexpected argument type!");
351 //promote to 64-bits, sign/zero extending based on type
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
355 ExtendKind = ISD::SIGN_EXTEND;
356 else if (Args[i].isZExt)
357 ExtendKind = ISD::ZERO_EXTEND;
358 Val = DAG.getNode(ExtendKind, MVT::i64, Val);
363 if(RegValuesToPass.size() >= 8) {
366 RegValuesToPass.push_back(Val);
371 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
374 if(RegValuesToPass.size() >= 8) {
377 RegValuesToPass.push_back(Val);
378 if(1 /* TODO: if(calling external or varadic function)*/ ) {
379 ValToConvert = Val; // additionally pass this FP value as an int
387 StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
389 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
390 PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
391 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
392 ArgOffset += ObjSize;
395 if(ValToConvert.Val) {
396 Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
400 // Emit all stores, make sure they occur before any copies into physregs.
402 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
404 static const unsigned IntArgRegs[] = {
405 IA64::out0, IA64::out1, IA64::out2, IA64::out3,
406 IA64::out4, IA64::out5, IA64::out6, IA64::out7
409 static const unsigned FPArgRegs[] = {
410 IA64::F8, IA64::F9, IA64::F10, IA64::F11,
411 IA64::F12, IA64::F13, IA64::F14, IA64::F15
416 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
417 SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
418 Chain = GPBeforeCall.getValue(1);
419 InFlag = Chain.getValue(2);
420 SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
421 Chain = SPBeforeCall.getValue(1);
422 InFlag = Chain.getValue(2);
423 SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
424 Chain = RPBeforeCall.getValue(1);
425 InFlag = Chain.getValue(2);
427 // Build a sequence of copy-to-reg nodes chained together with token chain
428 // and flag operands which copy the outgoing integer args into regs out[0-7]
429 // mapped 1:1 and the FP args into regs F8-F15 "lazily"
430 // TODO: for performance, we should only copy FP args into int regs when we
431 // know this is required (i.e. for varardic or external (unknown) functions)
433 // first to the FP->(integer representation) conversions, these are
434 // flagged for now, but shouldn't have to be (TODO)
435 unsigned seenConverts = 0;
436 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
437 if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
438 Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++],
440 InFlag = Chain.getValue(1);
444 // next copy args into the usual places, these are flagged
445 unsigned usedFPArgs = 0;
446 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
447 Chain = DAG.getCopyToReg(Chain,
448 MVT::isInteger(RegValuesToPass[i].getValueType()) ?
449 IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
450 InFlag = Chain.getValue(1);
453 // If the callee is a GlobalAddress node (quite common, every direct call is)
454 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
456 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
457 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
461 std::vector<MVT::ValueType> NodeTys;
462 std::vector<SDOperand> CallOperands;
463 NodeTys.push_back(MVT::Other); // Returns a chain
464 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
465 CallOperands.push_back(Chain);
466 CallOperands.push_back(Callee);
468 // emit the call itself
470 CallOperands.push_back(InFlag);
472 assert(0 && "this should never happen!\n");
474 // to make way for a hack:
475 Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys,
476 &CallOperands[0], CallOperands.size());
477 InFlag = Chain.getValue(1);
479 // restore the GP, SP and RP after the call
480 Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
481 InFlag = Chain.getValue(1);
482 Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
483 InFlag = Chain.getValue(1);
484 Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
485 InFlag = Chain.getValue(1);
487 std::vector<MVT::ValueType> RetVals;
488 RetVals.push_back(MVT::Other);
489 RetVals.push_back(MVT::Flag);
491 MVT::ValueType RetTyVT = getValueType(RetTy);
493 if (RetTyVT != MVT::isVoid) {
495 default: assert(0 && "Unknown value type to return!");
496 case MVT::i1: { // bools are just like other integers (returned in r8)
497 // we *could* fall through to the truncate below, but this saves a
498 // few redundant predicate ops
499 SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
500 InFlag = boolInR8.getValue(2);
501 Chain = boolInR8.getValue(1);
502 SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
503 InFlag = zeroReg.getValue(2);
504 Chain = zeroReg.getValue(1);
506 RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
512 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
513 Chain = RetVal.getValue(1);
515 // keep track of whether it is sign or zero extended (todo: bools?)
517 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
518 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
520 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
523 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
524 Chain = RetVal.getValue(1);
525 InFlag = RetVal.getValue(2); // XXX dead
528 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
529 Chain = RetVal.getValue(1);
530 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal);
533 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
534 Chain = RetVal.getValue(1);
535 InFlag = RetVal.getValue(2); // XXX dead
540 Chain = DAG.getCALLSEQ_END(Chain,
541 DAG.getConstant(NumBytes, getPointerTy()),
542 DAG.getConstant(0, getPointerTy()),
544 return std::make_pair(RetVal, Chain);
547 SDOperand IA64TargetLowering::
548 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
549 switch (Op.getOpcode()) {
550 default: assert(0 && "Should not custom lower this!");
551 case ISD::GlobalTLSAddress:
552 assert(0 && "TLS not implemented for IA64.");
554 SDOperand AR_PFSVal, Copy;
556 switch(Op.getNumOperands()) {
558 assert(0 && "Do not know how to return this many arguments!");
561 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
562 AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS,
564 return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
566 // Copy the result into the output register & restore ar.pfs
567 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
568 unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;
570 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
571 Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
573 AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal,
575 return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other,
576 AR_PFSVal, AR_PFSVal.getValue(1));
582 MVT::ValueType VT = getPointerTy();
583 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
584 SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
586 // Increment the pointer, VAList, to the next vaarg
587 SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
588 DAG.getConstant(MVT::getSizeInBits(VT)/8,
590 // Store the incremented VAList to the legalized pointer
591 VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
592 Op.getOperand(1), SV, 0);
593 // Load the actual argument out of the pointer VAList
594 return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
597 // vastart just stores the address of the VarArgsFrameIndex slot into the
598 // memory location argument.
599 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
600 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
601 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
603 // Frame & Return address. Currently unimplemented
604 case ISD::RETURNADDR: break;
605 case ISD::FRAMEADDR: break;