1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
26 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
27 : TargetLowering(TM) {
29 // register class for general registers
30 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
32 // register class for FP registers
33 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
35 // register class for predicate registers
36 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
38 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
39 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
40 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
42 setSetCCResultType(MVT::i1);
43 setShiftAmountType(MVT::i64);
45 setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
47 setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
49 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
50 setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
51 setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
52 setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand);
54 setOperationAction(ISD::FREM , MVT::f32 , Expand);
55 setOperationAction(ISD::FREM , MVT::f64 , Expand);
57 setOperationAction(ISD::UREM , MVT::f32 , Expand);
58 setOperationAction(ISD::UREM , MVT::f64 , Expand);
60 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
61 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
62 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
64 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
65 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
67 // We don't support sin/cos/sqrt
68 setOperationAction(ISD::FSIN , MVT::f64, Expand);
69 setOperationAction(ISD::FCOS , MVT::f64, Expand);
70 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
71 setOperationAction(ISD::FSIN , MVT::f32, Expand);
72 setOperationAction(ISD::FCOS , MVT::f32, Expand);
73 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
75 // We don't have line number support yet.
76 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
77 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
78 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
80 //IA64 has these, but they are not implemented
81 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
82 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
84 computeRegisterProperties();
86 addLegalFPImmediate(+0.0);
87 addLegalFPImmediate(+1.0);
90 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
91 static bool isFloatingPointZero(SDOperand Op) {
92 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
93 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
94 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
95 // Maybe this has already been legalized into the constant pool?
96 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
97 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
98 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
103 std::vector<SDOperand>
104 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
105 std::vector<SDOperand> ArgValues;
107 // add beautiful description of IA64 stack frame format
108 // here (from intel 24535803.pdf most likely)
110 MachineFunction &MF = DAG.getMachineFunction();
111 MachineFrameInfo *MFI = MF.getFrameInfo();
113 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
114 SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
115 RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
117 MachineBasicBlock& BB = MF.front();
119 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
120 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
122 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
123 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
129 unsigned used_FPArgs = 0; // how many FP args have been used so far?
131 unsigned ArgOffset = 0;
134 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
136 SDOperand newroot, argt;
137 if(count < 8) { // need to fix this logic? maybe.
139 switch (getValueType(I->getType())) {
141 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
143 // fixme? (well, will need to for weird FP structy stuff,
144 // see intel ABI docs)
146 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
147 MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
148 // floating point args go into f8..f15 as-needed, the increment
149 argVreg[count] = // is below..:
150 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
151 // FP args go into f8..f15 as needed: (hence the ++)
152 argPreg[count] = args_FP[used_FPArgs++];
153 argOpc[count] = IA64::FMOV;
154 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
156 if (I->getType() == Type::FloatTy)
157 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
159 case MVT::i1: // NOTE: as far as C abi stuff goes,
160 // bools are just boring old ints
165 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
166 MF.addLiveIn(args_int[count]); // mark this register as liveIn
168 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
169 argPreg[count] = args_int[count];
170 argOpc[count] = IA64::MOV;
172 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
173 if ( getValueType(I->getType()) != MVT::i64)
174 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
178 } else { // more than 8 args go into the frame
179 // Create the frame index object for this incoming parameter...
180 ArgOffset = 16 + 8 * (count - 8);
181 int FI = MFI->CreateFixedObject(8, ArgOffset);
183 // Create the SelectionDAG nodes corresponding to a load
184 //from this parameter
185 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
186 argt = newroot = DAG.getLoad(getValueType(I->getType()),
187 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
190 DAG.setRoot(newroot.getValue(1));
191 ArgValues.push_back(argt);
195 // Create a vreg to hold the output of (what will become)
196 // the "alloc" instruction
197 VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
198 BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
199 // we create a PSEUDO_ALLOC (pseudo)instruction for now
201 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
204 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
205 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
208 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
211 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
212 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
216 unsigned tempOffset=0;
218 // if this is a varargs function, we simply lower llvm.va_start by
219 // pointing to the first entry
222 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
225 // here we actually do the moving of args, and store them to the stack
226 // too if this is a varargs function:
227 for (int i = 0; i < count && i < 8; ++i) {
228 BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
230 // if this is a varargs function, we copy the input registers to the stack
231 int FI = MFI->CreateFixedObject(8, tempOffset);
232 tempOffset+=8; //XXX: is it safe to use r22 like this?
233 BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
234 // FIXME: we should use st8.spill here, one day
235 BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
239 // Finally, inform the code generator which regs we return values in.
240 // (see the ISD::RET: case in the instruction selector)
241 switch (getValueType(F.getReturnType())) {
242 default: assert(0 && "i have no idea where to return this type!");
243 case MVT::isVoid: break;
249 MF.addLiveOut(IA64::r8);
253 MF.addLiveOut(IA64::F8);
260 std::pair<SDOperand, SDOperand>
261 IA64TargetLowering::LowerCallTo(SDOperand Chain,
262 const Type *RetTy, bool isVarArg,
263 unsigned CallingConv, bool isTailCall,
264 SDOperand Callee, ArgListTy &Args,
267 MachineFunction &MF = DAG.getMachineFunction();
269 unsigned NumBytes = 16;
270 unsigned outRegsUsed = 0;
272 if (Args.size() > 8) {
273 NumBytes += (Args.size() - 8) * 8;
276 outRegsUsed = Args.size();
279 // FIXME? this WILL fail if we ever try to pass around an arg that
280 // consumes more than a single output slot (a 'real' double, int128
281 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
282 // registers we use. Hopefully, the assembler will notice.
283 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
284 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
286 // keep stack frame 16-byte aligned
287 //assert(NumBytes==((NumBytes+15) & ~15) && "stack frame not 16-byte aligned!");
288 NumBytes = (NumBytes+15) & ~15;
290 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
291 DAG.getConstant(NumBytes, getPointerTy()));
293 SDOperand StackPtr, NullSV;
294 std::vector<SDOperand> Stores;
295 std::vector<SDOperand> Converts;
296 std::vector<SDOperand> RegValuesToPass;
297 unsigned ArgOffset = 16;
299 for (unsigned i = 0, e = Args.size(); i != e; ++i)
301 SDOperand Val = Args[i].first;
302 MVT::ValueType ObjectVT = Val.getValueType();
303 SDOperand ValToStore(0, 0), ValToConvert(0, 0);
306 default: assert(0 && "unexpected argument type!");
311 //promote to 64-bits, sign/zero extending based on type
313 if(Args[i].second->isSigned())
314 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Val);
316 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Val);
320 if(RegValuesToPass.size() >= 8) {
323 RegValuesToPass.push_back(Val);
328 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
331 if(RegValuesToPass.size() >= 8) {
334 RegValuesToPass.push_back(Val);
335 if(1 /* TODO: if(calling external or varadic function)*/ ) {
336 ValToConvert = Val; // additionally pass this FP value as an int
344 StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
345 NullSV = DAG.getSrcValue(NULL);
347 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
348 PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
349 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
350 ValToStore, PtrOff, NullSV));
351 ArgOffset += ObjSize;
354 if(ValToConvert.Val) {
355 Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
359 // Emit all stores, make sure they occur before any copies into physregs.
361 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
363 static const unsigned IntArgRegs[] = {
364 IA64::out0, IA64::out1, IA64::out2, IA64::out3,
365 IA64::out4, IA64::out5, IA64::out6, IA64::out7
368 static const unsigned FPArgRegs[] = {
369 IA64::F8, IA64::F9, IA64::F10, IA64::F11,
370 IA64::F12, IA64::F13, IA64::F14, IA64::F15
375 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
376 SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
377 Chain = GPBeforeCall;
378 InFlag = Chain.getValue(1);
379 SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
380 Chain = SPBeforeCall;
381 InFlag = Chain.getValue(1);
382 SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
383 Chain = RPBeforeCall;
384 InFlag = Chain.getValue(1);
386 // Build a sequence of copy-to-reg nodes chained together with token chain
387 // and flag operands which copy the outgoing integer args into regs out[0-7]
388 // mapped 1:1 and the FP args into regs F8-F15 "lazily"
389 // TODO: for performance, we should only copy FP args into int regs when we
390 // know this is required (i.e. for varardic or external (unknown) functions)
392 // first to the FP->(integer representation) conversions, these are
394 unsigned seenConverts = 0;
395 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
396 if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
397 Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++]);
401 // next copy args into the usual places, these are flagged
402 unsigned usedFPArgs = 0;
403 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
404 Chain = DAG.getCopyToReg(Chain,
405 MVT::isInteger(RegValuesToPass[i].getValueType()) ?
406 IntArgRegs[i] : FPArgRegs[usedFPArgs++],
407 RegValuesToPass[i], InFlag);
408 InFlag = Chain.getValue(1);
411 // If the callee is a GlobalAddress node (quite common, every direct call is)
412 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
414 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
415 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
419 std::vector<MVT::ValueType> NodeTys;
420 std::vector<SDOperand> CallOperands;
421 NodeTys.push_back(MVT::Other); // Returns a chain
422 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
423 CallOperands.push_back(Chain);
424 CallOperands.push_back(Callee);
426 // emit the call itself
428 CallOperands.push_back(InFlag);
430 /* out with the old...
431 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
433 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
435 // to make way for a hack:
436 Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys, CallOperands);
437 InFlag = Chain.getValue(1);
439 // restore the GP, SP and RP after the call
440 Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
441 InFlag = Chain.getValue(1);
442 Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
443 InFlag = Chain.getValue(1);
444 Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
445 InFlag = Chain.getValue(1);
447 std::vector<MVT::ValueType> RetVals;
448 RetVals.push_back(MVT::Other);
449 RetVals.push_back(MVT::Flag);
451 MVT::ValueType RetTyVT = getValueType(RetTy);
453 if (RetTyVT != MVT::isVoid) {
455 default: // assert(0 && "Unknown value type to return!");
456 case MVT::i1: { // bools are just like other integers (returned in r8)
457 SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
458 InFlag = boolInR8.getValue(2);
459 Chain = boolInR8.getValue(1);
460 SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
461 InFlag = zeroReg.getValue(2);
462 Chain = zeroReg.getValue(1);
464 RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
470 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
471 Chain = RetVal.getValue(1);
473 // Add a note to keep track of whether it is sign or zero extended - TODO: bools
474 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
475 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
476 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
479 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
480 Chain = RetVal.getValue(1);
483 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
484 Chain = RetVal.getValue(1);
489 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
490 DAG.getConstant(NumBytes, getPointerTy()));
492 return std::make_pair(RetVal, Chain);
496 IA64TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
497 Value *VAListV, SelectionDAG &DAG) {
498 // vastart just stores the address of the VarArgsFrameIndex slot.
499 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
500 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR,
501 VAListP, DAG.getSrcValue(VAListV));
504 std::pair<SDOperand,SDOperand> IA64TargetLowering::
505 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
506 const Type *ArgTy, SelectionDAG &DAG) {
508 MVT::ValueType ArgVT = getValueType(ArgTy);
509 SDOperand Val = DAG.getLoad(MVT::i64, Chain,
510 VAListP, DAG.getSrcValue(VAListV));
511 SDOperand Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), Val,
512 DAG.getSrcValue(NULL));
514 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
517 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
518 "Other types should have been promoted for varargs!");
521 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
522 DAG.getConstant(Amt, Val.getValueType()));
523 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
524 Val, VAListP, DAG.getSrcValue(VAListV));
525 return std::make_pair(Result, Chain);
530 std::pair<SDOperand, SDOperand> IA64TargetLowering::
531 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
533 assert(0 && "LowerFrameReturnAddress unimplemented");