1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
26 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
27 : TargetLowering(TM) {
29 // register class for general registers
30 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
32 // register class for FP registers
33 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
35 // register class for predicate registers
36 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
38 setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote);
40 setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
42 setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Expand);
43 setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand);
44 setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand);
45 setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand);
47 setOperationAction(ISD::BRIND , MVT::Other, Expand);
48 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
49 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
50 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
52 // ia64 uses SELECT not SELECT_CC
53 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
55 // We need to handle ISD::RET for void functions ourselves,
56 // so we get a chance to restore ar.pfs before adding a
58 setOperationAction(ISD::RET, MVT::Other, Custom);
60 setSetCCResultType(MVT::i1);
61 setShiftAmountType(MVT::i64);
63 setOperationAction(ISD::FREM , MVT::f32 , Expand);
64 setOperationAction(ISD::FREM , MVT::f64 , Expand);
66 setOperationAction(ISD::UREM , MVT::f32 , Expand);
67 setOperationAction(ISD::UREM , MVT::f64 , Expand);
69 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
70 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
71 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
73 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
74 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
76 // We don't support sin/cos/sqrt
77 setOperationAction(ISD::FSIN , MVT::f64, Expand);
78 setOperationAction(ISD::FCOS , MVT::f64, Expand);
79 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
80 setOperationAction(ISD::FSIN , MVT::f32, Expand);
81 setOperationAction(ISD::FCOS , MVT::f32, Expand);
82 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
84 // FIXME: IA64 supports fcopysign natively!
85 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
86 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
88 // We don't have line number support yet.
89 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
90 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
91 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
93 //IA64 has these, but they are not implemented
94 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
95 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
96 setOperationAction(ISD::ROTL , MVT::i64 , Expand);
97 setOperationAction(ISD::ROTR , MVT::i64 , Expand);
98 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev
100 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
101 setOperationAction(ISD::VAARG , MVT::Other, Custom);
102 setOperationAction(ISD::VASTART , MVT::Other, Custom);
104 // Use the default implementation.
105 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
106 setOperationAction(ISD::VAEND , MVT::Other, Expand);
107 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
108 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
109 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
111 setStackPointerRegisterToSaveRestore(IA64::r12);
113 setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
114 setJumpBufAlignment(16); // ...and must be 16-byte aligned
116 computeRegisterProperties();
118 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
119 addLegalFPImmediate(+0.0);
120 addLegalFPImmediate(+1.0);
123 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
126 case IA64ISD::GETFD: return "IA64ISD::GETFD";
127 case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
128 case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
133 std::vector<SDOperand>
134 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
135 std::vector<SDOperand> ArgValues;
137 // add beautiful description of IA64 stack frame format
138 // here (from intel 24535803.pdf most likely)
140 MachineFunction &MF = DAG.getMachineFunction();
141 MachineFrameInfo *MFI = MF.getFrameInfo();
142 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
144 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
145 SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
146 RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
148 MachineBasicBlock& BB = MF.front();
150 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
151 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
153 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
154 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
160 unsigned used_FPArgs = 0; // how many FP args have been used so far?
162 unsigned ArgOffset = 0;
165 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
167 SDOperand newroot, argt;
168 if(count < 8) { // need to fix this logic? maybe.
170 switch (getValueType(I->getType())) {
172 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
174 // fixme? (well, will need to for weird FP structy stuff,
175 // see intel ABI docs)
177 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
178 MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
179 // floating point args go into f8..f15 as-needed, the increment
180 argVreg[count] = // is below..:
181 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
182 // FP args go into f8..f15 as needed: (hence the ++)
183 argPreg[count] = args_FP[used_FPArgs++];
184 argOpc[count] = IA64::FMOV;
185 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
187 if (I->getType() == Type::FloatTy)
188 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
190 case MVT::i1: // NOTE: as far as C abi stuff goes,
191 // bools are just boring old ints
196 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
197 MF.addLiveIn(args_int[count]); // mark this register as liveIn
199 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
200 argPreg[count] = args_int[count];
201 argOpc[count] = IA64::MOV;
203 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
204 if ( getValueType(I->getType()) != MVT::i64)
205 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
209 } else { // more than 8 args go into the frame
210 // Create the frame index object for this incoming parameter...
211 ArgOffset = 16 + 8 * (count - 8);
212 int FI = MFI->CreateFixedObject(8, ArgOffset);
214 // Create the SelectionDAG nodes corresponding to a load
215 //from this parameter
216 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
217 argt = newroot = DAG.getLoad(getValueType(I->getType()),
218 DAG.getEntryNode(), FIN, NULL, 0);
221 DAG.setRoot(newroot.getValue(1));
222 ArgValues.push_back(argt);
226 // Create a vreg to hold the output of (what will become)
227 // the "alloc" instruction
228 VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
229 BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
230 // we create a PSEUDO_ALLOC (pseudo)instruction for now
232 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
235 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
236 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
239 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
242 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
243 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
247 unsigned tempOffset=0;
249 // if this is a varargs function, we simply lower llvm.va_start by
250 // pointing to the first entry
253 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
256 // here we actually do the moving of args, and store them to the stack
257 // too if this is a varargs function:
258 for (int i = 0; i < count && i < 8; ++i) {
259 BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
261 // if this is a varargs function, we copy the input registers to the stack
262 int FI = MFI->CreateFixedObject(8, tempOffset);
263 tempOffset+=8; //XXX: is it safe to use r22 like this?
264 BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
265 // FIXME: we should use st8.spill here, one day
266 BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
270 // Finally, inform the code generator which regs we return values in.
271 // (see the ISD::RET: case in the instruction selector)
272 switch (getValueType(F.getReturnType())) {
273 default: assert(0 && "i have no idea where to return this type!");
274 case MVT::isVoid: break;
280 MF.addLiveOut(IA64::r8);
284 MF.addLiveOut(IA64::F8);
291 std::pair<SDOperand, SDOperand>
292 IA64TargetLowering::LowerCallTo(SDOperand Chain,
293 const Type *RetTy, bool RetTyIsSigned,
294 bool isVarArg, unsigned CallingConv,
295 bool isTailCall, SDOperand Callee,
296 ArgListTy &Args, SelectionDAG &DAG) {
298 MachineFunction &MF = DAG.getMachineFunction();
300 unsigned NumBytes = 16;
301 unsigned outRegsUsed = 0;
303 if (Args.size() > 8) {
304 NumBytes += (Args.size() - 8) * 8;
307 outRegsUsed = Args.size();
310 // FIXME? this WILL fail if we ever try to pass around an arg that
311 // consumes more than a single output slot (a 'real' double, int128
312 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
313 // registers we use. Hopefully, the assembler will notice.
314 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
315 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
317 // keep stack frame 16-byte aligned
318 // assert(NumBytes==((NumBytes+15) & ~15) &&
319 // "stack frame not 16-byte aligned!");
320 NumBytes = (NumBytes+15) & ~15;
322 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
325 std::vector<SDOperand> Stores;
326 std::vector<SDOperand> Converts;
327 std::vector<SDOperand> RegValuesToPass;
328 unsigned ArgOffset = 16;
330 for (unsigned i = 0, e = Args.size(); i != e; ++i)
332 SDOperand Val = Args[i].Node;
333 MVT::ValueType ObjectVT = Val.getValueType();
334 SDOperand ValToStore(0, 0), ValToConvert(0, 0);
337 default: assert(0 && "unexpected argument type!");
342 //promote to 64-bits, sign/zero extending based on type
344 ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
345 if (Args[i].isSigned)
346 ExtendKind = ISD::SIGN_EXTEND;
347 Val = DAG.getNode(ExtendKind, MVT::i64, Val);
352 if(RegValuesToPass.size() >= 8) {
355 RegValuesToPass.push_back(Val);
360 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
363 if(RegValuesToPass.size() >= 8) {
366 RegValuesToPass.push_back(Val);
367 if(1 /* TODO: if(calling external or varadic function)*/ ) {
368 ValToConvert = Val; // additionally pass this FP value as an int
376 StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
378 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
379 PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
380 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
381 ArgOffset += ObjSize;
384 if(ValToConvert.Val) {
385 Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
389 // Emit all stores, make sure they occur before any copies into physregs.
391 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
393 static const unsigned IntArgRegs[] = {
394 IA64::out0, IA64::out1, IA64::out2, IA64::out3,
395 IA64::out4, IA64::out5, IA64::out6, IA64::out7
398 static const unsigned FPArgRegs[] = {
399 IA64::F8, IA64::F9, IA64::F10, IA64::F11,
400 IA64::F12, IA64::F13, IA64::F14, IA64::F15
405 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
406 SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
407 Chain = GPBeforeCall.getValue(1);
408 InFlag = Chain.getValue(2);
409 SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
410 Chain = SPBeforeCall.getValue(1);
411 InFlag = Chain.getValue(2);
412 SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
413 Chain = RPBeforeCall.getValue(1);
414 InFlag = Chain.getValue(2);
416 // Build a sequence of copy-to-reg nodes chained together with token chain
417 // and flag operands which copy the outgoing integer args into regs out[0-7]
418 // mapped 1:1 and the FP args into regs F8-F15 "lazily"
419 // TODO: for performance, we should only copy FP args into int regs when we
420 // know this is required (i.e. for varardic or external (unknown) functions)
422 // first to the FP->(integer representation) conversions, these are
423 // flagged for now, but shouldn't have to be (TODO)
424 unsigned seenConverts = 0;
425 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
426 if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
427 Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++],
429 InFlag = Chain.getValue(1);
433 // next copy args into the usual places, these are flagged
434 unsigned usedFPArgs = 0;
435 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
436 Chain = DAG.getCopyToReg(Chain,
437 MVT::isInteger(RegValuesToPass[i].getValueType()) ?
438 IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
439 InFlag = Chain.getValue(1);
442 // If the callee is a GlobalAddress node (quite common, every direct call is)
443 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
445 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
446 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
450 std::vector<MVT::ValueType> NodeTys;
451 std::vector<SDOperand> CallOperands;
452 NodeTys.push_back(MVT::Other); // Returns a chain
453 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
454 CallOperands.push_back(Chain);
455 CallOperands.push_back(Callee);
457 // emit the call itself
459 CallOperands.push_back(InFlag);
461 assert(0 && "this should never happen!\n");
463 // to make way for a hack:
464 Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys,
465 &CallOperands[0], CallOperands.size());
466 InFlag = Chain.getValue(1);
468 // restore the GP, SP and RP after the call
469 Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
470 InFlag = Chain.getValue(1);
471 Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
472 InFlag = Chain.getValue(1);
473 Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
474 InFlag = Chain.getValue(1);
476 std::vector<MVT::ValueType> RetVals;
477 RetVals.push_back(MVT::Other);
478 RetVals.push_back(MVT::Flag);
480 MVT::ValueType RetTyVT = getValueType(RetTy);
482 if (RetTyVT != MVT::isVoid) {
484 default: assert(0 && "Unknown value type to return!");
485 case MVT::i1: { // bools are just like other integers (returned in r8)
486 // we *could* fall through to the truncate below, but this saves a
487 // few redundant predicate ops
488 SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
489 InFlag = boolInR8.getValue(2);
490 Chain = boolInR8.getValue(1);
491 SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
492 InFlag = zeroReg.getValue(2);
493 Chain = zeroReg.getValue(1);
495 RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
501 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
502 Chain = RetVal.getValue(1);
504 // keep track of whether it is sign or zero extended (todo: bools?)
506 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
507 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
509 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
512 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
513 Chain = RetVal.getValue(1);
514 InFlag = RetVal.getValue(2); // XXX dead
517 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
518 Chain = RetVal.getValue(1);
519 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal);
522 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
523 Chain = RetVal.getValue(1);
524 InFlag = RetVal.getValue(2); // XXX dead
529 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
530 DAG.getConstant(NumBytes, getPointerTy()));
532 return std::make_pair(RetVal, Chain);
535 std::pair<SDOperand, SDOperand> IA64TargetLowering::
536 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
538 assert(0 && "LowerFrameReturnAddress unimplemented");
542 SDOperand IA64TargetLowering::
543 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
544 switch (Op.getOpcode()) {
545 default: assert(0 && "Should not custom lower this!");
547 SDOperand AR_PFSVal, Copy;
549 switch(Op.getNumOperands()) {
551 assert(0 && "Do not know how to return this many arguments!");
554 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
555 AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS,
557 return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
559 // Copy the result into the output register & restore ar.pfs
560 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
561 unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;
563 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
564 Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
566 AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal,
568 return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other,
569 AR_PFSVal, AR_PFSVal.getValue(1));
575 MVT::ValueType VT = getPointerTy();
576 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
577 SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
578 SV->getValue(), SV->getOffset());
579 // Increment the pointer, VAList, to the next vaarg
580 SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
581 DAG.getConstant(MVT::getSizeInBits(VT)/8,
583 // Store the incremented VAList to the legalized pointer
584 VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
585 Op.getOperand(1), SV->getValue(), SV->getOffset());
586 // Load the actual argument out of the pointer VAList
587 return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
590 // vastart just stores the address of the VarArgsFrameIndex slot into the
591 // memory location argument.
592 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
593 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
594 return DAG.getStore(Op.getOperand(0), FR,
595 Op.getOperand(1), SV->getValue(), SV->getOffset());