1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
16 #include "IA64TargetMachine.h"
17 #include "IA64ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
32 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
33 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
35 //===--------------------------------------------------------------------===//
36 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
37 /// instructions for SelectionDAG operations.
39 class IA64DAGToDAGISel : public SelectionDAGISel {
40 IA64TargetLowering IA64Lowering;
41 unsigned GlobalBaseReg;
43 IA64DAGToDAGISel(TargetMachine &TM)
44 : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI64Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI64Imm(uint64_t Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i64);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 // SDOperand getGlobalBaseReg(); TODO: hmm
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDOperand Select(SDOperand Op);
66 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
67 unsigned OCHi, unsigned OCLo,
68 bool IsArithmetic = false,
70 SDNode *SelectBitfieldInsert(SDNode *N);
72 /// SelectCC - Select a comparison of the specified values with the
73 /// specified condition code, returning the CR# of the expression.
74 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
76 /// SelectAddr - Given the specified address, return the two operands for a
77 /// load/store instruction, and return true if it should be an indexed [r+r]
79 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
81 SDOperand BuildSDIVSequence(SDNode *N);
82 SDOperand BuildUDIVSequence(SDNode *N);
84 /// InstructionSelectBasicBlock - This callback is invoked by
85 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
86 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
88 virtual const char *getPassName() const {
89 return "IA64 (Itanium) DAG->DAG Instruction Selector";
92 // Include the pieces autogenerated from the target description.
93 #include "IA64GenDAGISel.inc"
96 SDOperand SelectCALL(SDOperand Op);
100 /// InstructionSelectBasicBlock - This callback is invoked by
101 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
102 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
105 // The selection process is inherently a bottom-up recursive process (users
106 // select their uses before themselves). Given infinite stack space, we
107 // could just start selecting on the root and traverse the whole graph. In
108 // practice however, this causes us to run out of stack space on large basic
109 // blocks. To avoid this problem, select the entry node, then all its uses,
110 // iteratively instead of recursively.
111 std::vector<SDOperand> Worklist;
112 Worklist.push_back(DAG.getEntryNode());
114 // Note that we can do this in the IA64 target (scanning forward across token
115 // chain edges) because no nodes ever get folded across these edges. On a
116 // target like X86 which supports load/modify/store operations, this would
117 // have to be more careful.
118 while (!Worklist.empty()) {
119 SDOperand Node = Worklist.back();
122 // Chose from the least deep of the top two nodes.
123 if (!Worklist.empty() &&
124 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
125 std::swap(Worklist.back(), Node);
127 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
128 Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
129 CodeGenMap.count(Node)) continue;
131 for (SDNode::use_iterator UI = Node.Val->use_begin(),
132 E = Node.Val->use_end(); UI != E; ++UI) {
133 // Scan the values. If this use has a value that is a token chain, add it
136 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
137 if (User->getValueType(i) == MVT::Other) {
138 Worklist.push_back(SDOperand(User, i));
143 // Finally, legalize this node.
147 // Select target instructions for the DAG.
148 DAG.setRoot(Select(DAG.getRoot()));
150 DAG.RemoveDeadNodes();
152 // Emit machine code to BB.
153 ScheduleAndEmitDAG(DAG);
157 SDOperand IA64DAGToDAGISel::SelectCALL(SDOperand Op) {
159 SDOperand Chain = Select(N->getOperand(0));
162 std::vector<SDOperand> CallOperands;
164 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
165 SDOperand GPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r1, MVT::i64);
166 Chain = GPBeforeCall.getValue(1);
167 SDOperand SPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
168 Chain = SPBeforeCall.getValue(1);
169 SDOperand RPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::rp, MVT::i64);
170 Chain = RPBeforeCall.getValue(1);
172 // if we can call directly, do so
173 if (GlobalAddressSDNode *GASD =
174 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
175 CallOpcode = IA64::BRCALL_IPREL;
176 CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
178 } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
179 // case for correctness, to avoid
180 // "non-pic code with imm reloc.n
181 // against dynamic symbol" errors
182 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
183 CallOpcode = IA64::BRCALL_IPREL;
184 CallOperands.push_back(N->getOperand(1));
186 // otherwise we need to load the function descriptor,
187 // load the branch target (function)'s entry point and GP,
188 // branch (call) then restore the GP
190 SDOperand FnDescriptor = Select(N->getOperand(1));
192 // load the branch target's entry point [mem] and
194 SDOperand targetEntryPoint=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
196 Chain = targetEntryPoint.getValue(1);
197 SDOperand targetGPAddr=CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
198 FnDescriptor, CurDAG->getConstant(8, MVT::i64));
199 Chain = targetGPAddr.getValue(1);
200 SDOperand targetGP=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
202 Chain = targetGP.getValue(1);
204 /* FIXME? (methcall still fails)
205 SDOperand targetEntryPoint=CurDAG->getLoad(MVT::i64, Chain, FnDescriptor,
206 CurDAG->getSrcValue(0));
207 SDOperand targetGPAddr=CurDAG->getNode(ISD::ADD, MVT::i64, FnDescriptor,
208 CurDAG->getConstant(8, MVT::i64));
209 SDOperand targetGP=CurDAG->getLoad(MVT::i64, Chain, targetGPAddr,
210 CurDAG->getSrcValue(0));
213 /* this is just the long way of writing the two lines below?
214 // Copy the callee GP into r1
215 SDOperand r1 = CurDAG->getRegister(IA64::r1, MVT::i64);
216 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::i64, Chain, r1,
220 // Copy the callee address into the b6 branch register
221 SDOperand B6 = CurDAG->getRegister(IA64::B6, MVT::i64);
222 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::i64, Chain, B6,
226 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP);
227 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint);
229 CallOperands.push_back(CurDAG->getRegister(IA64::B6, MVT::i64));
230 CallOpcode = IA64::BRCALL_INDIRECT;
233 // see section 8.5.8 of "Itanium Software Conventions and
234 // Runtime Architecture Guide to see some examples of what's going
235 // on here. (in short: int args get mapped 1:1 'slot-wise' to out0->out7,
236 // while FP args get mapped to F8->F15 as needed)
238 // TODO: support in-memory arguments
240 unsigned used_FPArgs=0; // how many FP args have been used so far?
242 unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
243 IA64::out4, IA64::out5, IA64::out6, IA64::out7 };
244 unsigned FPArgs[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
245 IA64::F12, IA64::F13, IA64::F14, IA64::F15 };
247 SDOperand InFlag; // Null incoming flag value.
249 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
250 unsigned DestReg = 0;
251 MVT::ValueType RegTy = N->getOperand(i).getValueType();
252 if (RegTy == MVT::i64) {
253 assert((i-2) < 8 && "Too many int args");
254 DestReg = intArgs[i-2];
256 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
257 "Unpromoted integer arg?");
258 assert(used_FPArgs < 8 && "Too many fp args");
259 DestReg = FPArgs[used_FPArgs++];
262 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
263 SDOperand Val = Select(N->getOperand(i));
264 if(MVT::isInteger(N->getOperand(i).getValueType())) {
265 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
266 InFlag = Chain.getValue(1);
267 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
269 // some functions (e.g. printf) want floating point arguments
270 // *also* passed as in-memory representations in integer registers
271 // this is FORTRAN legacy junk which we don't _always_ need
272 // to do, but to be on the safe side, we do.
273 else if(MVT::isFloatingPoint(N->getOperand(i).getValueType())) {
274 assert((i-2) < 8 && "FP args alone would fit, but no int regs left");
275 // first copy into the appropriate FP reg
276 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val);
277 // then copy into the appropriate integer reg
278 DestReg = intArgs[i-2];
279 // GETFD takes an FP reg and writes a GP reg
280 Chain = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Val);
281 // FIXME: this next line is a bit unfortunate
282 Chain = CurDAG->getCopyToReg(Chain, DestReg, Chain, InFlag);
283 InFlag = Chain.getValue(1);
284 CallOperands.push_back(CurDAG->getRegister(DestReg, MVT::i64));
289 // Finally, once everything is in registers to pass to the call, emit the
292 CallOperands.push_back(InFlag); // Strong dep on register copies.
294 CallOperands.push_back(Chain); // Weak dep on whatever occurs before
295 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
298 std::vector<SDOperand> CallResults;
300 // If the call has results, copy the values out of the ret val registers.
301 switch (N->getValueType(0)) {
302 default: assert(0 && "Unexpected ret value!");
303 case MVT::Other: break;
305 // bools are returned as bytes 0/1 in r8
306 SDOperand byteval = CurDAG->getCopyFromReg(Chain, IA64::r8, MVT::i64,
308 Chain = byteval.getValue(1);
309 Chain = CurDAG->getTargetNode(IA64::CMPNE, MVT::i1, MVT::Other,
310 byteval, CurDAG->getRegister(IA64::r0, MVT::i64)).getValue(1);
311 CallResults.push_back(Chain.getValue(0));
315 Chain = CurDAG->getCopyFromReg(Chain, IA64::r8, MVT::i64,
316 Chain.getValue(1)).getValue(1);
317 CallResults.push_back(Chain.getValue(0));
320 Chain = CurDAG->getCopyFromReg(Chain, IA64::F8, N->getValueType(0),
321 Chain.getValue(1)).getValue(1);
322 CallResults.push_back(Chain.getValue(0));
326 // restore GP, SP and RP - FIXME: this doesn't quite work (e.g.
327 // methcall / objinst both segfault on exit) and it *really*
328 // doesn't work unless you have -sched=none
329 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, GPBeforeCall);
330 Chain = CurDAG->getCopyToReg(Chain, IA64::r12, SPBeforeCall);
331 Chain = CurDAG->getCopyToReg(Chain, IA64::rp, RPBeforeCall);
332 CallResults.push_back(Chain); // llc segfaults w/o this,
333 // ary3(e.g.) SIGILLs with 3
335 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
336 CodeGenMap[Op.getValue(i)] = CallResults[i];
338 return CallResults[Op.ResNo];
341 // Select - Convert the specified operand from a target-independent to a
342 // target-specific node if it hasn't already been changed.
343 SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
345 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
346 N->getOpcode() < IA64ISD::FIRST_NUMBER)
347 return Op; // Already selected.
349 // If this has already been converted, use it.
350 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
351 if (CGMI != CodeGenMap.end()) return CGMI->second;
353 switch (N->getOpcode()) {
357 case ISD::TAILCALL: return SelectCALL(Op);
360 * case ISD::DYNAMIC_STACKALLOC:
362 case ISD::ConstantFP: {
363 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
365 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0))
366 return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
367 else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0))
368 return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
370 assert(0 && "Unexpected FP constant!");
373 case ISD::FrameIndex: { // TODO: reduce creepyness
374 int FI = cast<FrameIndexSDNode>(N)->getIndex();
375 if (N->hasOneUse()) {
376 CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
377 CurDAG->getTargetFrameIndex(FI, MVT::i64));
378 return SDOperand(N, 0);
380 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
381 CurDAG->getTargetFrameIndex(FI, MVT::i64));
384 case ISD::ConstantPool: {
385 Constant *C = cast<ConstantPoolSDNode>(N)->get();
386 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
387 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
388 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
391 case ISD::GlobalAddress: {
392 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
393 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
394 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
395 CurDAG->getRegister(IA64::r1, MVT::i64), GA);
396 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
401 case ISD::ZEXTLOAD: {
402 SDOperand Chain = Select(N->getOperand(0));
403 SDOperand Address = Select(N->getOperand(1));
405 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
406 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
408 switch (TypeBeingLoaded) {
409 default: N->dump(); assert(0 && "Cannot load this type!");
410 case MVT::i1: { // this is a bool
411 Opc = IA64::LD1; // first we load a byte, then compare for != 0
412 CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
413 CurDAG->getTargetNode(Opc, MVT::i64, Address),
414 CurDAG->getRegister(IA64::r0, MVT::i64), Chain);
415 return SDOperand(N, Op.ResNo); // XXX: early exit
417 case MVT::i8: Opc = IA64::LD1; break;
418 case MVT::i16: Opc = IA64::LD2; break;
419 case MVT::i32: Opc = IA64::LD4; break;
420 case MVT::i64: Opc = IA64::LD8; break;
422 case MVT::f32: Opc = IA64::LDF4; break;
423 case MVT::f64: Opc = IA64::LDF8; break;
426 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
427 Address, Chain); // TODO: comment this
429 return SDOperand(N, Op.ResNo);
432 case ISD::TRUNCSTORE:
434 SDOperand Address = Select(N->getOperand(2));
435 SDOperand Chain = Select(N->getOperand(0));
438 if (N->getOpcode() == ISD::STORE) {
439 switch (N->getOperand(1).getValueType()) {
440 default: assert(0 && "unknown type in store");
441 case MVT::i1: { // this is a bool
442 Opc = IA64::ST1; // we store either 0 or 1 as a byte
443 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address,
444 CurDAG->getTargetNode(IA64::PADDS, MVT::i64,
445 CurDAG->getRegister(IA64::r0, MVT::i64),
446 CurDAG->getConstant(1, MVT::i64),
447 Select(N->getOperand(1))),
449 return SDOperand(N, 0); // XXX: early exit
451 case MVT::i64: Opc = IA64::ST8; break;
452 case MVT::f64: Opc = IA64::STF8; break;
454 } else { //ISD::TRUNCSTORE
455 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
456 default: assert(0 && "unknown type in truncstore");
457 case MVT::i8: Opc = IA64::ST1; break;
458 case MVT::i16: Opc = IA64::ST2; break;
459 case MVT::i32: Opc = IA64::ST4; break;
460 case MVT::f32: Opc = IA64::STF4; break;
464 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
465 Select(N->getOperand(1)), Chain);
466 return SDOperand(N, 0);
470 SDOperand Chain = Select(N->getOperand(0));
471 SDOperand CC = Select(N->getOperand(1));
472 MachineBasicBlock *Dest =
473 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
474 //FIXME - we do NOT need long branches all the time
475 CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, CurDAG->getBasicBlock(Dest), Chain);
476 return SDOperand(N, 0);
479 case ISD::CALLSEQ_START:
480 case ISD::CALLSEQ_END: {
481 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
482 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
483 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
484 CurDAG->SelectNodeTo(N, Opc, MVT::Other,
485 getI64Imm(Amt), Select(N->getOperand(0)));
486 return SDOperand(N, 0);
490 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
492 switch (N->getNumOperands()) {
494 assert(0 && "Unknown return instruction!");
496 SDOperand RetVal = Select(N->getOperand(1));
497 switch (RetVal.getValueType()) {
498 default: assert(0 && "I don't know how to return this type! (promote?)");
499 // FIXME: do I need to add support for bools here?
500 // (return '0' or '1' in r8, basically...)
502 // FIXME: need to round floats - 80 bits is bad, the tester
505 // we mark r8 as live on exit up above in LowerArguments()
506 // BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
507 Chain = CurDAG->getCopyToReg(Chain, IA64::r8, RetVal);
510 // we mark F8 as live on exit up above in LowerArguments()
511 // BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
512 Chain = CurDAG->getCopyToReg(Chain, IA64::F8, RetVal);
521 // we need to copy VirtGPR (the vreg (to become a real reg)) that holds
522 // the output of this function's alloc instruction back into ar.pfs
523 // before we return. this copy must not float up above the last
524 // outgoing call in this function!!!
525 SDOperand AR_PFSVal = CurDAG->getCopyFromReg(Chain, IA64Lowering.VirtGPR,
527 Chain = AR_PFSVal.getValue(1);
528 Chain = CurDAG->getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
530 CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain); // and then just emit a 'ret' instruction
532 // before returning, restore the ar.pfs register (set by the 'alloc' up top)
533 // BuildMI(BB, IA64::MOV, 1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
535 return SDOperand(N, 0);
539 // FIXME: we don't need long branches all the time!
540 CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, N->getOperand(1),
541 Select(N->getOperand(0)));
542 return SDOperand(N, 0);
546 return SelectCode(Op);
550 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
551 /// into an IA64-specific DAG, ready for instruction scheduling.
553 FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
554 return new IA64DAGToDAGISel(TM);