1 //===----- HexagonShuffler.cpp - Instruction bundle shuffling -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the shuffling of insns inside a bundle according to the
11 // packet formation rules of the Hexagon ISA.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "hexagon-shuffle"
20 #include "MCTargetDesc/HexagonBaseInfo.h"
21 #include "MCTargetDesc/HexagonMCTargetDesc.h"
22 #include "MCTargetDesc/HexagonMCInstrInfo.h"
23 #include "HexagonShuffler.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
31 // Insn shuffling priority.
33 // The priority is directly proportional to how restricted the insn is based
34 // on its flexibility to run on the available slots. So, the fewer slots it
35 // may run on, the higher its priority.
36 enum { MAX = 360360 }; // LCD of 1/2, 1/3, 1/4,... 1/15.
40 HexagonBid() : Bid(0){};
41 HexagonBid(unsigned B) { Bid = B ? MAX / countPopulation(B) : 0; };
43 // Check if the insn priority is overflowed.
44 bool isSold() const { return (Bid >= MAX); };
46 HexagonBid &operator+=(const HexagonBid &B) {
52 // Slot shuffling allocation.
53 class HexagonUnitAuction {
54 HexagonBid Scores[HEXAGON_PACKET_SIZE];
55 // Mask indicating which slot is unavailable.
56 unsigned isSold : HEXAGON_PACKET_SIZE;
59 HexagonUnitAuction() : isSold(0){};
62 bool bid(unsigned B) {
63 // Exclude already auctioned slots from the bid.
64 unsigned b = B & ~isSold;
66 for (unsigned i = 0; i < HEXAGON_PACKET_SIZE; ++i)
68 // Request candidate slots.
69 Scores[i] += HexagonBid(b);
70 isSold |= Scores[i].isSold() << i;
75 // Error if the desired slots are already full.
79 } // end anonymous namespace
81 unsigned HexagonResource::setWeight(unsigned s) {
82 const unsigned SlotWeight = 8;
83 const unsigned MaskWeight = SlotWeight - 1;
84 bool Key = (1 << s) & getUnits();
86 // TODO: Improve this API so that we can prevent misuse statically.
87 assert(SlotWeight * s < 32 && "Argument to setWeight too large.");
89 // Calculate relative weight of the insn for the given slot, weighing it the
90 // heavier the more restrictive the insn is and the lowest the slots that the
91 // insn may be executed in.
93 (Key << (SlotWeight * s)) * ((MaskWeight - countPopulation(getUnits()))
94 << countTrailingZeros(getUnits()));
98 HexagonShuffler::HexagonShuffler(MCInstrInfo const &MCII,
99 MCSubtargetInfo const &STI)
100 : MCII(MCII), STI(STI) {
104 void HexagonShuffler::reset() {
107 Error = SHUFFLE_SUCCESS;
110 void HexagonShuffler::append(MCInst const *ID, MCInst const *Extender,
111 unsigned S, bool X) {
112 HexagonInstr PI(ID, Extender, S, X);
114 Packet.push_back(PI);
117 /// Check that the packet is legal and enforce relative insn order.
118 bool HexagonShuffler::check() {
119 // Descriptive slot masks.
120 const unsigned slotSingleLoad = 0x1, slotSingleStore = 0x1, slotOne = 0x2,
121 slotThree = 0x8, slotFirstJump = 0x8, slotLastJump = 0x4,
122 slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1;
123 // Highest slots for branches and stores used to keep their original order.
124 unsigned slotJump = slotFirstJump;
125 unsigned slotLoadStore = slotFirstLoadStore;
126 // Number of branches, solo branches, indirect branches.
127 unsigned jumps = 0, jump1 = 0, jumpr = 0;
128 // Number of memory operations, loads, solo loads, stores, solo stores, single
130 unsigned memory = 0, loads = 0, load0 = 0, stores = 0, store0 = 0, store1 = 0;
131 // Number of duplex insns, solo insns.
132 unsigned duplex = 0, solo = 0;
133 // Number of insns restricting other insns in the packet to A and X types,
134 // which is neither A or X types.
135 unsigned onlyAX = 0, neitherAnorX = 0;
136 // Number of insns restricting other insns in slot #1 to A type.
137 unsigned onlyAin1 = 0;
138 // Number of insns restricting any insn in slot #1, except A2_nop.
139 unsigned onlyNo1 = 0;
140 unsigned xtypeFloat = 0;
141 unsigned pSlot3Cnt = 0;
142 iterator slot3ISJ = end();
144 // Collect information from the insns in the packet.
145 for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
146 MCInst const *ID = ISJ->getDesc();
148 if (HexagonMCInstrInfo::isSolo(MCII, *ID))
149 solo += !ISJ->isSoloException();
150 else if (HexagonMCInstrInfo::isSoloAX(MCII, *ID))
151 onlyAX += !ISJ->isSoloException();
152 else if (HexagonMCInstrInfo::isSoloAin1(MCII, *ID))
153 onlyAin1 += !ISJ->isSoloException();
154 if (HexagonMCInstrInfo::getType(MCII, *ID) != HexagonII::TypeALU32 &&
155 HexagonMCInstrInfo::getType(MCII, *ID) != HexagonII::TypeXTYPE)
157 if (HexagonMCInstrInfo::prefersSlot3(MCII, *ID)) {
162 switch (HexagonMCInstrInfo::getType(MCII, *ID)) {
163 case HexagonII::TypeXTYPE:
164 if (HexagonMCInstrInfo::isFloat(MCII, *ID))
167 case HexagonII::TypeJR:
170 case HexagonII::TypeJ:
173 case HexagonII::TypeLD:
176 if (ISJ->Core.getUnits() == slotSingleLoad)
178 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isReturn())
179 ++jumps, ++jump1; // DEALLOC_RETURN is of type LD.
181 case HexagonII::TypeST:
184 if (ISJ->Core.getUnits() == slotSingleStore)
187 case HexagonII::TypeMEMOP:
193 case HexagonII::TypeNV:
194 ++memory; // NV insns are memory-like.
195 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch())
198 case HexagonII::TypeCR:
199 // Legacy conditional branch predicated on a register.
200 case HexagonII::TypeSYSTEM:
201 if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad())
207 // Check if the packet is legal.
208 if ((load0 > 1 || store0 > 1) || (duplex > 1 || (duplex && memory)) ||
209 (solo && size() > 1) || (onlyAX && neitherAnorX > 1) ||
210 (onlyAX && xtypeFloat)) {
211 Error = SHUFFLE_ERROR_INVALID;
215 if (jump1 && jumps > 1) {
216 // Error if single branch with another branch.
217 Error = SHUFFLE_ERROR_BRANCHES;
221 // Modify packet accordingly.
222 // TODO: need to reserve slots #0 and #1 for duplex insns.
223 bool bOnlySlot3 = false;
224 for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
225 MCInst const *ID = ISJ->getDesc();
227 if (!ISJ->Core.getUnits()) {
228 // Error if insn may not be executed in any slot.
229 Error = SHUFFLE_ERROR_UNKNOWN;
233 // Exclude from slot #1 any insn but A2_nop.
234 if (HexagonMCInstrInfo::getDesc(MCII, *ID).getOpcode() != Hexagon::A2_nop)
236 ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne);
238 // Exclude from slot #1 any insn but A-type.
239 if (HexagonMCInstrInfo::getType(MCII, *ID) != HexagonII::TypeALU32)
241 ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne);
243 // Branches must keep the original order.
244 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch() ||
245 HexagonMCInstrInfo::getDesc(MCII, *ID).isCall())
247 if (jumpr || slotJump < slotLastJump) {
248 // Error if indirect branch with another branch or
249 // no more slots available for branches.
250 Error = SHUFFLE_ERROR_BRANCHES;
253 // Pin the branch to the highest slot available to it.
254 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotJump);
255 // Update next highest slot available to branches.
259 // A single load must use slot #0.
260 if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad()) {
261 if (loads == 1 && loads == memory)
262 // Pin the load to slot #0.
263 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad);
266 // A single store must use slot #0.
267 if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayStore()) {
270 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore);
271 else if (stores > 1) {
272 if (slotLoadStore < slotLastLoadStore) {
273 // Error if no more slots available for stores.
274 Error = SHUFFLE_ERROR_STORES;
277 // Pin the store to the highest slot available to it.
278 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore);
279 // Update the next highest slot available to stores.
283 if (store1 && stores > 1) {
284 // Error if a single store with another store.
285 Error = SHUFFLE_ERROR_STORES;
290 // flag if an instruction can only be executed in slot 3
291 if (ISJ->Core.getUnits() == slotThree)
294 if (!ISJ->Core.getUnits()) {
295 // Error if insn may not be executed in any slot.
296 Error = SHUFFLE_ERROR_NOSLOTS;
301 bool validateSlots = true;
302 if (bOnlySlot3 == false && pSlot3Cnt == 1 && slot3ISJ != end()) {
303 // save off slot mask of instruction marked with A_PREFER_SLOT3
304 // and then pin it to slot #3
305 unsigned saveUnits = slot3ISJ->Core.getUnits();
306 slot3ISJ->Core.setUnits(saveUnits & slotThree);
308 HexagonUnitAuction AuctionCore;
309 std::sort(begin(), end(), HexagonInstr::lessCore);
311 // see if things ok with that instruction being pinned to slot #3
313 for (iterator I = begin(); I != end() && bFail != true; ++I)
314 if (!AuctionCore.bid(I->Core.getUnits()))
317 // if yes, great, if not then restore original slot mask
319 validateSlots = false; // all good, no need to re-do auction
321 for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
322 MCInst const *ID = ISJ->getDesc();
323 if (HexagonMCInstrInfo::prefersSlot3(MCII, *ID))
324 ISJ->Core.setUnits(saveUnits);
328 // Check if any slot, core, is over-subscribed.
329 // Verify the core slot subscriptions.
331 HexagonUnitAuction AuctionCore;
333 std::sort(begin(), end(), HexagonInstr::lessCore);
335 for (iterator I = begin(); I != end(); ++I)
336 if (!AuctionCore.bid(I->Core.getUnits())) {
337 Error = SHUFFLE_ERROR_SLOTS;
342 Error = SHUFFLE_SUCCESS;
346 bool HexagonShuffler::shuffle() {
347 if (size() > HEXAGON_PACKET_SIZE) {
348 // Ignore a packet with with more than what a packet can hold
349 // or with compound or duplex insns for now.
350 Error = SHUFFLE_ERROR_INVALID;
354 // Check and prepare packet.
355 if (size() > 1 && check())
356 // Reorder the handles for each slot.
357 for (unsigned nSlot = 0, emptySlots = 0; nSlot < HEXAGON_PACKET_SIZE;
360 unsigned slotSkip, slotWeight;
362 // Prioritize the handles considering their restrictions.
363 for (ISJ = ISK = Packet.begin(), slotSkip = slotWeight = 0;
364 ISK != Packet.end(); ++ISK, ++slotSkip)
365 if (slotSkip < nSlot - emptySlots)
366 // Note which handle to begin at.
369 // Calculate the weight of the slot.
370 slotWeight += ISK->Core.setWeight(HEXAGON_PACKET_SIZE - nSlot - 1);
373 // Sort the packet, favoring source order,
374 // beginning after the previous slot.
375 std::sort(ISJ, Packet.end());
381 for (iterator ISJ = begin(); ISJ != end(); ++ISJ)
382 DEBUG(dbgs().write_hex(ISJ->Core.getUnits());
384 << HexagonMCInstrInfo::getDesc(MCII, *ISJ->getDesc())
387 DEBUG(dbgs() << '\n');
389 return (!getError());