1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "MCTargetDesc/HexagonBaseInfo.h"
12 #include "MCTargetDesc/HexagonFixupKinds.h"
13 #include "MCTargetDesc/HexagonMCCodeEmitter.h"
14 #include "MCTargetDesc/HexagonMCInstrInfo.h"
15 #include "MCTargetDesc/HexagonMCTargetDesc.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/EndianStream.h"
26 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mccodeemitter"
31 using namespace Hexagon;
33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
37 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
38 Extended(new bool(false)), CurrentBundle(new MCInst const *) {}
40 uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last,
42 MCInst const &MCI) const {
43 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
44 if (Instruction == 0) {
45 if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
47 assert(Instruction != Last);
48 return HexagonII::INST_PARSE_LOOP_END;
51 if (Instruction == 1) {
52 if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
54 assert(Instruction != Last);
55 return HexagonII::INST_PARSE_LOOP_END;
59 assert(Instruction == Last);
60 return HexagonII::INST_PARSE_DUPLEX;
62 if(Instruction == Last)
63 return HexagonII::INST_PARSE_PACKET_END;
64 return HexagonII::INST_PARSE_NOT_END;
67 void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS,
68 SmallVectorImpl<MCFixup> &Fixups,
69 MCSubtargetInfo const &STI) const {
70 MCInst &HMB = const_cast<MCInst &>(MI);
72 assert(HexagonMCInstrInfo::isBundle(HMB));
73 DEBUG(dbgs() << "Encoding bundle\n";);
77 size_t Instruction = 0;
78 size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
79 for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
80 MCInst &HMI = const_cast<MCInst &>(*I.getInst());
81 EncodeSingleInstruction(HMI, OS, Fixups, STI,
82 parseBits(Instruction, Last, HMB, HMI),
84 *Extended = HexagonMCInstrInfo::isImmext(HMI);
85 *Addend += HEXAGON_INSTR_SIZE;
91 /// EncodeSingleInstruction - Emit a single
92 void HexagonMCCodeEmitter::EncodeSingleInstruction(
93 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
94 const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const {
96 assert(!HexagonMCInstrInfo::isBundle(HMB));
99 // Pseudo instructions don't get encoded and shouldn't be here
100 // in the first place!
101 assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() &&
102 "pseudo-instruction found");
103 DEBUG(dbgs() << "Encoding insn"
104 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
107 if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) {
108 // Calculate the new value distance to the associated producer
110 HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB));
111 unsigned SOffset = 0;
112 unsigned Register = MCO.getReg();
114 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
115 auto i = Instructions.begin() + Index - 1;
117 assert(i != Instructions.begin() - 1 && "Couldn't find producer");
118 MCInst const &Inst = *i->getInst();
119 if (HexagonMCInstrInfo::isImmext(Inst))
123 HexagonMCInstrInfo::hasNewValue(MCII, Inst)
124 ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg()
125 : static_cast<unsigned>(Hexagon::NoRegister);
126 if (Register != Register1)
127 // This isn't the register we're looking for
129 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
130 // Producer is unpredicated
132 assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) &&
133 "Unpredicated consumer depending on predicated producer");
134 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
135 HexagonMCInstrInfo::isPredicatedTrue(MCII, HMB))
136 // Producer predicate sense matched ours
139 // Hexagon PRM 10.11 Construct Nt from distance
140 unsigned Offset = SOffset;
142 MCO.setReg(Offset + Hexagon::R0);
145 Binary = getBinaryCodeForInstr(HMB, Fixups, STI);
146 // Check for unimplemented instructions. Immediate extenders
147 // are encoded as zero, so they need to be accounted for.
149 ((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) &&
150 (HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) &&
151 (HMB.getOpcode() != A4_ext_g))) {
152 // Use a A2_nop for unimplemented instructions.
153 DEBUG(dbgs() << "Unimplemented inst: "
154 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
156 llvm_unreachable("Unimplemented Instruction");
160 // if we need to emit a duplexed instruction
161 if (HMB.getOpcode() >= Hexagon::DuplexIClass0 &&
162 HMB.getOpcode() <= Hexagon::DuplexIClassF) {
163 assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
164 "Emitting duplex without duplex parse bits");
166 switch (HMB.getOpcode()) {
167 case Hexagon::DuplexIClass0:
170 case Hexagon::DuplexIClass1:
173 case Hexagon::DuplexIClass2:
176 case Hexagon::DuplexIClass3:
179 case Hexagon::DuplexIClass4:
182 case Hexagon::DuplexIClass5:
185 case Hexagon::DuplexIClass6:
188 case Hexagon::DuplexIClass7:
191 case Hexagon::DuplexIClass8:
194 case Hexagon::DuplexIClass9:
197 case Hexagon::DuplexIClassA:
200 case Hexagon::DuplexIClassB:
203 case Hexagon::DuplexIClassC:
206 case Hexagon::DuplexIClassD:
209 case Hexagon::DuplexIClassE:
212 case Hexagon::DuplexIClassF:
216 llvm_unreachable("Unimplemented DuplexIClass");
219 // 29 is the bit position.
220 // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
221 // Last bit is moved to bit position 13
222 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
224 const MCInst *subInst0 = HMB.getOperand(0).getInst();
225 const MCInst *subInst1 = HMB.getOperand(1).getInst();
227 // get subinstruction slot 0
228 unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
229 // get subinstruction slot 1
230 unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
232 Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
234 support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
238 static Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
240 const MCSymbolRefExpr::VariantKind kind) {
241 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
242 unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
244 if (insnType == HexagonII::TypePREFIX) {
246 case llvm::MCSymbolRefExpr::VK_GOTOFF:
247 return Hexagon::fixup_Hexagon_GOTREL_32_6_X;
248 case llvm::MCSymbolRefExpr::VK_GOT:
249 return Hexagon::fixup_Hexagon_GOT_32_6_X;
250 case llvm::MCSymbolRefExpr::VK_TPREL:
251 return Hexagon::fixup_Hexagon_TPREL_32_6_X;
252 case llvm::MCSymbolRefExpr::VK_DTPREL:
253 return Hexagon::fixup_Hexagon_DTPREL_32_6_X;
254 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
255 return Hexagon::fixup_Hexagon_GD_GOT_32_6_X;
256 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
257 return Hexagon::fixup_Hexagon_LD_GOT_32_6_X;
258 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
259 return Hexagon::fixup_Hexagon_IE_32_6_X;
260 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
261 return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
264 return Hexagon::fixup_Hexagon_B32_PCREL_X;
266 return Hexagon::fixup_Hexagon_32_6_X;
268 } else if (MCID.isBranch())
269 return (Hexagon::fixup_Hexagon_B13_PCREL);
271 switch (MCID.getOpcode()) {
273 case Hexagon::A2_tfrih:
275 case llvm::MCSymbolRefExpr::VK_GOT:
276 return Hexagon::fixup_Hexagon_GOT_HI16;
277 case llvm::MCSymbolRefExpr::VK_GOTOFF:
278 return Hexagon::fixup_Hexagon_GOTREL_HI16;
279 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
280 return Hexagon::fixup_Hexagon_GD_GOT_HI16;
281 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
282 return Hexagon::fixup_Hexagon_LD_GOT_HI16;
283 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
284 return Hexagon::fixup_Hexagon_IE_HI16;
285 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
286 return Hexagon::fixup_Hexagon_IE_GOT_HI16;
287 case llvm::MCSymbolRefExpr::VK_TPREL:
288 return Hexagon::fixup_Hexagon_TPREL_HI16;
289 case llvm::MCSymbolRefExpr::VK_DTPREL:
290 return Hexagon::fixup_Hexagon_DTPREL_HI16;
292 return Hexagon::fixup_Hexagon_HI16;
296 case Hexagon::A2_tfril:
298 case llvm::MCSymbolRefExpr::VK_GOT:
299 return Hexagon::fixup_Hexagon_GOT_LO16;
300 case llvm::MCSymbolRefExpr::VK_GOTOFF:
301 return Hexagon::fixup_Hexagon_GOTREL_LO16;
302 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
303 return Hexagon::fixup_Hexagon_GD_GOT_LO16;
304 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
305 return Hexagon::fixup_Hexagon_LD_GOT_LO16;
306 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
307 return Hexagon::fixup_Hexagon_IE_LO16;
308 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
309 return Hexagon::fixup_Hexagon_IE_GOT_LO16;
310 case llvm::MCSymbolRefExpr::VK_TPREL:
311 return Hexagon::fixup_Hexagon_TPREL_LO16;
312 case llvm::MCSymbolRefExpr::VK_DTPREL:
313 return Hexagon::fixup_Hexagon_DTPREL_LO16;
315 return Hexagon::fixup_Hexagon_LO16;
318 // The only relocs left should be GP relative:
320 if (MCID.mayStore() || MCID.mayLoad()) {
321 for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses;
323 if (*ImpUses == Hexagon::GP) {
324 switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
325 case HexagonII::MemAccessSize::ByteAccess:
326 return fixup_Hexagon_GPREL16_0;
327 case HexagonII::MemAccessSize::HalfWordAccess:
328 return fixup_Hexagon_GPREL16_1;
329 case HexagonII::MemAccessSize::WordAccess:
330 return fixup_Hexagon_GPREL16_2;
331 case HexagonII::MemAccessSize::DoubleWordAccess:
332 return fixup_Hexagon_GPREL16_3;
334 llvm_unreachable("unhandled fixup");
339 llvm_unreachable("unhandled fixup");
342 return LastTargetFixupKind;
345 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
348 SmallVectorImpl<MCFixup> &Fixups,
349 const MCSubtargetInfo &STI) const
354 if (ME->evaluateAsAbsolute(Res))
357 MCExpr::ExprKind MK = ME->getKind();
358 if (MK == MCExpr::Constant) {
359 return cast<MCConstantExpr>(ME)->getValue();
361 if (MK == MCExpr::Binary) {
363 Res = getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getLHS(), Fixups, STI);
365 getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getRHS(), Fixups, STI);
369 assert(MK == MCExpr::SymbolRef);
371 Hexagon::Fixups FixupKind =
372 Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16);
373 const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
374 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
375 unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
376 HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
377 const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
379 DEBUG(dbgs() << "----------------------------------------\n");
380 DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
382 DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
383 DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
384 DEBUG(dbgs() << "Addend: " << *Addend << "\n");
385 DEBUG(dbgs() << "----------------------------------------\n");
389 DEBUG(dbgs() << "unrecognized bit count of " << bits << '\n');
394 case llvm::MCSymbolRefExpr::VK_Hexagon_PCREL:
395 FixupKind = Hexagon::fixup_Hexagon_32_PCREL;
397 case llvm::MCSymbolRefExpr::VK_GOT:
398 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
399 : Hexagon::fixup_Hexagon_GOT_32;
401 case llvm::MCSymbolRefExpr::VK_GOTOFF:
402 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
403 : Hexagon::fixup_Hexagon_GOTREL_32;
405 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
406 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
407 : Hexagon::fixup_Hexagon_GD_GOT_32;
409 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
410 FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
411 : Hexagon::fixup_Hexagon_LD_GOT_32;
413 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
414 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
415 : Hexagon::fixup_Hexagon_IE_32;
417 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
418 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
419 : Hexagon::fixup_Hexagon_IE_GOT_32;
421 case llvm::MCSymbolRefExpr::VK_TPREL:
422 FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
423 : Hexagon::fixup_Hexagon_TPREL_32;
425 case llvm::MCSymbolRefExpr::VK_DTPREL:
426 FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
427 : Hexagon::fixup_Hexagon_DTPREL_32;
431 *Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32;
438 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_PLT:
439 FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
441 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_PLT:
442 FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
445 if (MCID.isBranch() || MCID.isCall()) {
446 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
447 : Hexagon::fixup_Hexagon_B22_PCREL;
449 errs() << "unrecognized relocation, bits: " << bits << "\n";
450 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
460 FixupKind = Hexagon::fixup_Hexagon_16_X;
462 case llvm::MCSymbolRefExpr::VK_GOT:
463 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
465 case llvm::MCSymbolRefExpr::VK_GOTOFF:
466 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
468 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
469 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X;
471 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
472 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X;
474 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
475 FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
477 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
478 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X;
480 case llvm::MCSymbolRefExpr::VK_TPREL:
481 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
483 case llvm::MCSymbolRefExpr::VK_DTPREL:
484 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
490 errs() << "unrecognized relocation, bits " << bits << "\n";
491 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
493 case llvm::MCSymbolRefExpr::VK_GOTOFF:
494 if ((MCID.getOpcode() == Hexagon::HI) ||
495 (MCID.getOpcode() == Hexagon::LO_H))
496 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
498 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
500 case llvm::MCSymbolRefExpr::VK_Hexagon_GPREL:
501 FixupKind = Hexagon::fixup_Hexagon_GPREL16_0;
503 case llvm::MCSymbolRefExpr::VK_Hexagon_LO16:
504 FixupKind = Hexagon::fixup_Hexagon_LO16;
506 case llvm::MCSymbolRefExpr::VK_Hexagon_HI16:
507 FixupKind = Hexagon::fixup_Hexagon_HI16;
509 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
510 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16;
512 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
513 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16;
515 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
516 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16;
518 case llvm::MCSymbolRefExpr::VK_TPREL:
519 FixupKind = Hexagon::fixup_Hexagon_TPREL_16;
521 case llvm::MCSymbolRefExpr::VK_DTPREL:
522 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16;
528 if (MCID.isBranch() || MCID.isCall())
529 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
530 : Hexagon::fixup_Hexagon_B15_PCREL;
535 FixupKind = Hexagon::fixup_Hexagon_B13_PCREL;
537 errs() << "unrecognized relocation, bits " << bits << "\n";
538 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
546 FixupKind = Hexagon::fixup_Hexagon_12_X;
548 // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
549 case llvm::MCSymbolRefExpr::VK_GOT:
550 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
552 case llvm::MCSymbolRefExpr::VK_GOTOFF:
553 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
557 errs() << "unrecognized relocation, bits " << bits << "\n";
558 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
566 FixupKind = Hexagon::fixup_Hexagon_11_X;
568 case llvm::MCSymbolRefExpr::VK_GOT:
569 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
571 case llvm::MCSymbolRefExpr::VK_GOTOFF:
572 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
574 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
575 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X;
577 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
578 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X;
580 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
581 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X;
583 case llvm::MCSymbolRefExpr::VK_TPREL:
584 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
586 case llvm::MCSymbolRefExpr::VK_DTPREL:
587 FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X;
591 errs() << "unrecognized relocation, bits " << bits << "\n";
592 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
598 FixupKind = Hexagon::fixup_Hexagon_10_X;
602 if (MCID.isBranch() ||
603 (llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
604 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
605 : Hexagon::fixup_Hexagon_B9_PCREL;
607 FixupKind = Hexagon::fixup_Hexagon_9_X;
609 errs() << "unrecognized relocation, bits " << bits << "\n";
610 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
616 FixupKind = Hexagon::fixup_Hexagon_8_X;
618 errs() << "unrecognized relocation, bits " << bits << "\n";
619 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
624 if (MCID.isBranch() ||
625 (llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
626 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
627 : Hexagon::fixup_Hexagon_B7_PCREL;
629 FixupKind = Hexagon::fixup_Hexagon_7_X;
631 errs() << "unrecognized relocation, bits " << bits << "\n";
632 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
640 FixupKind = Hexagon::fixup_Hexagon_6_X;
642 case llvm::MCSymbolRefExpr::VK_Hexagon_PCREL:
643 FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X;
645 // This is part of an extender, GOT_11 is a
646 // Word32_U6 unsigned/truncated reloc.
647 case llvm::MCSymbolRefExpr::VK_GOT:
648 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
650 case llvm::MCSymbolRefExpr::VK_GOTOFF:
651 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
655 errs() << "unrecognized relocation, bits " << bits << "\n";
656 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
661 FixupKind = getFixupNoBits(MCII, MI, MO, kind);
666 MCFixup::create(*Addend, MO.getExpr(), MCFixupKind(FixupKind));
667 Fixups.push_back(fixup);
668 // All of the information is in the fixup.
673 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
674 SmallVectorImpl<MCFixup> &Fixups,
675 MCSubtargetInfo const &STI) const {
677 return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
679 return static_cast<unsigned>(MO.getImm());
683 return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
686 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
687 MCRegisterInfo const &MRI,
689 return new HexagonMCCodeEmitter(MII, MCT);
692 #include "HexagonGenMCCodeEmitter.inc"