1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "MCTargetDesc/HexagonBaseInfo.h"
12 #include "MCTargetDesc/HexagonMCCodeEmitter.h"
13 #include "MCTargetDesc/HexagonMCInst.h"
14 #include "MCTargetDesc/HexagonMCInstrInfo.h"
15 #include "MCTargetDesc/HexagonMCTargetDesc.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "mccodeemitter"
30 using namespace Hexagon;
32 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 /// \brief 10.6 Instruction Packets
36 /// Possible values for instruction packet parse field.
37 enum class ParseField { duplex = 0x0, last0 = 0x1, last1 = 0x2, end = 0x3 };
38 /// \brief Returns the packet bits based on instruction position.
39 uint32_t getPacketBits(HexagonMCInst const &HMI) {
40 unsigned const ParseFieldOffset = 14;
41 ParseField Field = HMI.isPacketEnd() ? ParseField::end : ParseField::last0;
42 return static_cast <uint32_t> (Field) << ParseFieldOffset;
44 void emitLittleEndian(uint64_t Binary, raw_ostream &OS) {
45 OS << static_cast<uint8_t>((Binary >> 0x00) & 0xff);
46 OS << static_cast<uint8_t>((Binary >> 0x08) & 0xff);
47 OS << static_cast<uint8_t>((Binary >> 0x10) & 0xff);
48 OS << static_cast<uint8_t>((Binary >> 0x18) & 0xff);
52 HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
53 MCSubtargetInfo const &aMST,
55 : MST(aMST), MCT(aMCT), MCII (aMII) {}
57 void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS,
58 SmallVectorImpl<MCFixup> &Fixups,
59 MCSubtargetInfo const &STI) const {
60 HexagonMCInst const &HMB = static_cast<HexagonMCInst const &>(MI);
61 uint64_t Binary = getBinaryCodeForInstr(HMB, Fixups, STI) | getPacketBits(HMB);
62 assert(HexagonMCInstrInfo::getDesc(MCII, HMB).getSize() == 4 &&
63 "All instructions should be 32bit");
64 emitLittleEndian(Binary, OS);
69 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
70 SmallVectorImpl<MCFixup> &Fixups,
71 MCSubtargetInfo const &STI) const {
73 return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
75 return static_cast<unsigned>(MO.getImm());
76 llvm_unreachable("Only Immediates and Registers implemented right now");
79 MCSubtargetInfo const &HexagonMCCodeEmitter::getSubtargetInfo() const {
83 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
84 MCRegisterInfo const &MRI,
85 MCSubtargetInfo const &MST,
87 return new HexagonMCCodeEmitter(MII, MST, MCT);
90 #include "HexagonGenMCCodeEmitter.inc"