1 //===----- HexagonMCChecker.h - Instruction bundle checking ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the checking of insns inside a bundle according to the
11 // packet constraint rules of the Hexagon ISA.
13 //===----------------------------------------------------------------------===//
15 #ifndef HEXAGONMCCHECKER_H
16 #define HEXAGONMCCHECKER_H
21 #include "MCTargetDesc/HexagonMCShuffler.h"
29 unsigned Error, Warning, ShuffleError;
33 class HexagonMCErrInfo {
38 CHECK_ERROR_BRANCHES = 0x00001,
39 CHECK_ERROR_NEWP = 0x00002,
40 CHECK_ERROR_NEWV = 0x00004,
41 CHECK_ERROR_REGISTERS = 0x00008,
42 CHECK_ERROR_READONLY = 0x00010,
43 CHECK_ERROR_LOOP = 0x00020,
44 CHECK_ERROR_ENDLOOP = 0x00040,
45 CHECK_ERROR_SOLO = 0x00080,
46 CHECK_ERROR_SHUFFLE = 0x00100,
47 CHECK_ERROR_NOSLOTS = 0x00200,
48 CHECK_ERROR_UNKNOWN = 0x00400,
50 CHECK_WARN_CURRENT = 0x10000,
51 CHECK_WARN_TEMPORARY = 0x20000
56 s.Error = CHECK_SUCCESS;
57 s.Warning = CHECK_SUCCESS;
58 s.ShuffleError = HexagonShuffler::SHUFFLE_SUCCESS;
59 s.Register = Hexagon::NoRegister;
65 void setError(unsigned e, unsigned r = Hexagon::NoRegister)
66 { s.Error = e; s.Register = r; };
67 void setWarning(unsigned w, unsigned r = Hexagon::NoRegister)
68 { s.Warning = w; s.Register = r; };
69 void setShuffleError(unsigned e) { s.ShuffleError = e; };
72 /// Check for a valid bundle.
73 class HexagonMCChecker {
77 const MCRegisterInfo& RI;
78 MCInstrInfo const &MCII;
79 MCSubtargetInfo const &STI;
82 /// Set of definitions: register #, if predicated, if predicated true.
83 typedef std::pair<unsigned, bool> PredSense;
84 static const PredSense Unconditional;
85 typedef std::multiset<PredSense> PredSet;
86 typedef std::multiset<PredSense>::iterator PredSetIterator;
88 typedef llvm::DenseMap<unsigned, PredSet>::iterator DefsIterator;
89 llvm::DenseMap<unsigned, PredSet> Defs;
91 /// Information about how a new-value register is defined or used:
92 /// PredReg = predicate register, 0 if use/def not predicated,
93 /// Cond = true/false for if(PredReg)/if(!PredReg) respectively,
94 /// IsFloat = true if definition produces a floating point value
95 /// (not valid for uses),
96 /// IsNVJ = true if the use is a new-value branch (not valid for
100 bool IsFloat, IsNVJ, Cond;
101 // The special-case "constructors":
102 static NewSense Jmp(bool isNVJ) {
103 NewSense NS = { /*PredReg=*/ 0, /*IsFloat=*/ false, /*IsNVJ=*/ isNVJ,
107 static NewSense Use(unsigned PR, bool True) {
108 NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ false, /*IsNVJ=*/ false,
112 static NewSense Def(unsigned PR, bool True, bool Float) {
113 NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ Float, /*IsNVJ=*/ false,
118 /// Set of definitions that produce new register:
119 typedef llvm::SmallVector<NewSense,2> NewSenseList;
120 typedef llvm::DenseMap<unsigned, NewSenseList>::iterator NewDefsIterator;
121 llvm::DenseMap<unsigned, NewSenseList> NewDefs;
123 /// Set of weak definitions whose clashes should be enforced selectively.
124 typedef std::set<unsigned>::iterator SoftDefsIterator;
125 std::set<unsigned> SoftDefs;
127 /// Set of current definitions committed to the register file.
128 typedef std::set<unsigned>::iterator CurDefsIterator;
129 std::set<unsigned> CurDefs;
131 /// Set of temporary definitions not committed to the register file.
132 typedef std::set<unsigned>::iterator TmpDefsIterator;
133 std::set<unsigned> TmpDefs;
135 /// Set of new predicates used.
136 typedef std::set<unsigned>::iterator NewPredsIterator;
137 std::set<unsigned> NewPreds;
139 /// Set of predicates defined late.
140 typedef std::multiset<unsigned>::iterator LatePredsIterator;
141 std::multiset<unsigned> LatePreds;
144 typedef std::set<unsigned>::iterator UsesIterator;
145 std::set<unsigned> Uses;
147 /// Set of new values used: new register, if new-value jump.
148 typedef llvm::DenseMap<unsigned, NewSense>::iterator NewUsesIterator;
149 llvm::DenseMap<unsigned, NewSense> NewUses;
151 /// Pre-defined set of read-only registers.
152 typedef std::set<unsigned>::iterator ReadOnlyIterator;
153 std::set<unsigned> ReadOnly;
155 std::queue<ErrInfo_T> ErrInfoQ;
156 HexagonMCErrInfo CrntErrInfo;
159 if (bLoadErrInfo == true) {
160 if (ErrInfoQ.empty()) {
163 CrntErrInfo.s = ErrInfoQ.front();
167 bLoadErrInfo = false;
171 void init(MCInst const&);
174 bool checkBranches();
175 bool checkPredicates();
176 bool checkNewValues();
177 bool checkRegisters();
182 static void compoundRegisterMap(unsigned&);
184 bool isPredicateRegister(unsigned R) const {
185 return (Hexagon::P0 == R || Hexagon::P1 == R ||
186 Hexagon::P2 == R || Hexagon::P3 == R);
188 bool isLoopRegister(unsigned R) const {
189 return (Hexagon::SA0 == R || Hexagon::LC0 == R ||
190 Hexagon::SA1 == R || Hexagon::LC1 == R);
193 bool hasValidNewValueDef(const NewSense &Use,
194 const NewSenseList &Defs) const;
197 explicit HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst& mcb, MCInst &mcbdx,
198 const MCRegisterInfo& ri);
202 /// add a new error/warning
203 void addErrInfo(HexagonMCErrInfo &err) { ErrInfoQ.push(err.s); };
205 /// Return the error code for the last operation in the insn bundle.
206 unsigned getError() { getErrInfo(); return CrntErrInfo.s.Error; };
207 unsigned getWarning() { getErrInfo(); return CrntErrInfo.s.Warning; };
208 unsigned getShuffleError() { getErrInfo(); return CrntErrInfo.s.ShuffleError; };
209 unsigned getErrRegister() { getErrInfo(); return CrntErrInfo.s.Register; };
210 bool getNextErrInfo() {
212 return (ErrInfoQ.empty()) ? false : (getErrInfo(), true);
218 #endif // HEXAGONMCCHECKER_H