1 //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an Hexagon MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonAsmPrinter.h"
16 #include "HexagonInstPrinter.h"
17 #include "MCTargetDesc/HexagonMCInst.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/Support/raw_ostream.h"
26 #define DEBUG_TYPE "asm-printer"
28 #define GET_INSTRUCTION_NAME
29 #include "HexagonGenAsmWriter.inc"
31 const char HexagonInstPrinter::PacketPadding = '\t';
32 // Return the minimum value that a constant extendable operand can have
33 // without being extended.
34 static int getMinValue(uint64_t TSFlags) {
36 (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
38 (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
41 return -1U << (bits - 1);
46 // Return the maximum value that a constant extendable operand can have
47 // without being extended.
48 static int getMaxValue(uint64_t TSFlags) {
50 (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
52 (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
55 return ~(-1U << (bits - 1));
57 return ~(-1U << bits);
60 // Return true if the instruction must be extended.
61 static bool isExtended(uint64_t TSFlags) {
62 return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
65 // Currently just used in an assert statement
66 static bool isExtendable(uint64_t TSFlags) LLVM_ATTRIBUTE_UNUSED;
67 // Return true if the instruction may be extended based on the operand value.
68 static bool isExtendable(uint64_t TSFlags) {
69 return (TSFlags >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
72 StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {
73 return MII.getName(Opcode);
76 StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const {
77 return getRegisterName(RegNo);
80 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
82 printInst((const HexagonMCInst*)(MI), O, Annot);
85 void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O,
87 const char startPacket = '{',
89 // TODO: add outer HW loop when it's supported too.
90 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
91 // Ending a harware loop is different from ending an regular packet.
92 assert(MI->isPacketEnd() && "Loop-end must also end the packet");
94 if (MI->isPacketBegin()) {
95 // There must be a packet to end a loop.
96 // FIXME: when shuffling is always run, this shouldn't be needed.
97 HexagonMCInst Nop (Hexagon::NOP);
100 Nop.setPacketBegin (MI->isPacketBegin());
101 printInst (&Nop, O, NoAnnot);
105 if (MI->isPacketEnd())
106 O << PacketPadding << endPacket;
108 printInstruction(MI, O);
111 // Prefix the insn opening the packet.
112 if (MI->isPacketBegin())
113 O << PacketPadding << startPacket << '\n';
115 printInstruction(MI, O);
117 // Suffix the insn closing the packet.
118 if (MI->isPacketEnd())
119 // Suffix the packet in a new line always, since the GNU assembler has
120 // issues with a closing brace on the same line as CONST{32,64}.
121 O << '\n' << PacketPadding << endPacket;
124 printAnnotation(O, Annot);
127 void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
128 raw_ostream &O) const {
129 const MCOperand& MO = MI->getOperand(OpNo);
132 O << getRegisterName(MO.getReg());
133 } else if(MO.isExpr()) {
135 } else if(MO.isImm()) {
136 printImmOperand(MI, OpNo, O);
138 llvm_unreachable("Unknown operand");
142 void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,
143 raw_ostream &O) const {
144 const MCOperand& MO = MI->getOperand(OpNo);
148 } else if(MO.isImm()) {
149 O << MI->getOperand(OpNo).getImm();
151 llvm_unreachable("Unknown operand");
155 void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,
156 raw_ostream &O) const {
157 const MCOperand &MO = MI->getOperand(OpNo);
158 const MCInstrDesc &MII = getMII().get(MI->getOpcode());
160 assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&
161 "Expecting an extendable operand");
163 if (MO.isExpr() || isExtended(MII.TSFlags)) {
165 } else if (MO.isImm()) {
166 int ImmValue = MO.getImm();
167 if (ImmValue < getMinValue(MII.TSFlags) ||
168 ImmValue > getMaxValue(MII.TSFlags))
171 printOperand(MI, OpNo, O);
174 void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,
175 unsigned OpNo, raw_ostream &O) const {
176 O << MI->getOperand(OpNo).getImm();
179 void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,
180 raw_ostream &O) const {
181 O << -MI->getOperand(OpNo).getImm();
184 void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,
185 raw_ostream &O) const {
189 void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,
190 raw_ostream &O) const {
191 const MCOperand& MO0 = MI->getOperand(OpNo);
192 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
194 O << getRegisterName(MO0.getReg());
195 O << " + #" << MO1.getImm();
198 void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,
199 raw_ostream &O) const {
200 const MCOperand& MO0 = MI->getOperand(OpNo);
201 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
203 O << getRegisterName(MO0.getReg()) << ", #" << MO1.getImm();
206 void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,
207 raw_ostream &O) const {
208 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
210 printOperand(MI, OpNo, O);
213 void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,
214 raw_ostream &O) const {
215 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
217 printOperand(MI, OpNo, O);
220 void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,
221 raw_ostream &O) const {
222 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
224 printOperand(MI, OpNo, O);
227 void HexagonInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
228 raw_ostream &O) const {
229 // Branches can take an immediate operand. This is used by the branch
230 // selection pass to print $+8, an eight byte displacement from the PC.
231 llvm_unreachable("Unknown branch operand.");
234 void HexagonInstPrinter::printCallOperand(const MCInst *MI, unsigned OpNo,
235 raw_ostream &O) const {
238 void HexagonInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,
239 raw_ostream &O) const {
242 void HexagonInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
243 raw_ostream &O) const {
246 void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,
247 raw_ostream &O, bool hi) const {
248 assert(MI->getOperand(OpNo).isImm() && "Unknown symbol operand");
250 O << '#' << (hi ? "HI" : "LO") << "(#";
251 printOperand(MI, OpNo, O);