1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "packets"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/ScheduleDAG.h"
26 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
27 #include "llvm/CodeGen/LatencyPriorityQueue.h"
28 #include "llvm/CodeGen/SchedulerRegistry.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/Statistic.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/MC/MCInstrItineraries.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
45 #include "HexagonTargetMachine.h"
46 #include "HexagonRegisterInfo.h"
47 #include "HexagonSubtarget.h"
48 #include "HexagonMachineFunctionInfo.h"
55 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
56 cl::ZeroOrMore, cl::Hidden, cl::init(true),
57 cl::desc("Allow non-solo packetization of volatile memory references"));
59 extern cl::opt<bool> ScheduleInlineAsm;
60 extern cl::opt<bool> CountDeadOutput;
63 void initializeHexagonPacketizerPass(PassRegistry&);
68 class HexagonPacketizer : public MachineFunctionPass {
72 HexagonPacketizer() : MachineFunctionPass(ID) {
73 initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry());
76 void getAnalysisUsage(AnalysisUsage &AU) const {
78 AU.addRequired<MachineDominatorTree>();
79 AU.addRequired<MachineBranchProbabilityInfo>();
80 AU.addPreserved<MachineDominatorTree>();
81 AU.addRequired<MachineLoopInfo>();
82 AU.addPreserved<MachineLoopInfo>();
83 MachineFunctionPass::getAnalysisUsage(AU);
86 const char *getPassName() const {
87 return "Hexagon Packetizer";
90 bool runOnMachineFunction(MachineFunction &Fn);
92 char HexagonPacketizer::ID = 0;
94 class HexagonPacketizerList : public VLIWPacketizerList {
98 // Has the instruction been promoted to a dot-new instruction.
99 bool PromotedToDotNew;
101 // Has the instruction been glued to allocframe.
102 bool GlueAllocframeStore;
104 // Has the feeder instruction been glued to new value jump.
105 bool GlueToNewValueJump;
107 // Check if there is a dependence between some instruction already in this
108 // packet and this instruction.
111 // Only check for dependence if there are resources available to
112 // schedule this instruction.
113 bool FoundSequentialDependence;
115 /// \brief A handle to the branch probability pass.
116 const MachineBranchProbabilityInfo *MBPI;
118 // Track MIs with ignored dependece.
119 std::vector<MachineInstr*> IgnoreDepMIs;
123 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
124 MachineDominatorTree &MDT,
125 const MachineBranchProbabilityInfo *MBPI);
127 // initPacketizerState - initialize some internal flags.
128 void initPacketizerState();
130 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
131 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
133 // isSoloInstruction - return true if instruction MI can not be packetized
134 // with any other instruction, which means that MI itself is a packet.
135 bool isSoloInstruction(MachineInstr *MI);
137 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
139 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
141 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
143 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
145 MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
147 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
148 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
149 MachineBasicBlock::iterator &MII,
150 const TargetRegisterClass* RC);
151 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
153 std::map <MachineInstr*, SUnit*> MIToSUnit,
154 MachineBasicBlock::iterator &MII,
155 const TargetRegisterClass* RC);
156 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
158 std::map <MachineInstr*, SUnit*> MIToSUnit,
159 MachineBasicBlock::iterator &MII);
160 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
162 std::map <MachineInstr*, SUnit*> MIToSUnit);
163 bool DemoteToDotOld(MachineInstr* MI);
164 bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
165 std::map <MachineInstr*, SUnit*> MIToSUnit);
166 bool RestrictingDepExistInPacket(MachineInstr*,
167 unsigned, std::map <MachineInstr*, SUnit*>);
168 bool isNewifiable(MachineInstr* MI);
169 bool isCondInst(MachineInstr* MI);
170 bool IsNewifyStore (MachineInstr* MI);
171 bool tryAllocateResourcesForConstExt(MachineInstr* MI);
172 bool canReserveResourcesForConstExt(MachineInstr *MI);
173 void reserveResourcesForConstExt(MachineInstr* MI);
174 bool isNewValueInst(MachineInstr* MI);
178 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
180 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
181 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
182 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
183 INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
187 // HexagonPacketizerList Ctor.
188 HexagonPacketizerList::HexagonPacketizerList(
189 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT,
190 const MachineBranchProbabilityInfo *MBPI)
191 : VLIWPacketizerList(MF, MLI, MDT, true){
195 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
196 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
197 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
198 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
199 const MachineBranchProbabilityInfo *MBPI =
200 &getAnalysis<MachineBranchProbabilityInfo>();
201 // Instantiate the packetizer.
202 HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI);
204 // DFA state table should not be empty.
205 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
208 // Loop over all basic blocks and remove KILL pseudo-instructions
209 // These instructions confuse the dependence analysis. Consider:
211 // R0 = KILL R0, D0 (Insn 1)
213 // Here, Insn 1 will result in the dependence graph not emitting an output
214 // dependence between Insn 0 and Insn 2. This can lead to incorrect
217 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
218 MBB != MBBe; ++MBB) {
219 MachineBasicBlock::iterator End = MBB->end();
220 MachineBasicBlock::iterator MI = MBB->begin();
223 MachineBasicBlock::iterator DeleteMI = MI;
225 MBB->erase(DeleteMI);
233 // Loop over all of the basic blocks.
234 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
235 MBB != MBBe; ++MBB) {
236 // Find scheduling regions and schedule / packetize each region.
237 unsigned RemainingCount = MBB->size();
238 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
239 RegionEnd != MBB->begin();) {
240 // The next region starts above the previous region. Look backward in the
241 // instruction stream until we find the nearest boundary.
242 MachineBasicBlock::iterator I = RegionEnd;
243 for(;I != MBB->begin(); --I, --RemainingCount) {
244 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
249 // Skip empty scheduling regions.
250 if (I == RegionEnd) {
251 RegionEnd = llvm::prior(RegionEnd);
255 // Skip regions with one instruction.
256 if (I == llvm::prior(RegionEnd)) {
257 RegionEnd = llvm::prior(RegionEnd);
261 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
270 static bool IsIndirectCall(MachineInstr* MI) {
271 return ((MI->getOpcode() == Hexagon::CALLR) ||
272 (MI->getOpcode() == Hexagon::CALLRv3));
275 // Reserve resources for constant extender. Trigure an assertion if
277 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
278 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
279 MachineFunction *MF = MI->getParent()->getParent();
280 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
283 if (ResourceTracker->canReserveResources(PseudoMI)) {
284 ResourceTracker->reserveResources(PseudoMI);
285 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
287 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
288 llvm_unreachable("can not reserve resources for constant extender.");
293 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
294 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
295 assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
296 "Should only be called for constant extended instructions");
297 MachineFunction *MF = MI->getParent()->getParent();
298 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
300 bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
301 MF->DeleteMachineInstr(PseudoMI);
305 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
306 // true, otherwise, return false.
307 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
308 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
309 MachineFunction *MF = MI->getParent()->getParent();
310 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
313 if (ResourceTracker->canReserveResources(PseudoMI)) {
314 ResourceTracker->reserveResources(PseudoMI);
315 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
318 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
324 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
328 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
329 const HexagonRegisterInfo* QRI =
330 (const HexagonRegisterInfo *) TM.getRegisterInfo();
332 // Check for lr dependence
333 if (DepReg == QRI->getRARegister()) {
337 if (QII->isDeallocRet(MI)) {
338 if (DepReg == QRI->getFrameRegister() ||
339 DepReg == QRI->getStackRegister())
343 // Check if this is a predicate dependence
344 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
345 if (RC == &Hexagon::PredRegsRegClass) {
350 // Lastly check for an operand used in an indirect call
351 // If we had an attribute for checking if an instruction is an indirect call,
352 // then we could have avoided this relatively brittle implementation of
355 // Assumes that the first operand of the CALLr is the function address
357 if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
358 MachineOperand MO = MI->getOperand(0);
359 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
367 static bool IsRegDependence(const SDep::Kind DepType) {
368 return (DepType == SDep::Data || DepType == SDep::Anti ||
369 DepType == SDep::Output);
372 static bool IsDirectJump(MachineInstr* MI) {
373 return (MI->getOpcode() == Hexagon::JMP);
376 static bool IsSchedBarrier(MachineInstr* MI) {
377 switch (MI->getOpcode()) {
378 case Hexagon::BARRIER:
384 static bool IsControlFlow(MachineInstr* MI) {
385 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
388 // Function returns true if an instruction can be promoted to the new-value
389 // store. It will always return false for v2 and v3.
390 // It lists all the conditional and unconditional stores that can be promoted
391 // to the new-value stores.
393 bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
394 const HexagonRegisterInfo* QRI =
395 (const HexagonRegisterInfo *) TM.getRegisterInfo();
396 switch (MI->getOpcode())
400 case Hexagon::STrib_indexed:
401 case Hexagon::STrib_indexed_shl_V4:
402 case Hexagon::STrib_shl_V4:
403 case Hexagon::STb_GP_V4:
404 case Hexagon::POST_STbri:
405 case Hexagon::STrib_cPt:
406 case Hexagon::STrib_cdnPt_V4:
407 case Hexagon::STrib_cNotPt:
408 case Hexagon::STrib_cdnNotPt_V4:
409 case Hexagon::STrib_indexed_cPt:
410 case Hexagon::STrib_indexed_cdnPt_V4:
411 case Hexagon::STrib_indexed_cNotPt:
412 case Hexagon::STrib_indexed_cdnNotPt_V4:
413 case Hexagon::STrib_indexed_shl_cPt_V4:
414 case Hexagon::STrib_indexed_shl_cdnPt_V4:
415 case Hexagon::STrib_indexed_shl_cNotPt_V4:
416 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
417 case Hexagon::POST_STbri_cPt:
418 case Hexagon::POST_STbri_cdnPt_V4:
419 case Hexagon::POST_STbri_cNotPt:
420 case Hexagon::POST_STbri_cdnNotPt_V4:
421 case Hexagon::STb_GP_cPt_V4:
422 case Hexagon::STb_GP_cNotPt_V4:
423 case Hexagon::STb_GP_cdnPt_V4:
424 case Hexagon::STb_GP_cdnNotPt_V4:
428 case Hexagon::STrih_indexed:
429 case Hexagon::STrih_indexed_shl_V4:
430 case Hexagon::STrih_shl_V4:
431 case Hexagon::STh_GP_V4:
432 case Hexagon::POST_SThri:
433 case Hexagon::STrih_cPt:
434 case Hexagon::STrih_cdnPt_V4:
435 case Hexagon::STrih_cNotPt:
436 case Hexagon::STrih_cdnNotPt_V4:
437 case Hexagon::STrih_indexed_cPt:
438 case Hexagon::STrih_indexed_cdnPt_V4:
439 case Hexagon::STrih_indexed_cNotPt:
440 case Hexagon::STrih_indexed_cdnNotPt_V4:
441 case Hexagon::STrih_indexed_shl_cPt_V4:
442 case Hexagon::STrih_indexed_shl_cdnPt_V4:
443 case Hexagon::STrih_indexed_shl_cNotPt_V4:
444 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
445 case Hexagon::POST_SThri_cPt:
446 case Hexagon::POST_SThri_cdnPt_V4:
447 case Hexagon::POST_SThri_cNotPt:
448 case Hexagon::POST_SThri_cdnNotPt_V4:
449 case Hexagon::STh_GP_cPt_V4:
450 case Hexagon::STh_GP_cNotPt_V4:
451 case Hexagon::STh_GP_cdnPt_V4:
452 case Hexagon::STh_GP_cdnNotPt_V4:
456 case Hexagon::STriw_indexed:
457 case Hexagon::STriw_indexed_shl_V4:
458 case Hexagon::STriw_shl_V4:
459 case Hexagon::STw_GP_V4:
460 case Hexagon::POST_STwri:
461 case Hexagon::STriw_cPt:
462 case Hexagon::STriw_cdnPt_V4:
463 case Hexagon::STriw_cNotPt:
464 case Hexagon::STriw_cdnNotPt_V4:
465 case Hexagon::STriw_indexed_cPt:
466 case Hexagon::STriw_indexed_cdnPt_V4:
467 case Hexagon::STriw_indexed_cNotPt:
468 case Hexagon::STriw_indexed_cdnNotPt_V4:
469 case Hexagon::STriw_indexed_shl_cPt_V4:
470 case Hexagon::STriw_indexed_shl_cdnPt_V4:
471 case Hexagon::STriw_indexed_shl_cNotPt_V4:
472 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
473 case Hexagon::POST_STwri_cPt:
474 case Hexagon::POST_STwri_cdnPt_V4:
475 case Hexagon::POST_STwri_cNotPt:
476 case Hexagon::POST_STwri_cdnNotPt_V4:
477 case Hexagon::STw_GP_cPt_V4:
478 case Hexagon::STw_GP_cNotPt_V4:
479 case Hexagon::STw_GP_cdnPt_V4:
480 case Hexagon::STw_GP_cdnNotPt_V4:
481 return QRI->Subtarget.hasV4TOps();
486 static bool IsLoopN(MachineInstr *MI) {
487 return (MI->getOpcode() == Hexagon::LOOP0_i ||
488 MI->getOpcode() == Hexagon::LOOP0_r);
491 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
492 /// callee-saved register.
493 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
494 const TargetRegisterInfo *TRI) {
495 for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
496 unsigned CalleeSavedReg = *CSR;
497 if (MI->modifiesRegister(CalleeSavedReg, TRI))
503 // Return the new value instruction for a given store.
504 static int GetDotNewOp(const int opc) {
506 default: llvm_unreachable("Unknown .new type");
507 // store new value byte
509 return Hexagon::STrib_nv_V4;
511 case Hexagon::STrib_indexed:
512 return Hexagon::STrib_indexed_nv_V4;
514 case Hexagon::STrib_indexed_shl_V4:
515 return Hexagon::STrib_indexed_shl_nv_V4;
517 case Hexagon::STrib_shl_V4:
518 return Hexagon::STrib_shl_nv_V4;
520 case Hexagon::STb_GP_V4:
521 return Hexagon::STb_GP_nv_V4;
523 case Hexagon::POST_STbri:
524 return Hexagon::POST_STbri_nv_V4;
526 case Hexagon::STrib_cPt:
527 return Hexagon::STrib_cPt_nv_V4;
529 case Hexagon::STrib_cdnPt_V4:
530 return Hexagon::STrib_cdnPt_nv_V4;
532 case Hexagon::STrib_cNotPt:
533 return Hexagon::STrib_cNotPt_nv_V4;
535 case Hexagon::STrib_cdnNotPt_V4:
536 return Hexagon::STrib_cdnNotPt_nv_V4;
538 case Hexagon::STrib_indexed_cPt:
539 return Hexagon::STrib_indexed_cPt_nv_V4;
541 case Hexagon::STrib_indexed_cdnPt_V4:
542 return Hexagon::STrib_indexed_cdnPt_nv_V4;
544 case Hexagon::STrib_indexed_cNotPt:
545 return Hexagon::STrib_indexed_cNotPt_nv_V4;
547 case Hexagon::STrib_indexed_cdnNotPt_V4:
548 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
550 case Hexagon::STrib_indexed_shl_cPt_V4:
551 return Hexagon::STrib_indexed_shl_cPt_nv_V4;
553 case Hexagon::STrib_indexed_shl_cdnPt_V4:
554 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
556 case Hexagon::STrib_indexed_shl_cNotPt_V4:
557 return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
559 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
560 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
562 case Hexagon::POST_STbri_cPt:
563 return Hexagon::POST_STbri_cPt_nv_V4;
565 case Hexagon::POST_STbri_cdnPt_V4:
566 return Hexagon::POST_STbri_cdnPt_nv_V4;
568 case Hexagon::POST_STbri_cNotPt:
569 return Hexagon::POST_STbri_cNotPt_nv_V4;
571 case Hexagon::POST_STbri_cdnNotPt_V4:
572 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
574 case Hexagon::STb_GP_cPt_V4:
575 return Hexagon::STb_GP_cPt_nv_V4;
577 case Hexagon::STb_GP_cNotPt_V4:
578 return Hexagon::STb_GP_cNotPt_nv_V4;
580 case Hexagon::STb_GP_cdnPt_V4:
581 return Hexagon::STb_GP_cdnPt_nv_V4;
583 case Hexagon::STb_GP_cdnNotPt_V4:
584 return Hexagon::STb_GP_cdnNotPt_nv_V4;
586 // store new value halfword
588 return Hexagon::STrih_nv_V4;
590 case Hexagon::STrih_indexed:
591 return Hexagon::STrih_indexed_nv_V4;
593 case Hexagon::STrih_indexed_shl_V4:
594 return Hexagon::STrih_indexed_shl_nv_V4;
596 case Hexagon::STrih_shl_V4:
597 return Hexagon::STrih_shl_nv_V4;
599 case Hexagon::STh_GP_V4:
600 return Hexagon::STh_GP_nv_V4;
602 case Hexagon::POST_SThri:
603 return Hexagon::POST_SThri_nv_V4;
605 case Hexagon::STrih_cPt:
606 return Hexagon::STrih_cPt_nv_V4;
608 case Hexagon::STrih_cdnPt_V4:
609 return Hexagon::STrih_cdnPt_nv_V4;
611 case Hexagon::STrih_cNotPt:
612 return Hexagon::STrih_cNotPt_nv_V4;
614 case Hexagon::STrih_cdnNotPt_V4:
615 return Hexagon::STrih_cdnNotPt_nv_V4;
617 case Hexagon::STrih_indexed_cPt:
618 return Hexagon::STrih_indexed_cPt_nv_V4;
620 case Hexagon::STrih_indexed_cdnPt_V4:
621 return Hexagon::STrih_indexed_cdnPt_nv_V4;
623 case Hexagon::STrih_indexed_cNotPt:
624 return Hexagon::STrih_indexed_cNotPt_nv_V4;
626 case Hexagon::STrih_indexed_cdnNotPt_V4:
627 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
629 case Hexagon::STrih_indexed_shl_cPt_V4:
630 return Hexagon::STrih_indexed_shl_cPt_nv_V4;
632 case Hexagon::STrih_indexed_shl_cdnPt_V4:
633 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
635 case Hexagon::STrih_indexed_shl_cNotPt_V4:
636 return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
638 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
639 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
641 case Hexagon::POST_SThri_cPt:
642 return Hexagon::POST_SThri_cPt_nv_V4;
644 case Hexagon::POST_SThri_cdnPt_V4:
645 return Hexagon::POST_SThri_cdnPt_nv_V4;
647 case Hexagon::POST_SThri_cNotPt:
648 return Hexagon::POST_SThri_cNotPt_nv_V4;
650 case Hexagon::POST_SThri_cdnNotPt_V4:
651 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
653 case Hexagon::STh_GP_cPt_V4:
654 return Hexagon::STh_GP_cPt_nv_V4;
656 case Hexagon::STh_GP_cNotPt_V4:
657 return Hexagon::STh_GP_cNotPt_nv_V4;
659 case Hexagon::STh_GP_cdnPt_V4:
660 return Hexagon::STh_GP_cdnPt_nv_V4;
662 case Hexagon::STh_GP_cdnNotPt_V4:
663 return Hexagon::STh_GP_cdnNotPt_nv_V4;
665 // store new value word
667 return Hexagon::STriw_nv_V4;
669 case Hexagon::STriw_indexed:
670 return Hexagon::STriw_indexed_nv_V4;
672 case Hexagon::STriw_indexed_shl_V4:
673 return Hexagon::STriw_indexed_shl_nv_V4;
675 case Hexagon::STriw_shl_V4:
676 return Hexagon::STriw_shl_nv_V4;
678 case Hexagon::STw_GP_V4:
679 return Hexagon::STw_GP_nv_V4;
681 case Hexagon::POST_STwri:
682 return Hexagon::POST_STwri_nv_V4;
684 case Hexagon::STriw_cPt:
685 return Hexagon::STriw_cPt_nv_V4;
687 case Hexagon::STriw_cdnPt_V4:
688 return Hexagon::STriw_cdnPt_nv_V4;
690 case Hexagon::STriw_cNotPt:
691 return Hexagon::STriw_cNotPt_nv_V4;
693 case Hexagon::STriw_cdnNotPt_V4:
694 return Hexagon::STriw_cdnNotPt_nv_V4;
696 case Hexagon::STriw_indexed_cPt:
697 return Hexagon::STriw_indexed_cPt_nv_V4;
699 case Hexagon::STriw_indexed_cdnPt_V4:
700 return Hexagon::STriw_indexed_cdnPt_nv_V4;
702 case Hexagon::STriw_indexed_cNotPt:
703 return Hexagon::STriw_indexed_cNotPt_nv_V4;
705 case Hexagon::STriw_indexed_cdnNotPt_V4:
706 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
708 case Hexagon::STriw_indexed_shl_cPt_V4:
709 return Hexagon::STriw_indexed_shl_cPt_nv_V4;
711 case Hexagon::STriw_indexed_shl_cdnPt_V4:
712 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
714 case Hexagon::STriw_indexed_shl_cNotPt_V4:
715 return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
717 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
718 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
720 case Hexagon::POST_STwri_cPt:
721 return Hexagon::POST_STwri_cPt_nv_V4;
723 case Hexagon::POST_STwri_cdnPt_V4:
724 return Hexagon::POST_STwri_cdnPt_nv_V4;
726 case Hexagon::POST_STwri_cNotPt:
727 return Hexagon::POST_STwri_cNotPt_nv_V4;
729 case Hexagon::POST_STwri_cdnNotPt_V4:
730 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
732 case Hexagon::STw_GP_cPt_V4:
733 return Hexagon::STw_GP_cPt_nv_V4;
735 case Hexagon::STw_GP_cNotPt_V4:
736 return Hexagon::STw_GP_cNotPt_nv_V4;
738 case Hexagon::STw_GP_cdnPt_V4:
739 return Hexagon::STw_GP_cdnPt_nv_V4;
741 case Hexagon::STw_GP_cdnNotPt_V4:
742 return Hexagon::STw_GP_cdnNotPt_nv_V4;
747 // Return .new predicate version for an instruction
748 static int GetDotNewPredOp(MachineInstr *MI,
749 const MachineBranchProbabilityInfo *MBPI,
750 const HexagonInstrInfo *QII) {
751 switch (MI->getOpcode()) {
752 default: llvm_unreachable("Unknown .new type");
753 // Conditional stores
754 // Store byte conditionally
755 case Hexagon::STrib_cPt :
756 return Hexagon::STrib_cdnPt_V4;
758 case Hexagon::STrib_cNotPt :
759 return Hexagon::STrib_cdnNotPt_V4;
761 case Hexagon::STrib_indexed_cPt :
762 return Hexagon::STrib_indexed_cdnPt_V4;
764 case Hexagon::STrib_indexed_cNotPt :
765 return Hexagon::STrib_indexed_cdnNotPt_V4;
767 case Hexagon::STrib_imm_cPt_V4 :
768 return Hexagon::STrib_imm_cdnPt_V4;
770 case Hexagon::STrib_imm_cNotPt_V4 :
771 return Hexagon::STrib_imm_cdnNotPt_V4;
773 case Hexagon::POST_STbri_cPt :
774 return Hexagon::POST_STbri_cdnPt_V4;
776 case Hexagon::POST_STbri_cNotPt :
777 return Hexagon::POST_STbri_cdnNotPt_V4;
779 case Hexagon::STrib_indexed_shl_cPt_V4 :
780 return Hexagon::STrib_indexed_shl_cdnPt_V4;
782 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
783 return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
785 case Hexagon::STb_GP_cPt_V4 :
786 return Hexagon::STb_GP_cdnPt_V4;
788 case Hexagon::STb_GP_cNotPt_V4 :
789 return Hexagon::STb_GP_cdnNotPt_V4;
791 // Store doubleword conditionally
792 case Hexagon::STrid_cPt :
793 return Hexagon::STrid_cdnPt_V4;
795 case Hexagon::STrid_cNotPt :
796 return Hexagon::STrid_cdnNotPt_V4;
798 case Hexagon::STrid_indexed_cPt :
799 return Hexagon::STrid_indexed_cdnPt_V4;
801 case Hexagon::STrid_indexed_cNotPt :
802 return Hexagon::STrid_indexed_cdnNotPt_V4;
804 case Hexagon::STrid_indexed_shl_cPt_V4 :
805 return Hexagon::STrid_indexed_shl_cdnPt_V4;
807 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
808 return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
810 case Hexagon::POST_STdri_cPt :
811 return Hexagon::POST_STdri_cdnPt_V4;
813 case Hexagon::POST_STdri_cNotPt :
814 return Hexagon::POST_STdri_cdnNotPt_V4;
816 case Hexagon::STd_GP_cPt_V4 :
817 return Hexagon::STd_GP_cdnPt_V4;
819 case Hexagon::STd_GP_cNotPt_V4 :
820 return Hexagon::STd_GP_cdnNotPt_V4;
822 // Store halfword conditionally
823 case Hexagon::STrih_cPt :
824 return Hexagon::STrih_cdnPt_V4;
826 case Hexagon::STrih_cNotPt :
827 return Hexagon::STrih_cdnNotPt_V4;
829 case Hexagon::STrih_indexed_cPt :
830 return Hexagon::STrih_indexed_cdnPt_V4;
832 case Hexagon::STrih_indexed_cNotPt :
833 return Hexagon::STrih_indexed_cdnNotPt_V4;
835 case Hexagon::STrih_imm_cPt_V4 :
836 return Hexagon::STrih_imm_cdnPt_V4;
838 case Hexagon::STrih_imm_cNotPt_V4 :
839 return Hexagon::STrih_imm_cdnNotPt_V4;
841 case Hexagon::STrih_indexed_shl_cPt_V4 :
842 return Hexagon::STrih_indexed_shl_cdnPt_V4;
844 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
845 return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
847 case Hexagon::POST_SThri_cPt :
848 return Hexagon::POST_SThri_cdnPt_V4;
850 case Hexagon::POST_SThri_cNotPt :
851 return Hexagon::POST_SThri_cdnNotPt_V4;
853 case Hexagon::STh_GP_cPt_V4 :
854 return Hexagon::STh_GP_cdnPt_V4;
856 case Hexagon::STh_GP_cNotPt_V4 :
857 return Hexagon::STh_GP_cdnNotPt_V4;
859 // Store word conditionally
860 case Hexagon::STriw_cPt :
861 return Hexagon::STriw_cdnPt_V4;
863 case Hexagon::STriw_cNotPt :
864 return Hexagon::STriw_cdnNotPt_V4;
866 case Hexagon::STriw_indexed_cPt :
867 return Hexagon::STriw_indexed_cdnPt_V4;
869 case Hexagon::STriw_indexed_cNotPt :
870 return Hexagon::STriw_indexed_cdnNotPt_V4;
872 case Hexagon::STriw_imm_cPt_V4 :
873 return Hexagon::STriw_imm_cdnPt_V4;
875 case Hexagon::STriw_imm_cNotPt_V4 :
876 return Hexagon::STriw_imm_cdnNotPt_V4;
878 case Hexagon::STriw_indexed_shl_cPt_V4 :
879 return Hexagon::STriw_indexed_shl_cdnPt_V4;
881 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
882 return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
884 case Hexagon::POST_STwri_cPt :
885 return Hexagon::POST_STwri_cdnPt_V4;
887 case Hexagon::POST_STwri_cNotPt :
888 return Hexagon::POST_STwri_cdnNotPt_V4;
890 case Hexagon::STw_GP_cPt_V4 :
891 return Hexagon::STw_GP_cdnPt_V4;
893 case Hexagon::STw_GP_cNotPt_V4 :
894 return Hexagon::STw_GP_cdnNotPt_V4;
899 return QII->getDotNewPredJumpOp(MI, MBPI);
901 case Hexagon::JMPR_t:
902 return Hexagon::JMPR_tnew_tV3;
904 case Hexagon::JMPR_f:
905 return Hexagon::JMPR_fnew_tV3;
907 // Conditional Transfers
908 case Hexagon::TFR_cPt:
909 return Hexagon::TFR_cdnPt;
911 case Hexagon::TFR_cNotPt:
912 return Hexagon::TFR_cdnNotPt;
914 case Hexagon::TFRI_cPt:
915 return Hexagon::TFRI_cdnPt;
917 case Hexagon::TFRI_cNotPt:
918 return Hexagon::TFRI_cdnNotPt;
921 case Hexagon::LDrid_cPt :
922 return Hexagon::LDrid_cdnPt;
924 case Hexagon::LDrid_cNotPt :
925 return Hexagon::LDrid_cdnNotPt;
927 case Hexagon::LDrid_indexed_cPt :
928 return Hexagon::LDrid_indexed_cdnPt;
930 case Hexagon::LDrid_indexed_cNotPt :
931 return Hexagon::LDrid_indexed_cdnNotPt;
933 case Hexagon::POST_LDrid_cPt :
934 return Hexagon::POST_LDrid_cdnPt_V4;
936 case Hexagon::POST_LDrid_cNotPt :
937 return Hexagon::POST_LDrid_cdnNotPt_V4;
940 case Hexagon::LDriw_cPt :
941 return Hexagon::LDriw_cdnPt;
943 case Hexagon::LDriw_cNotPt :
944 return Hexagon::LDriw_cdnNotPt;
946 case Hexagon::LDriw_indexed_cPt :
947 return Hexagon::LDriw_indexed_cdnPt;
949 case Hexagon::LDriw_indexed_cNotPt :
950 return Hexagon::LDriw_indexed_cdnNotPt;
952 case Hexagon::POST_LDriw_cPt :
953 return Hexagon::POST_LDriw_cdnPt_V4;
955 case Hexagon::POST_LDriw_cNotPt :
956 return Hexagon::POST_LDriw_cdnNotPt_V4;
959 case Hexagon::LDrih_cPt :
960 return Hexagon::LDrih_cdnPt;
962 case Hexagon::LDrih_cNotPt :
963 return Hexagon::LDrih_cdnNotPt;
965 case Hexagon::LDrih_indexed_cPt :
966 return Hexagon::LDrih_indexed_cdnPt;
968 case Hexagon::LDrih_indexed_cNotPt :
969 return Hexagon::LDrih_indexed_cdnNotPt;
971 case Hexagon::POST_LDrih_cPt :
972 return Hexagon::POST_LDrih_cdnPt_V4;
974 case Hexagon::POST_LDrih_cNotPt :
975 return Hexagon::POST_LDrih_cdnNotPt_V4;
978 case Hexagon::LDrib_cPt :
979 return Hexagon::LDrib_cdnPt;
981 case Hexagon::LDrib_cNotPt :
982 return Hexagon::LDrib_cdnNotPt;
984 case Hexagon::LDrib_indexed_cPt :
985 return Hexagon::LDrib_indexed_cdnPt;
987 case Hexagon::LDrib_indexed_cNotPt :
988 return Hexagon::LDrib_indexed_cdnNotPt;
990 case Hexagon::POST_LDrib_cPt :
991 return Hexagon::POST_LDrib_cdnPt_V4;
993 case Hexagon::POST_LDrib_cNotPt :
994 return Hexagon::POST_LDrib_cdnNotPt_V4;
996 // Load unsigned halfword
997 case Hexagon::LDriuh_cPt :
998 return Hexagon::LDriuh_cdnPt;
1000 case Hexagon::LDriuh_cNotPt :
1001 return Hexagon::LDriuh_cdnNotPt;
1003 case Hexagon::LDriuh_indexed_cPt :
1004 return Hexagon::LDriuh_indexed_cdnPt;
1006 case Hexagon::LDriuh_indexed_cNotPt :
1007 return Hexagon::LDriuh_indexed_cdnNotPt;
1009 case Hexagon::POST_LDriuh_cPt :
1010 return Hexagon::POST_LDriuh_cdnPt_V4;
1012 case Hexagon::POST_LDriuh_cNotPt :
1013 return Hexagon::POST_LDriuh_cdnNotPt_V4;
1015 // Load unsigned byte
1016 case Hexagon::LDriub_cPt :
1017 return Hexagon::LDriub_cdnPt;
1019 case Hexagon::LDriub_cNotPt :
1020 return Hexagon::LDriub_cdnNotPt;
1022 case Hexagon::LDriub_indexed_cPt :
1023 return Hexagon::LDriub_indexed_cdnPt;
1025 case Hexagon::LDriub_indexed_cNotPt :
1026 return Hexagon::LDriub_indexed_cdnNotPt;
1028 case Hexagon::POST_LDriub_cPt :
1029 return Hexagon::POST_LDriub_cdnPt_V4;
1031 case Hexagon::POST_LDriub_cNotPt :
1032 return Hexagon::POST_LDriub_cdnNotPt_V4;
1034 // V4 indexed+scaled load
1036 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1037 return Hexagon::LDrid_indexed_shl_cdnPt_V4;
1039 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1040 return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
1042 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1043 return Hexagon::LDrib_indexed_shl_cdnPt_V4;
1045 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1046 return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
1048 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1049 return Hexagon::LDriub_indexed_shl_cdnPt_V4;
1051 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1052 return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
1054 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1055 return Hexagon::LDrih_indexed_shl_cdnPt_V4;
1057 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1058 return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
1060 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1061 return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
1063 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1064 return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
1066 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1067 return Hexagon::LDriw_indexed_shl_cdnPt_V4;
1069 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1070 return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
1072 // V4 global address load
1074 case Hexagon::LDd_GP_cPt_V4:
1075 return Hexagon::LDd_GP_cdnPt_V4;
1077 case Hexagon::LDd_GP_cNotPt_V4:
1078 return Hexagon::LDd_GP_cdnNotPt_V4;
1080 case Hexagon::LDb_GP_cPt_V4:
1081 return Hexagon::LDb_GP_cdnPt_V4;
1083 case Hexagon::LDb_GP_cNotPt_V4:
1084 return Hexagon::LDb_GP_cdnNotPt_V4;
1086 case Hexagon::LDub_GP_cPt_V4:
1087 return Hexagon::LDub_GP_cdnPt_V4;
1089 case Hexagon::LDub_GP_cNotPt_V4:
1090 return Hexagon::LDub_GP_cdnNotPt_V4;
1092 case Hexagon::LDh_GP_cPt_V4:
1093 return Hexagon::LDh_GP_cdnPt_V4;
1095 case Hexagon::LDh_GP_cNotPt_V4:
1096 return Hexagon::LDh_GP_cdnNotPt_V4;
1098 case Hexagon::LDuh_GP_cPt_V4:
1099 return Hexagon::LDuh_GP_cdnPt_V4;
1101 case Hexagon::LDuh_GP_cNotPt_V4:
1102 return Hexagon::LDuh_GP_cdnNotPt_V4;
1104 case Hexagon::LDw_GP_cPt_V4:
1105 return Hexagon::LDw_GP_cdnPt_V4;
1107 case Hexagon::LDw_GP_cNotPt_V4:
1108 return Hexagon::LDw_GP_cdnNotPt_V4;
1110 // Conditional store new-value byte
1111 case Hexagon::STrib_cPt_nv_V4 :
1112 return Hexagon::STrib_cdnPt_nv_V4;
1113 case Hexagon::STrib_cNotPt_nv_V4 :
1114 return Hexagon::STrib_cdnNotPt_nv_V4;
1116 case Hexagon::STrib_indexed_cPt_nv_V4 :
1117 return Hexagon::STrib_indexed_cdnPt_nv_V4;
1118 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1119 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
1121 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1122 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
1123 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1124 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
1126 case Hexagon::POST_STbri_cPt_nv_V4 :
1127 return Hexagon::POST_STbri_cdnPt_nv_V4;
1128 case Hexagon::POST_STbri_cNotPt_nv_V4 :
1129 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
1131 case Hexagon::STb_GP_cPt_nv_V4 :
1132 return Hexagon::STb_GP_cdnPt_nv_V4;
1134 case Hexagon::STb_GP_cNotPt_nv_V4 :
1135 return Hexagon::STb_GP_cdnNotPt_nv_V4;
1137 // Conditional store new-value halfword
1138 case Hexagon::STrih_cPt_nv_V4 :
1139 return Hexagon::STrih_cdnPt_nv_V4;
1140 case Hexagon::STrih_cNotPt_nv_V4 :
1141 return Hexagon::STrih_cdnNotPt_nv_V4;
1143 case Hexagon::STrih_indexed_cPt_nv_V4 :
1144 return Hexagon::STrih_indexed_cdnPt_nv_V4;
1145 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1146 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
1148 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1149 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
1150 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1151 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
1153 case Hexagon::POST_SThri_cPt_nv_V4 :
1154 return Hexagon::POST_SThri_cdnPt_nv_V4;
1155 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1156 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
1158 case Hexagon::STh_GP_cPt_nv_V4 :
1159 return Hexagon::STh_GP_cdnPt_nv_V4;
1161 case Hexagon::STh_GP_cNotPt_nv_V4 :
1162 return Hexagon::STh_GP_cdnNotPt_nv_V4;
1164 // Conditional store new-value word
1165 case Hexagon::STriw_cPt_nv_V4 :
1166 return Hexagon::STriw_cdnPt_nv_V4;
1167 case Hexagon::STriw_cNotPt_nv_V4 :
1168 return Hexagon::STriw_cdnNotPt_nv_V4;
1170 case Hexagon::STriw_indexed_cPt_nv_V4 :
1171 return Hexagon::STriw_indexed_cdnPt_nv_V4;
1172 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1173 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
1175 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1176 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
1177 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1178 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
1180 case Hexagon::POST_STwri_cPt_nv_V4 :
1181 return Hexagon::POST_STwri_cdnPt_nv_V4;
1182 case Hexagon::POST_STwri_cNotPt_nv_V4:
1183 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
1185 case Hexagon::STw_GP_cPt_nv_V4 :
1186 return Hexagon::STw_GP_cdnPt_nv_V4;
1188 case Hexagon::STw_GP_cNotPt_nv_V4 :
1189 return Hexagon::STw_GP_cdnNotPt_nv_V4;
1192 case Hexagon::ADD_ri_cPt :
1193 return Hexagon::ADD_ri_cdnPt;
1194 case Hexagon::ADD_ri_cNotPt :
1195 return Hexagon::ADD_ri_cdnNotPt;
1197 case Hexagon::ADD_rr_cPt :
1198 return Hexagon::ADD_rr_cdnPt;
1199 case Hexagon::ADD_rr_cNotPt :
1200 return Hexagon::ADD_rr_cdnNotPt;
1202 // Conditional logical Operations
1203 case Hexagon::XOR_rr_cPt :
1204 return Hexagon::XOR_rr_cdnPt;
1205 case Hexagon::XOR_rr_cNotPt :
1206 return Hexagon::XOR_rr_cdnNotPt;
1208 case Hexagon::AND_rr_cPt :
1209 return Hexagon::AND_rr_cdnPt;
1210 case Hexagon::AND_rr_cNotPt :
1211 return Hexagon::AND_rr_cdnNotPt;
1213 case Hexagon::OR_rr_cPt :
1214 return Hexagon::OR_rr_cdnPt;
1215 case Hexagon::OR_rr_cNotPt :
1216 return Hexagon::OR_rr_cdnNotPt;
1218 // Conditional Subtract
1219 case Hexagon::SUB_rr_cPt :
1220 return Hexagon::SUB_rr_cdnPt;
1221 case Hexagon::SUB_rr_cNotPt :
1222 return Hexagon::SUB_rr_cdnNotPt;
1224 // Conditional combine
1225 case Hexagon::COMBINE_rr_cPt :
1226 return Hexagon::COMBINE_rr_cdnPt;
1227 case Hexagon::COMBINE_rr_cNotPt :
1228 return Hexagon::COMBINE_rr_cdnNotPt;
1230 case Hexagon::ASLH_cPt_V4 :
1231 return Hexagon::ASLH_cdnPt_V4;
1232 case Hexagon::ASLH_cNotPt_V4 :
1233 return Hexagon::ASLH_cdnNotPt_V4;
1235 case Hexagon::ASRH_cPt_V4 :
1236 return Hexagon::ASRH_cdnPt_V4;
1237 case Hexagon::ASRH_cNotPt_V4 :
1238 return Hexagon::ASRH_cdnNotPt_V4;
1240 case Hexagon::SXTB_cPt_V4 :
1241 return Hexagon::SXTB_cdnPt_V4;
1242 case Hexagon::SXTB_cNotPt_V4 :
1243 return Hexagon::SXTB_cdnNotPt_V4;
1245 case Hexagon::SXTH_cPt_V4 :
1246 return Hexagon::SXTH_cdnPt_V4;
1247 case Hexagon::SXTH_cNotPt_V4 :
1248 return Hexagon::SXTH_cdnNotPt_V4;
1250 case Hexagon::ZXTB_cPt_V4 :
1251 return Hexagon::ZXTB_cdnPt_V4;
1252 case Hexagon::ZXTB_cNotPt_V4 :
1253 return Hexagon::ZXTB_cdnNotPt_V4;
1255 case Hexagon::ZXTH_cPt_V4 :
1256 return Hexagon::ZXTH_cdnPt_V4;
1257 case Hexagon::ZXTH_cNotPt_V4 :
1258 return Hexagon::ZXTH_cdnNotPt_V4;
1262 // Returns true if an instruction can be promoted to .new predicate
1263 // or new-value store.
1264 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
1265 if ( isCondInst(MI) || IsNewifyStore(MI))
1271 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
1272 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1273 const MCInstrDesc& TID = MI->getDesc();
1274 // bug 5670: until that is fixed,
1275 // this portion is disabled.
1276 if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
1277 || QII->isConditionalTransfer(MI)
1278 || QII->isConditionalALU32(MI)
1279 || QII->isConditionalLoad(MI)
1280 || QII->isConditionalStore(MI)) {
1287 // Promote an instructiont to its .new form.
1288 // At this time, we have already made a call to CanPromoteToDotNew
1289 // and made sure that it can *indeed* be promoted.
1290 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
1291 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
1292 const TargetRegisterClass* RC) {
1294 assert (DepType == SDep::Data);
1295 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1298 if (RC == &Hexagon::PredRegsRegClass)
1299 NewOpcode = GetDotNewPredOp(MI, MBPI, QII);
1301 NewOpcode = GetDotNewOp(MI->getOpcode());
1302 MI->setDesc(QII->get(NewOpcode));
1307 // Returns the most basic instruction for the .new predicated instructions and
1308 // new-value stores.
1309 // For example, all of the following instructions will be converted back to the
1310 // same instruction:
1311 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1312 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1313 // 3) if (p0.new) memw(R0+#0) = R1 --->
1315 // To understand the translation of instruction 1 to its original form, consider
1316 // a packet with 3 instructions.
1317 // { p0 = cmp.eq(R0,R1)
1318 // if (p0.new) R2 = add(R3, R4)
1319 // R5 = add (R3, R1)
1321 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
1323 // This instruction can be part of the previous packet only if both p0 and R2
1324 // are promoted to .new values. This promotion happens in steps, first
1325 // predicate register is promoted to .new and in the next iteration R2 is
1326 // promoted. Therefore, in case of dependence check failure (due to R5) during
1327 // next iteration, it should be converted back to its most basic form.
1329 static int GetDotOldOp(const int opc) {
1331 default: llvm_unreachable("Unknown .old type");
1332 case Hexagon::TFR_cdnPt:
1333 return Hexagon::TFR_cPt;
1335 case Hexagon::TFR_cdnNotPt:
1336 return Hexagon::TFR_cNotPt;
1338 case Hexagon::TFRI_cdnPt:
1339 return Hexagon::TFRI_cPt;
1341 case Hexagon::TFRI_cdnNotPt:
1342 return Hexagon::TFRI_cNotPt;
1344 case Hexagon::JMP_tnew_t:
1345 return Hexagon::JMP_t;
1347 case Hexagon::JMP_fnew_t:
1348 return Hexagon::JMP_f;
1350 case Hexagon::JMPR_tnew_tV3:
1351 return Hexagon::JMPR_t;
1353 case Hexagon::JMPR_fnew_tV3:
1354 return Hexagon::JMPR_f;
1358 case Hexagon::LDrid_cdnPt :
1359 return Hexagon::LDrid_cPt;
1361 case Hexagon::LDrid_cdnNotPt :
1362 return Hexagon::LDrid_cNotPt;
1364 case Hexagon::LDrid_indexed_cdnPt :
1365 return Hexagon::LDrid_indexed_cPt;
1367 case Hexagon::LDrid_indexed_cdnNotPt :
1368 return Hexagon::LDrid_indexed_cNotPt;
1370 case Hexagon::POST_LDrid_cdnPt_V4 :
1371 return Hexagon::POST_LDrid_cPt;
1373 case Hexagon::POST_LDrid_cdnNotPt_V4 :
1374 return Hexagon::POST_LDrid_cNotPt;
1378 case Hexagon::LDriw_cdnPt :
1379 return Hexagon::LDriw_cPt;
1381 case Hexagon::LDriw_cdnNotPt :
1382 return Hexagon::LDriw_cNotPt;
1384 case Hexagon::LDriw_indexed_cdnPt :
1385 return Hexagon::LDriw_indexed_cPt;
1387 case Hexagon::LDriw_indexed_cdnNotPt :
1388 return Hexagon::LDriw_indexed_cNotPt;
1390 case Hexagon::POST_LDriw_cdnPt_V4 :
1391 return Hexagon::POST_LDriw_cPt;
1393 case Hexagon::POST_LDriw_cdnNotPt_V4 :
1394 return Hexagon::POST_LDriw_cNotPt;
1398 case Hexagon::LDrih_cdnPt :
1399 return Hexagon::LDrih_cPt;
1401 case Hexagon::LDrih_cdnNotPt :
1402 return Hexagon::LDrih_cNotPt;
1404 case Hexagon::LDrih_indexed_cdnPt :
1405 return Hexagon::LDrih_indexed_cPt;
1407 case Hexagon::LDrih_indexed_cdnNotPt :
1408 return Hexagon::LDrih_indexed_cNotPt;
1410 case Hexagon::POST_LDrih_cdnPt_V4 :
1411 return Hexagon::POST_LDrih_cPt;
1413 case Hexagon::POST_LDrih_cdnNotPt_V4 :
1414 return Hexagon::POST_LDrih_cNotPt;
1418 case Hexagon::LDrib_cdnPt :
1419 return Hexagon::LDrib_cPt;
1421 case Hexagon::LDrib_cdnNotPt :
1422 return Hexagon::LDrib_cNotPt;
1424 case Hexagon::LDrib_indexed_cdnPt :
1425 return Hexagon::LDrib_indexed_cPt;
1427 case Hexagon::LDrib_indexed_cdnNotPt :
1428 return Hexagon::LDrib_indexed_cNotPt;
1430 case Hexagon::POST_LDrib_cdnPt_V4 :
1431 return Hexagon::POST_LDrib_cPt;
1433 case Hexagon::POST_LDrib_cdnNotPt_V4 :
1434 return Hexagon::POST_LDrib_cNotPt;
1436 // Load unsigned half
1438 case Hexagon::LDriuh_cdnPt :
1439 return Hexagon::LDriuh_cPt;
1441 case Hexagon::LDriuh_cdnNotPt :
1442 return Hexagon::LDriuh_cNotPt;
1444 case Hexagon::LDriuh_indexed_cdnPt :
1445 return Hexagon::LDriuh_indexed_cPt;
1447 case Hexagon::LDriuh_indexed_cdnNotPt :
1448 return Hexagon::LDriuh_indexed_cNotPt;
1450 case Hexagon::POST_LDriuh_cdnPt_V4 :
1451 return Hexagon::POST_LDriuh_cPt;
1453 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
1454 return Hexagon::POST_LDriuh_cNotPt;
1456 // Load unsigned byte
1457 case Hexagon::LDriub_cdnPt :
1458 return Hexagon::LDriub_cPt;
1460 case Hexagon::LDriub_cdnNotPt :
1461 return Hexagon::LDriub_cNotPt;
1463 case Hexagon::LDriub_indexed_cdnPt :
1464 return Hexagon::LDriub_indexed_cPt;
1466 case Hexagon::LDriub_indexed_cdnNotPt :
1467 return Hexagon::LDriub_indexed_cNotPt;
1469 case Hexagon::POST_LDriub_cdnPt_V4 :
1470 return Hexagon::POST_LDriub_cPt;
1472 case Hexagon::POST_LDriub_cdnNotPt_V4 :
1473 return Hexagon::POST_LDriub_cNotPt;
1475 // V4 indexed+scaled Load
1477 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1478 return Hexagon::LDrid_indexed_shl_cPt_V4;
1480 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
1481 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1483 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1484 return Hexagon::LDrib_indexed_shl_cPt_V4;
1486 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
1487 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1489 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1490 return Hexagon::LDriub_indexed_shl_cPt_V4;
1492 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
1493 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1495 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1496 return Hexagon::LDrih_indexed_shl_cPt_V4;
1498 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
1499 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1501 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1502 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1504 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
1505 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1507 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1508 return Hexagon::LDriw_indexed_shl_cPt_V4;
1510 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
1511 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1513 // V4 global address load
1515 case Hexagon::LDd_GP_cdnPt_V4:
1516 return Hexagon::LDd_GP_cPt_V4;
1518 case Hexagon::LDd_GP_cdnNotPt_V4:
1519 return Hexagon::LDd_GP_cNotPt_V4;
1521 case Hexagon::LDb_GP_cdnPt_V4:
1522 return Hexagon::LDb_GP_cPt_V4;
1524 case Hexagon::LDb_GP_cdnNotPt_V4:
1525 return Hexagon::LDb_GP_cNotPt_V4;
1527 case Hexagon::LDub_GP_cdnPt_V4:
1528 return Hexagon::LDub_GP_cPt_V4;
1530 case Hexagon::LDub_GP_cdnNotPt_V4:
1531 return Hexagon::LDub_GP_cNotPt_V4;
1533 case Hexagon::LDh_GP_cdnPt_V4:
1534 return Hexagon::LDh_GP_cPt_V4;
1536 case Hexagon::LDh_GP_cdnNotPt_V4:
1537 return Hexagon::LDh_GP_cNotPt_V4;
1539 case Hexagon::LDuh_GP_cdnPt_V4:
1540 return Hexagon::LDuh_GP_cPt_V4;
1542 case Hexagon::LDuh_GP_cdnNotPt_V4:
1543 return Hexagon::LDuh_GP_cNotPt_V4;
1545 case Hexagon::LDw_GP_cdnPt_V4:
1546 return Hexagon::LDw_GP_cPt_V4;
1548 case Hexagon::LDw_GP_cdnNotPt_V4:
1549 return Hexagon::LDw_GP_cNotPt_V4;
1553 case Hexagon::ADD_ri_cdnPt :
1554 return Hexagon::ADD_ri_cPt;
1555 case Hexagon::ADD_ri_cdnNotPt :
1556 return Hexagon::ADD_ri_cNotPt;
1558 case Hexagon::ADD_rr_cdnPt :
1559 return Hexagon::ADD_rr_cPt;
1560 case Hexagon::ADD_rr_cdnNotPt:
1561 return Hexagon::ADD_rr_cNotPt;
1563 // Conditional logical Operations
1565 case Hexagon::XOR_rr_cdnPt :
1566 return Hexagon::XOR_rr_cPt;
1567 case Hexagon::XOR_rr_cdnNotPt :
1568 return Hexagon::XOR_rr_cNotPt;
1570 case Hexagon::AND_rr_cdnPt :
1571 return Hexagon::AND_rr_cPt;
1572 case Hexagon::AND_rr_cdnNotPt :
1573 return Hexagon::AND_rr_cNotPt;
1575 case Hexagon::OR_rr_cdnPt :
1576 return Hexagon::OR_rr_cPt;
1577 case Hexagon::OR_rr_cdnNotPt :
1578 return Hexagon::OR_rr_cNotPt;
1580 // Conditional Subtract
1582 case Hexagon::SUB_rr_cdnPt :
1583 return Hexagon::SUB_rr_cPt;
1584 case Hexagon::SUB_rr_cdnNotPt :
1585 return Hexagon::SUB_rr_cNotPt;
1587 // Conditional combine
1589 case Hexagon::COMBINE_rr_cdnPt :
1590 return Hexagon::COMBINE_rr_cPt;
1591 case Hexagon::COMBINE_rr_cdnNotPt :
1592 return Hexagon::COMBINE_rr_cNotPt;
1594 // Conditional shift operations
1596 case Hexagon::ASLH_cdnPt_V4 :
1597 return Hexagon::ASLH_cPt_V4;
1598 case Hexagon::ASLH_cdnNotPt_V4 :
1599 return Hexagon::ASLH_cNotPt_V4;
1601 case Hexagon::ASRH_cdnPt_V4 :
1602 return Hexagon::ASRH_cPt_V4;
1603 case Hexagon::ASRH_cdnNotPt_V4 :
1604 return Hexagon::ASRH_cNotPt_V4;
1606 case Hexagon::SXTB_cdnPt_V4 :
1607 return Hexagon::SXTB_cPt_V4;
1608 case Hexagon::SXTB_cdnNotPt_V4 :
1609 return Hexagon::SXTB_cNotPt_V4;
1611 case Hexagon::SXTH_cdnPt_V4 :
1612 return Hexagon::SXTH_cPt_V4;
1613 case Hexagon::SXTH_cdnNotPt_V4 :
1614 return Hexagon::SXTH_cNotPt_V4;
1616 case Hexagon::ZXTB_cdnPt_V4 :
1617 return Hexagon::ZXTB_cPt_V4;
1618 case Hexagon::ZXTB_cdnNotPt_V4 :
1619 return Hexagon::ZXTB_cNotPt_V4;
1621 case Hexagon::ZXTH_cdnPt_V4 :
1622 return Hexagon::ZXTH_cPt_V4;
1623 case Hexagon::ZXTH_cdnNotPt_V4 :
1624 return Hexagon::ZXTH_cNotPt_V4;
1628 case Hexagon::STrib_imm_cdnPt_V4 :
1629 return Hexagon::STrib_imm_cPt_V4;
1631 case Hexagon::STrib_imm_cdnNotPt_V4 :
1632 return Hexagon::STrib_imm_cNotPt_V4;
1634 case Hexagon::STrib_cdnPt_nv_V4 :
1635 case Hexagon::STrib_cPt_nv_V4 :
1636 case Hexagon::STrib_cdnPt_V4 :
1637 return Hexagon::STrib_cPt;
1639 case Hexagon::STrib_cdnNotPt_nv_V4 :
1640 case Hexagon::STrib_cNotPt_nv_V4 :
1641 case Hexagon::STrib_cdnNotPt_V4 :
1642 return Hexagon::STrib_cNotPt;
1644 case Hexagon::STrib_indexed_cdnPt_V4 :
1645 case Hexagon::STrib_indexed_cPt_nv_V4 :
1646 case Hexagon::STrib_indexed_cdnPt_nv_V4 :
1647 return Hexagon::STrib_indexed_cPt;
1649 case Hexagon::STrib_indexed_cdnNotPt_V4 :
1650 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1651 case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
1652 return Hexagon::STrib_indexed_cNotPt;
1654 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1655 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1656 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1657 return Hexagon::STrib_indexed_shl_cPt_V4;
1659 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1660 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1661 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
1662 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1664 case Hexagon::POST_STbri_cdnPt_nv_V4 :
1665 case Hexagon::POST_STbri_cPt_nv_V4 :
1666 case Hexagon::POST_STbri_cdnPt_V4 :
1667 return Hexagon::POST_STbri_cPt;
1669 case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
1670 case Hexagon::POST_STbri_cNotPt_nv_V4:
1671 case Hexagon::POST_STbri_cdnNotPt_V4 :
1672 return Hexagon::POST_STbri_cNotPt;
1674 case Hexagon::STb_GP_cdnPt_nv_V4:
1675 case Hexagon::STb_GP_cdnPt_V4:
1676 case Hexagon::STb_GP_cPt_nv_V4:
1677 return Hexagon::STb_GP_cPt_V4;
1679 case Hexagon::STb_GP_cdnNotPt_nv_V4:
1680 case Hexagon::STb_GP_cdnNotPt_V4:
1681 case Hexagon::STb_GP_cNotPt_nv_V4:
1682 return Hexagon::STb_GP_cNotPt_V4;
1684 // Store new-value byte - unconditional
1685 case Hexagon::STrib_nv_V4:
1686 return Hexagon::STrib;
1688 case Hexagon::STrib_indexed_nv_V4:
1689 return Hexagon::STrib_indexed;
1691 case Hexagon::STrib_indexed_shl_nv_V4:
1692 return Hexagon::STrib_indexed_shl_V4;
1694 case Hexagon::STrib_shl_nv_V4:
1695 return Hexagon::STrib_shl_V4;
1697 case Hexagon::STb_GP_nv_V4:
1698 return Hexagon::STb_GP_V4;
1700 case Hexagon::POST_STbri_nv_V4:
1701 return Hexagon::POST_STbri;
1704 case Hexagon::STrih_imm_cdnPt_V4 :
1705 return Hexagon::STrih_imm_cPt_V4;
1707 case Hexagon::STrih_imm_cdnNotPt_V4 :
1708 return Hexagon::STrih_imm_cNotPt_V4;
1710 case Hexagon::STrih_cdnPt_nv_V4 :
1711 case Hexagon::STrih_cPt_nv_V4 :
1712 case Hexagon::STrih_cdnPt_V4 :
1713 return Hexagon::STrih_cPt;
1715 case Hexagon::STrih_cdnNotPt_nv_V4 :
1716 case Hexagon::STrih_cNotPt_nv_V4 :
1717 case Hexagon::STrih_cdnNotPt_V4 :
1718 return Hexagon::STrih_cNotPt;
1720 case Hexagon::STrih_indexed_cdnPt_nv_V4:
1721 case Hexagon::STrih_indexed_cPt_nv_V4 :
1722 case Hexagon::STrih_indexed_cdnPt_V4 :
1723 return Hexagon::STrih_indexed_cPt;
1725 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1726 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1727 case Hexagon::STrih_indexed_cdnNotPt_V4 :
1728 return Hexagon::STrih_indexed_cNotPt;
1730 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
1731 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1732 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1733 return Hexagon::STrih_indexed_shl_cPt_V4;
1735 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
1736 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1737 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
1738 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1740 case Hexagon::POST_SThri_cdnPt_nv_V4 :
1741 case Hexagon::POST_SThri_cPt_nv_V4 :
1742 case Hexagon::POST_SThri_cdnPt_V4 :
1743 return Hexagon::POST_SThri_cPt;
1745 case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
1746 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1747 case Hexagon::POST_SThri_cdnNotPt_V4 :
1748 return Hexagon::POST_SThri_cNotPt;
1750 case Hexagon::STh_GP_cdnPt_nv_V4:
1751 case Hexagon::STh_GP_cdnPt_V4:
1752 case Hexagon::STh_GP_cPt_nv_V4:
1753 return Hexagon::STh_GP_cPt_V4;
1755 case Hexagon::STh_GP_cdnNotPt_nv_V4:
1756 case Hexagon::STh_GP_cdnNotPt_V4:
1757 case Hexagon::STh_GP_cNotPt_nv_V4:
1758 return Hexagon::STh_GP_cNotPt_V4;
1760 // Store new-value halfword - unconditional
1762 case Hexagon::STrih_nv_V4:
1763 return Hexagon::STrih;
1765 case Hexagon::STrih_indexed_nv_V4:
1766 return Hexagon::STrih_indexed;
1768 case Hexagon::STrih_indexed_shl_nv_V4:
1769 return Hexagon::STrih_indexed_shl_V4;
1771 case Hexagon::STrih_shl_nv_V4:
1772 return Hexagon::STrih_shl_V4;
1774 case Hexagon::STh_GP_nv_V4:
1775 return Hexagon::STh_GP_V4;
1777 case Hexagon::POST_SThri_nv_V4:
1778 return Hexagon::POST_SThri;
1782 case Hexagon::STriw_imm_cdnPt_V4 :
1783 return Hexagon::STriw_imm_cPt_V4;
1785 case Hexagon::STriw_imm_cdnNotPt_V4 :
1786 return Hexagon::STriw_imm_cNotPt_V4;
1788 case Hexagon::STriw_cdnPt_nv_V4 :
1789 case Hexagon::STriw_cPt_nv_V4 :
1790 case Hexagon::STriw_cdnPt_V4 :
1791 return Hexagon::STriw_cPt;
1793 case Hexagon::STriw_cdnNotPt_nv_V4 :
1794 case Hexagon::STriw_cNotPt_nv_V4 :
1795 case Hexagon::STriw_cdnNotPt_V4 :
1796 return Hexagon::STriw_cNotPt;
1798 case Hexagon::STriw_indexed_cdnPt_nv_V4 :
1799 case Hexagon::STriw_indexed_cPt_nv_V4 :
1800 case Hexagon::STriw_indexed_cdnPt_V4 :
1801 return Hexagon::STriw_indexed_cPt;
1803 case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
1804 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1805 case Hexagon::STriw_indexed_cdnNotPt_V4 :
1806 return Hexagon::STriw_indexed_cNotPt;
1808 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
1809 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1810 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1811 return Hexagon::STriw_indexed_shl_cPt_V4;
1813 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
1814 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1815 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
1816 return Hexagon::STriw_indexed_shl_cNotPt_V4;
1818 case Hexagon::POST_STwri_cdnPt_nv_V4 :
1819 case Hexagon::POST_STwri_cPt_nv_V4 :
1820 case Hexagon::POST_STwri_cdnPt_V4 :
1821 return Hexagon::POST_STwri_cPt;
1823 case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
1824 case Hexagon::POST_STwri_cNotPt_nv_V4 :
1825 case Hexagon::POST_STwri_cdnNotPt_V4 :
1826 return Hexagon::POST_STwri_cNotPt;
1828 case Hexagon::STw_GP_cdnPt_nv_V4:
1829 case Hexagon::STw_GP_cdnPt_V4:
1830 case Hexagon::STw_GP_cPt_nv_V4:
1831 return Hexagon::STw_GP_cPt_V4;
1833 case Hexagon::STw_GP_cdnNotPt_nv_V4:
1834 case Hexagon::STw_GP_cdnNotPt_V4:
1835 case Hexagon::STw_GP_cNotPt_nv_V4:
1836 return Hexagon::STw_GP_cNotPt_V4;
1838 // Store new-value word - unconditional
1840 case Hexagon::STriw_nv_V4:
1841 return Hexagon::STriw;
1843 case Hexagon::STriw_indexed_nv_V4:
1844 return Hexagon::STriw_indexed;
1846 case Hexagon::STriw_indexed_shl_nv_V4:
1847 return Hexagon::STriw_indexed_shl_V4;
1849 case Hexagon::STriw_shl_nv_V4:
1850 return Hexagon::STriw_shl_V4;
1852 case Hexagon::STw_GP_nv_V4:
1853 return Hexagon::STw_GP_V4;
1855 case Hexagon::POST_STwri_nv_V4:
1856 return Hexagon::POST_STwri;
1860 case Hexagon::STrid_cdnPt_V4 :
1861 return Hexagon::STrid_cPt;
1863 case Hexagon::STrid_cdnNotPt_V4 :
1864 return Hexagon::STrid_cNotPt;
1866 case Hexagon::STrid_indexed_cdnPt_V4 :
1867 return Hexagon::STrid_indexed_cPt;
1869 case Hexagon::STrid_indexed_cdnNotPt_V4 :
1870 return Hexagon::STrid_indexed_cNotPt;
1872 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1873 return Hexagon::STrid_indexed_shl_cPt_V4;
1875 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
1876 return Hexagon::STrid_indexed_shl_cNotPt_V4;
1878 case Hexagon::POST_STdri_cdnPt_V4 :
1879 return Hexagon::POST_STdri_cPt;
1881 case Hexagon::POST_STdri_cdnNotPt_V4 :
1882 return Hexagon::POST_STdri_cNotPt;
1884 case Hexagon::STd_GP_cdnPt_V4 :
1885 return Hexagon::STd_GP_cPt_V4;
1887 case Hexagon::STd_GP_cdnNotPt_V4 :
1888 return Hexagon::STd_GP_cNotPt_V4;
1893 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
1894 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1895 int NewOpcode = GetDotOldOp(MI->getOpcode());
1896 MI->setDesc(QII->get(NewOpcode));
1900 // Returns true if an instruction is predicated on p0 and false if it's
1901 // predicated on !p0.
1903 static bool GetPredicateSense(MachineInstr* MI,
1904 const HexagonInstrInfo *QII) {
1906 switch (MI->getOpcode()) {
1907 default: llvm_unreachable("Unknown predicate sense of the instruction");
1908 case Hexagon::TFR_cPt:
1909 case Hexagon::TFR_cdnPt:
1910 case Hexagon::TFRI_cPt:
1911 case Hexagon::TFRI_cdnPt:
1912 case Hexagon::STrib_cPt :
1913 case Hexagon::STrib_cdnPt_V4 :
1914 case Hexagon::STrib_indexed_cPt :
1915 case Hexagon::STrib_indexed_cdnPt_V4 :
1916 case Hexagon::STrib_indexed_shl_cPt_V4 :
1917 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1918 case Hexagon::POST_STbri_cPt :
1919 case Hexagon::POST_STbri_cdnPt_V4 :
1920 case Hexagon::STrih_cPt :
1921 case Hexagon::STrih_cdnPt_V4 :
1922 case Hexagon::STrih_indexed_cPt :
1923 case Hexagon::STrih_indexed_cdnPt_V4 :
1924 case Hexagon::STrih_indexed_shl_cPt_V4 :
1925 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1926 case Hexagon::POST_SThri_cPt :
1927 case Hexagon::POST_SThri_cdnPt_V4 :
1928 case Hexagon::STriw_cPt :
1929 case Hexagon::STriw_cdnPt_V4 :
1930 case Hexagon::STriw_indexed_cPt :
1931 case Hexagon::STriw_indexed_cdnPt_V4 :
1932 case Hexagon::STriw_indexed_shl_cPt_V4 :
1933 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1934 case Hexagon::POST_STwri_cPt :
1935 case Hexagon::POST_STwri_cdnPt_V4 :
1936 case Hexagon::STrib_imm_cPt_V4 :
1937 case Hexagon::STrib_imm_cdnPt_V4 :
1938 case Hexagon::STrid_cPt :
1939 case Hexagon::STrid_cdnPt_V4 :
1940 case Hexagon::STrid_indexed_cPt :
1941 case Hexagon::STrid_indexed_cdnPt_V4 :
1942 case Hexagon::STrid_indexed_shl_cPt_V4 :
1943 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1944 case Hexagon::POST_STdri_cPt :
1945 case Hexagon::POST_STdri_cdnPt_V4 :
1946 case Hexagon::STrih_imm_cPt_V4 :
1947 case Hexagon::STrih_imm_cdnPt_V4 :
1948 case Hexagon::STriw_imm_cPt_V4 :
1949 case Hexagon::STriw_imm_cdnPt_V4 :
1950 case Hexagon::JMP_tnew_t :
1951 case Hexagon::LDrid_cPt :
1952 case Hexagon::LDrid_cdnPt :
1953 case Hexagon::LDrid_indexed_cPt :
1954 case Hexagon::LDrid_indexed_cdnPt :
1955 case Hexagon::POST_LDrid_cPt :
1956 case Hexagon::POST_LDrid_cdnPt_V4 :
1957 case Hexagon::LDriw_cPt :
1958 case Hexagon::LDriw_cdnPt :
1959 case Hexagon::LDriw_indexed_cPt :
1960 case Hexagon::LDriw_indexed_cdnPt :
1961 case Hexagon::POST_LDriw_cPt :
1962 case Hexagon::POST_LDriw_cdnPt_V4 :
1963 case Hexagon::LDrih_cPt :
1964 case Hexagon::LDrih_cdnPt :
1965 case Hexagon::LDrih_indexed_cPt :
1966 case Hexagon::LDrih_indexed_cdnPt :
1967 case Hexagon::POST_LDrih_cPt :
1968 case Hexagon::POST_LDrih_cdnPt_V4 :
1969 case Hexagon::LDrib_cPt :
1970 case Hexagon::LDrib_cdnPt :
1971 case Hexagon::LDrib_indexed_cPt :
1972 case Hexagon::LDrib_indexed_cdnPt :
1973 case Hexagon::POST_LDrib_cPt :
1974 case Hexagon::POST_LDrib_cdnPt_V4 :
1975 case Hexagon::LDriuh_cPt :
1976 case Hexagon::LDriuh_cdnPt :
1977 case Hexagon::LDriuh_indexed_cPt :
1978 case Hexagon::LDriuh_indexed_cdnPt :
1979 case Hexagon::POST_LDriuh_cPt :
1980 case Hexagon::POST_LDriuh_cdnPt_V4 :
1981 case Hexagon::LDriub_cPt :
1982 case Hexagon::LDriub_cdnPt :
1983 case Hexagon::LDriub_indexed_cPt :
1984 case Hexagon::LDriub_indexed_cdnPt :
1985 case Hexagon::POST_LDriub_cPt :
1986 case Hexagon::POST_LDriub_cdnPt_V4 :
1987 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1988 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1989 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1990 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1991 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1992 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1993 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1994 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1995 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1996 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1997 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1998 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1999 case Hexagon::ADD_ri_cPt :
2000 case Hexagon::ADD_ri_cdnPt :
2001 case Hexagon::ADD_rr_cPt :
2002 case Hexagon::ADD_rr_cdnPt :
2003 case Hexagon::XOR_rr_cPt :
2004 case Hexagon::XOR_rr_cdnPt :
2005 case Hexagon::AND_rr_cPt :
2006 case Hexagon::AND_rr_cdnPt :
2007 case Hexagon::OR_rr_cPt :
2008 case Hexagon::OR_rr_cdnPt :
2009 case Hexagon::SUB_rr_cPt :
2010 case Hexagon::SUB_rr_cdnPt :
2011 case Hexagon::COMBINE_rr_cPt :
2012 case Hexagon::COMBINE_rr_cdnPt :
2013 case Hexagon::ASLH_cPt_V4 :
2014 case Hexagon::ASLH_cdnPt_V4 :
2015 case Hexagon::ASRH_cPt_V4 :
2016 case Hexagon::ASRH_cdnPt_V4 :
2017 case Hexagon::SXTB_cPt_V4 :
2018 case Hexagon::SXTB_cdnPt_V4 :
2019 case Hexagon::SXTH_cPt_V4 :
2020 case Hexagon::SXTH_cdnPt_V4 :
2021 case Hexagon::ZXTB_cPt_V4 :
2022 case Hexagon::ZXTB_cdnPt_V4 :
2023 case Hexagon::ZXTH_cPt_V4 :
2024 case Hexagon::ZXTH_cdnPt_V4 :
2025 case Hexagon::LDd_GP_cPt_V4 :
2026 case Hexagon::LDb_GP_cPt_V4 :
2027 case Hexagon::LDub_GP_cPt_V4 :
2028 case Hexagon::LDh_GP_cPt_V4 :
2029 case Hexagon::LDuh_GP_cPt_V4 :
2030 case Hexagon::LDw_GP_cPt_V4 :
2031 case Hexagon::STd_GP_cPt_V4 :
2032 case Hexagon::STb_GP_cPt_V4 :
2033 case Hexagon::STh_GP_cPt_V4 :
2034 case Hexagon::STw_GP_cPt_V4 :
2035 case Hexagon::LDd_GP_cdnPt_V4 :
2036 case Hexagon::LDb_GP_cdnPt_V4 :
2037 case Hexagon::LDub_GP_cdnPt_V4 :
2038 case Hexagon::LDh_GP_cdnPt_V4 :
2039 case Hexagon::LDuh_GP_cdnPt_V4 :
2040 case Hexagon::LDw_GP_cdnPt_V4 :
2041 case Hexagon::STd_GP_cdnPt_V4 :
2042 case Hexagon::STb_GP_cdnPt_V4 :
2043 case Hexagon::STh_GP_cdnPt_V4 :
2044 case Hexagon::STw_GP_cdnPt_V4 :
2047 case Hexagon::TFR_cNotPt:
2048 case Hexagon::TFR_cdnNotPt:
2049 case Hexagon::TFRI_cNotPt:
2050 case Hexagon::TFRI_cdnNotPt:
2051 case Hexagon::STrib_cNotPt :
2052 case Hexagon::STrib_cdnNotPt_V4 :
2053 case Hexagon::STrib_indexed_cNotPt :
2054 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2055 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2056 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2057 case Hexagon::POST_STbri_cNotPt :
2058 case Hexagon::POST_STbri_cdnNotPt_V4 :
2059 case Hexagon::STrih_cNotPt :
2060 case Hexagon::STrih_cdnNotPt_V4 :
2061 case Hexagon::STrih_indexed_cNotPt :
2062 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2063 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2064 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2065 case Hexagon::POST_SThri_cNotPt :
2066 case Hexagon::POST_SThri_cdnNotPt_V4 :
2067 case Hexagon::STriw_cNotPt :
2068 case Hexagon::STriw_cdnNotPt_V4 :
2069 case Hexagon::STriw_indexed_cNotPt :
2070 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2071 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2072 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2073 case Hexagon::POST_STwri_cNotPt :
2074 case Hexagon::POST_STwri_cdnNotPt_V4 :
2075 case Hexagon::STrib_imm_cNotPt_V4 :
2076 case Hexagon::STrib_imm_cdnNotPt_V4 :
2077 case Hexagon::STrid_cNotPt :
2078 case Hexagon::STrid_cdnNotPt_V4 :
2079 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2080 case Hexagon::STrid_indexed_cNotPt :
2081 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
2082 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2083 case Hexagon::POST_STdri_cNotPt :
2084 case Hexagon::POST_STdri_cdnNotPt_V4 :
2085 case Hexagon::STrih_imm_cNotPt_V4 :
2086 case Hexagon::STrih_imm_cdnNotPt_V4 :
2087 case Hexagon::STriw_imm_cNotPt_V4 :
2088 case Hexagon::STriw_imm_cdnNotPt_V4 :
2089 case Hexagon::JMP_fnew_t :
2090 case Hexagon::LDrid_cNotPt :
2091 case Hexagon::LDrid_cdnNotPt :
2092 case Hexagon::LDrid_indexed_cNotPt :
2093 case Hexagon::LDrid_indexed_cdnNotPt :
2094 case Hexagon::POST_LDrid_cNotPt :
2095 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2096 case Hexagon::LDriw_cNotPt :
2097 case Hexagon::LDriw_cdnNotPt :
2098 case Hexagon::LDriw_indexed_cNotPt :
2099 case Hexagon::LDriw_indexed_cdnNotPt :
2100 case Hexagon::POST_LDriw_cNotPt :
2101 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2102 case Hexagon::LDrih_cNotPt :
2103 case Hexagon::LDrih_cdnNotPt :
2104 case Hexagon::LDrih_indexed_cNotPt :
2105 case Hexagon::LDrih_indexed_cdnNotPt :
2106 case Hexagon::POST_LDrih_cNotPt :
2107 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2108 case Hexagon::LDrib_cNotPt :
2109 case Hexagon::LDrib_cdnNotPt :
2110 case Hexagon::LDrib_indexed_cNotPt :
2111 case Hexagon::LDrib_indexed_cdnNotPt :
2112 case Hexagon::POST_LDrib_cNotPt :
2113 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2114 case Hexagon::LDriuh_cNotPt :
2115 case Hexagon::LDriuh_cdnNotPt :
2116 case Hexagon::LDriuh_indexed_cNotPt :
2117 case Hexagon::LDriuh_indexed_cdnNotPt :
2118 case Hexagon::POST_LDriuh_cNotPt :
2119 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2120 case Hexagon::LDriub_cNotPt :
2121 case Hexagon::LDriub_cdnNotPt :
2122 case Hexagon::LDriub_indexed_cNotPt :
2123 case Hexagon::LDriub_indexed_cdnNotPt :
2124 case Hexagon::POST_LDriub_cNotPt :
2125 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2126 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2127 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2128 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2129 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2130 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2131 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2132 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2133 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2134 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2135 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2136 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2137 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2138 case Hexagon::ADD_ri_cNotPt :
2139 case Hexagon::ADD_ri_cdnNotPt :
2140 case Hexagon::ADD_rr_cNotPt :
2141 case Hexagon::ADD_rr_cdnNotPt :
2142 case Hexagon::XOR_rr_cNotPt :
2143 case Hexagon::XOR_rr_cdnNotPt :
2144 case Hexagon::AND_rr_cNotPt :
2145 case Hexagon::AND_rr_cdnNotPt :
2146 case Hexagon::OR_rr_cNotPt :
2147 case Hexagon::OR_rr_cdnNotPt :
2148 case Hexagon::SUB_rr_cNotPt :
2149 case Hexagon::SUB_rr_cdnNotPt :
2150 case Hexagon::COMBINE_rr_cNotPt :
2151 case Hexagon::COMBINE_rr_cdnNotPt :
2152 case Hexagon::ASLH_cNotPt_V4 :
2153 case Hexagon::ASLH_cdnNotPt_V4 :
2154 case Hexagon::ASRH_cNotPt_V4 :
2155 case Hexagon::ASRH_cdnNotPt_V4 :
2156 case Hexagon::SXTB_cNotPt_V4 :
2157 case Hexagon::SXTB_cdnNotPt_V4 :
2158 case Hexagon::SXTH_cNotPt_V4 :
2159 case Hexagon::SXTH_cdnNotPt_V4 :
2160 case Hexagon::ZXTB_cNotPt_V4 :
2161 case Hexagon::ZXTB_cdnNotPt_V4 :
2162 case Hexagon::ZXTH_cNotPt_V4 :
2163 case Hexagon::ZXTH_cdnNotPt_V4 :
2165 case Hexagon::LDd_GP_cNotPt_V4 :
2166 case Hexagon::LDb_GP_cNotPt_V4 :
2167 case Hexagon::LDub_GP_cNotPt_V4 :
2168 case Hexagon::LDh_GP_cNotPt_V4 :
2169 case Hexagon::LDuh_GP_cNotPt_V4 :
2170 case Hexagon::LDw_GP_cNotPt_V4 :
2171 case Hexagon::STd_GP_cNotPt_V4 :
2172 case Hexagon::STb_GP_cNotPt_V4 :
2173 case Hexagon::STh_GP_cNotPt_V4 :
2174 case Hexagon::STw_GP_cNotPt_V4 :
2175 case Hexagon::LDd_GP_cdnNotPt_V4 :
2176 case Hexagon::LDb_GP_cdnNotPt_V4 :
2177 case Hexagon::LDub_GP_cdnNotPt_V4 :
2178 case Hexagon::LDh_GP_cdnNotPt_V4 :
2179 case Hexagon::LDuh_GP_cdnNotPt_V4 :
2180 case Hexagon::LDw_GP_cdnNotPt_V4 :
2181 case Hexagon::STd_GP_cdnNotPt_V4 :
2182 case Hexagon::STb_GP_cdnNotPt_V4 :
2183 case Hexagon::STh_GP_cdnNotPt_V4 :
2184 case Hexagon::STw_GP_cdnNotPt_V4 :
2187 // return *some value* to avoid compiler warning
2191 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
2192 const HexagonInstrInfo *QII) {
2193 assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
2195 // Post Increment means duplicates. Use dense map to find duplicates in the
2196 // list. Caution: Densemap initializes with the minimum of 64 buckets,
2197 // whereas there are at most 5 operands in the post increment.
2198 DenseMap<unsigned, unsigned> DefRegsSet;
2199 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2200 if (MI->getOperand(opNum).isReg() &&
2201 MI->getOperand(opNum).isDef()) {
2202 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
2205 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2206 if (MI->getOperand(opNum).isReg() &&
2207 MI->getOperand(opNum).isUse()) {
2208 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
2209 return MI->getOperand(opNum);
2213 if (MI->getDesc().mayLoad()) {
2214 // The 2nd operand is always the post increment operand in load.
2215 assert(MI->getOperand(1).isReg() &&
2216 "Post increment operand has be to a register.");
2217 return (MI->getOperand(1));
2219 if (MI->getDesc().mayStore()) {
2220 // The 1st operand is always the post increment operand in store.
2221 assert(MI->getOperand(0).isReg() &&
2222 "Post increment operand has be to a register.");
2223 return (MI->getOperand(0));
2226 // we should never come here.
2227 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
2230 // get the value being stored
2231 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
2232 // value being stored is always the last operand.
2233 return (MI->getOperand(MI->getNumOperands()-1));
2236 // can be new value store?
2237 // Following restrictions are to be respected in convert a store into
2238 // a new value store.
2239 // 1. If an instruction uses auto-increment, its address register cannot
2240 // be a new-value register. Arch Spec 5.4.2.1
2241 // 2. If an instruction uses absolute-set addressing mode,
2242 // its address register cannot be a new-value register.
2243 // Arch Spec 5.4.2.1.TODO: This is not enabled as
2244 // as absolute-set address mode patters are not implemented.
2245 // 3. If an instruction produces a 64-bit result, its registers cannot be used
2246 // as new-value registers. Arch Spec 5.4.2.2.
2247 // 4. If the instruction that sets a new-value register is conditional, then
2248 // the instruction that uses the new-value register must also be conditional,
2249 // and both must always have their predicates evaluate identically.
2250 // Arch Spec 5.4.2.3.
2251 // 5. There is an implied restriction of a packet can not have another store,
2252 // if there is a new value store in the packet. Corollary, if there is
2253 // already a store in a packet, there can not be a new value store.
2254 // Arch Spec: 3.4.4.2
2255 bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
2256 MachineInstr *PacketMI, unsigned DepReg,
2257 std::map <MachineInstr*, SUnit*> MIToSUnit)
2259 // Make sure we are looking at the store
2260 if (!IsNewifyStore(MI))
2263 // Make sure there is dependency and can be new value'ed
2264 if (GetStoreValueOperand(MI).isReg() &&
2265 GetStoreValueOperand(MI).getReg() != DepReg)
2268 const HexagonRegisterInfo* QRI =
2269 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2270 const MCInstrDesc& MCID = PacketMI->getDesc();
2271 // first operand is always the result
2273 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2274 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
2276 // if there is already an store in the packet, no can do new value store
2277 // Arch Spec 3.4.4.2.
2278 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
2279 VE = CurrentPacketMIs.end();
2281 SUnit* PacketSU = MIToSUnit[*VI];
2282 if (PacketSU->getInstr()->getDesc().mayStore() ||
2283 // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
2284 // then we don't need this
2285 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2286 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
2290 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
2291 // new value store constraint: double regs can not feed into new value store
2292 // arch spec section: 5.4.2.2
2296 // Make sure it's NOT the post increment register that we are going to
2298 if (QII->isPostIncrement(MI) &&
2299 MI->getDesc().mayStore() &&
2300 GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
2304 if (QII->isPostIncrement(PacketMI) &&
2305 PacketMI->getDesc().mayLoad() &&
2306 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
2307 // if source is post_inc, or absolute-set addressing,
2308 // it can not feed into new value store
2309 // r3 = memw(r2++#4)
2310 // memw(r30 + #-1404) = r2.new -> can not be new value store
2311 // arch spec section: 5.4.2.1
2315 // If the source that feeds the store is predicated, new value store must
2316 // also be also predicated.
2317 if (QII->isPredicated(PacketMI)) {
2318 if (!QII->isPredicated(MI))
2321 // Check to make sure that they both will have their predicates
2322 // evaluate identically
2323 unsigned predRegNumSrc = 0;
2324 unsigned predRegNumDst = 0;
2325 const TargetRegisterClass* predRegClass = NULL;
2327 // Get predicate register used in the source instruction
2328 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2329 if ( PacketMI->getOperand(opNum).isReg())
2330 predRegNumSrc = PacketMI->getOperand(opNum).getReg();
2331 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
2332 if (predRegClass == &Hexagon::PredRegsRegClass) {
2336 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2337 ("predicate register not found in a predicated PacketMI instruction"));
2339 // Get predicate register used in new-value store instruction
2340 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2341 if ( MI->getOperand(opNum).isReg())
2342 predRegNumDst = MI->getOperand(opNum).getReg();
2343 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
2344 if (predRegClass == &Hexagon::PredRegsRegClass) {
2348 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2349 ("predicate register not found in a predicated MI instruction"));
2351 // New-value register producer and user (store) need to satisfy these
2353 // 1) Both instructions should be predicated on the same register.
2354 // 2) If producer of the new-value register is .new predicated then store
2355 // should also be .new predicated and if producer is not .new predicated
2356 // then store should not be .new predicated.
2357 // 3) Both new-value register producer and user should have same predicate
2358 // sense, i.e, either both should be negated or both should be none negated.
2360 if (( predRegNumDst != predRegNumSrc) ||
2361 QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI) ||
2362 GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
2367 // Make sure that other than the new-value register no other store instruction
2368 // register has been modified in the same packet. Predicate registers can be
2369 // modified by they should not be modified between the producer and the store
2370 // instruction as it will make them both conditional on different values.
2371 // We already know this to be true for all the instructions before and
2372 // including PacketMI. Howerver, we need to perform the check for the
2373 // remaining instructions in the packet.
2375 std::vector<MachineInstr*>::iterator VI;
2376 std::vector<MachineInstr*>::iterator VE;
2377 unsigned StartCheck = 0;
2379 for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
2381 SUnit* TempSU = MIToSUnit[*VI];
2382 MachineInstr* TempMI = TempSU->getInstr();
2384 // Following condition is true for all the instructions until PacketMI is
2385 // reached (StartCheck is set to 0 before the for loop).
2386 // StartCheck flag is 1 for all the instructions after PacketMI.
2387 if (TempMI != PacketMI && !StartCheck) // start processing only after
2388 continue; // encountering PacketMI
2391 if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
2394 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2395 if (MI->getOperand(opNum).isReg() &&
2396 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
2402 // Make sure that for non POST_INC stores:
2403 // 1. The only use of reg is DepReg and no other registers.
2404 // This handles V4 base+index registers.
2405 // The following store can not be dot new.
2406 // Eg. r0 = add(r0, #3)a
2407 // memw(r1+r0<<#2) = r0
2408 if (!QII->isPostIncrement(MI) &&
2409 GetStoreValueOperand(MI).isReg() &&
2410 GetStoreValueOperand(MI).getReg() == DepReg) {
2411 for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
2412 if (MI->getOperand(opNum).isReg() &&
2413 MI->getOperand(opNum).getReg() == DepReg) {
2417 // 2. If data definition is because of implicit definition of the register,
2418 // do not newify the store. Eg.
2419 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
2420 // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
2421 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2422 if (PacketMI->getOperand(opNum).isReg() &&
2423 PacketMI->getOperand(opNum).getReg() == DepReg &&
2424 PacketMI->getOperand(opNum).isDef() &&
2425 PacketMI->getOperand(opNum).isImplicit()) {
2431 // Can be dot new store.
2435 // can this MI to promoted to either
2436 // new value store or new value jump
2437 bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
2438 SUnit *PacketSU, unsigned DepReg,
2439 std::map <MachineInstr*, SUnit*> MIToSUnit,
2440 MachineBasicBlock::iterator &MII)
2443 const HexagonRegisterInfo* QRI =
2444 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2445 if (!QRI->Subtarget.hasV4TOps() ||
2449 MachineInstr *PacketMI = PacketSU->getInstr();
2451 // Check to see the store can be new value'ed.
2452 if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
2455 // Check to see the compare/jump can be new value'ed.
2456 // This is done as a pass on its own. Don't need to check it here.
2460 // Check to see if an instruction can be dot new
2461 // There are three kinds.
2462 // 1. dot new on predicate - V2/V3/V4
2463 // 2. dot new on stores NV/ST - V4
2464 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
2465 bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
2466 SUnit *PacketSU, unsigned DepReg,
2467 std::map <MachineInstr*, SUnit*> MIToSUnit,
2468 MachineBasicBlock::iterator &MII,
2469 const TargetRegisterClass* RC )
2471 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2472 // Already a dot new instruction.
2473 if (QII->isDotNewInst(MI) && !IsNewifyStore(MI))
2476 if (!isNewifiable(MI))
2480 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
2482 else if (RC != &Hexagon::PredRegsRegClass &&
2483 !IsNewifyStore(MI)) // MI is not a new-value store
2486 // Create a dot new machine instruction to see if resources can be
2487 // allocated. If not, bail out now.
2488 int NewOpcode = GetDotNewOp(MI->getOpcode());
2489 const MCInstrDesc &desc = QII->get(NewOpcode);
2491 MachineInstr *NewMI =
2492 MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
2493 bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
2494 MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
2496 if (!ResourcesAvailable)
2499 // new value store only
2500 // new new value jump generated as a passes
2501 if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
2508 // Go through the packet instructions and search for anti dependency
2509 // between them and DepReg from MI
2510 // Consider this case:
2512 // a) %R1<def> = TFRI_cdNotPt %P3, 2
2515 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
2516 // c) %P3<def> = TFR_PdRs %R23
2517 // d) %R1<def> = TFRI_cdnPt %P3, 4
2519 // The P3 from a) and d) will be complements after
2520 // a)'s P3 is converted to .new form
2521 // Anti Dep between c) and b) is irrelevant for this case
2522 bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
2524 std::map <MachineInstr*, SUnit*> MIToSUnit) {
2526 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2527 SUnit* PacketSUDep = MIToSUnit[MI];
2529 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2530 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2532 // We only care for dependencies to predicated instructions
2533 if(!QII->isPredicated(*VIN)) continue;
2535 // Scheduling Unit for current insn in the packet
2536 SUnit* PacketSU = MIToSUnit[*VIN];
2538 // Look at dependencies between current members of the packet
2539 // and predicate defining instruction MI.
2540 // Make sure that dependency is on the exact register
2542 if (PacketSU->isSucc(PacketSUDep)) {
2543 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2544 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
2545 (PacketSU->Succs[i].getKind() == SDep::Anti) &&
2546 (PacketSU->Succs[i].getReg() == DepReg)) {
2557 // Given two predicated instructions, this function detects whether
2558 // the predicates are complements
2559 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
2560 MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
2562 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2563 // Currently can only reason about conditional transfers
2564 if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
2568 // Scheduling unit for candidate
2569 SUnit* SU = MIToSUnit[MI1];
2571 // One corner case deals with the following scenario:
2573 // a) %R24<def> = TFR_cPt %P0, %R25
2577 // b) %R25<def> = TFR_cNotPt %P0, %R24
2578 // c) %P0<def> = CMPEQri %R26, 1
2581 // On general check a) and b) are complements, but
2582 // presence of c) will convert a) to .new form, and
2583 // then it is not a complement
2584 // We attempt to detect it by analyzing existing
2585 // dependencies in the packet
2587 // Analyze relationships between all existing members of the packet.
2588 // Look for Anti dependecy on the same predicate reg
2589 // as used in the candidate
2590 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2591 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2593 // Scheduling Unit for current insn in the packet
2594 SUnit* PacketSU = MIToSUnit[*VIN];
2596 // If this instruction in the packet is succeeded by the candidate...
2597 if (PacketSU->isSucc(SU)) {
2598 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2599 // The corner case exist when there is true data
2600 // dependency between candidate and one of current
2601 // packet members, this dep is on predicate reg, and
2602 // there already exist anti dep on the same pred in
2604 if (PacketSU->Succs[i].getSUnit() == SU &&
2605 Hexagon::PredRegsRegClass.contains(
2606 PacketSU->Succs[i].getReg()) &&
2607 PacketSU->Succs[i].getKind() == SDep::Data &&
2608 // Here I know that *VIN is predicate setting instruction
2609 // with true data dep to candidate on the register
2610 // we care about - c) in the above example.
2611 // Now I need to see if there is an anti dependency
2612 // from c) to any other instruction in the
2613 // same packet on the pred reg of interest
2614 RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
2622 // If the above case does not apply, check regular
2623 // complement condition.
2624 // Check that the predicate register is the same and
2625 // that the predicate sense is different
2626 // We also need to differentiate .old vs. .new:
2627 // !p0 is not complimentary to p0.new
2628 return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
2629 (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
2630 (QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
2633 // initPacketizerState - Initialize packetizer flags
2634 void HexagonPacketizerList::initPacketizerState() {
2637 PromotedToDotNew = false;
2638 GlueToNewValueJump = false;
2639 GlueAllocframeStore = false;
2640 FoundSequentialDependence = false;
2645 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
2646 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
2647 MachineBasicBlock *MBB) {
2648 if (MI->isDebugValue())
2651 // We must print out inline assembly
2652 if (MI->isInlineAsm())
2655 // We check if MI has any functional units mapped to it.
2656 // If it doesn't, we ignore the instruction.
2657 const MCInstrDesc& TID = MI->getDesc();
2658 unsigned SchedClass = TID.getSchedClass();
2659 const InstrStage* IS =
2660 ResourceTracker->getInstrItins()->beginStage(SchedClass);
2661 unsigned FuncUnits = IS->getUnits();
2665 // isSoloInstruction: - Returns true for instructions that must be
2666 // scheduled in their own packet.
2667 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
2669 if (MI->isInlineAsm())
2672 if (MI->isEHLabel())
2675 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
2676 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
2677 // They must not be grouped with other instructions in a packet.
2678 if (IsSchedBarrier(MI))
2684 // isLegalToPacketizeTogether:
2685 // SUI is the current instruction that is out side of the current packet.
2686 // SUJ is the current instruction inside the current packet against which that
2687 // SUI will be packetized.
2688 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
2689 MachineInstr *I = SUI->getInstr();
2690 MachineInstr *J = SUJ->getInstr();
2691 assert(I && J && "Unable to packetize null instruction!");
2693 const MCInstrDesc &MCIDI = I->getDesc();
2694 const MCInstrDesc &MCIDJ = J->getDesc();
2696 MachineBasicBlock::iterator II = I;
2698 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
2699 const HexagonRegisterInfo* QRI =
2700 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2701 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2703 // Inline asm cannot go in the packet.
2704 if (I->getOpcode() == Hexagon::INLINEASM)
2705 llvm_unreachable("Should not meet inline asm here!");
2707 if (isSoloInstruction(I))
2708 llvm_unreachable("Should not meet solo instr here!");
2710 // A save callee-save register function call can only be in a packet
2711 // with instructions that don't write to the callee-save registers.
2712 if ((QII->isSaveCalleeSavedRegsCall(I) &&
2713 DoesModifyCalleeSavedReg(J, QRI)) ||
2714 (QII->isSaveCalleeSavedRegsCall(J) &&
2715 DoesModifyCalleeSavedReg(I, QRI))) {
2720 // Two control flow instructions cannot go in the same packet.
2721 if (IsControlFlow(I) && IsControlFlow(J)) {
2726 // A LoopN instruction cannot appear in the same packet as a jump or call.
2727 if (IsLoopN(I) && ( IsDirectJump(J)
2729 || QII->isDeallocRet(J))) {
2733 if (IsLoopN(J) && ( IsDirectJump(I)
2735 || QII->isDeallocRet(I))) {
2740 // dealloc_return cannot appear in the same packet as a conditional or
2741 // unconditional jump.
2742 if (QII->isDeallocRet(I) && ( MCIDJ.isBranch()
2744 || MCIDJ.isBarrier())) {
2750 // V4 allows dual store. But does not allow second store, if the
2751 // first store is not in SLOT0. New value store, new value jump,
2752 // dealloc_return and memop always take SLOT0.
2753 // Arch spec 3.4.4.2
2754 if (QRI->Subtarget.hasV4TOps()) {
2755 if (MCIDI.mayStore() && MCIDJ.mayStore() &&
2756 (QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
2761 if ((QII->isMemOp(J) && MCIDI.mayStore())
2762 || (MCIDJ.mayStore() && QII->isMemOp(I))
2763 || (QII->isMemOp(J) && QII->isMemOp(I))) {
2769 if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
2774 // If an instruction feeds new value jump, glue it.
2775 MachineBasicBlock::iterator NextMII = I;
2777 MachineInstr *NextMI = NextMII;
2779 if (QII->isNewValueJump(NextMI)) {
2781 bool secondRegMatch = false;
2782 bool maintainNewValueJump = false;
2784 if (NextMI->getOperand(1).isReg() &&
2785 I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
2786 secondRegMatch = true;
2787 maintainNewValueJump = true;
2790 if (!secondRegMatch &&
2791 I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
2792 maintainNewValueJump = true;
2795 for (std::vector<MachineInstr*>::iterator
2796 VI = CurrentPacketMIs.begin(),
2797 VE = CurrentPacketMIs.end();
2798 (VI != VE && maintainNewValueJump); ++VI) {
2799 SUnit* PacketSU = MIToSUnit[*VI];
2801 // NVJ can not be part of the dual jump - Arch Spec: section 7.8
2802 if (PacketSU->getInstr()->getDesc().isCall()) {
2807 // 1. Packet does not have a store in it.
2808 // 2. If the first operand of the nvj is newified, and the second
2809 // operand is also a reg, it (second reg) is not defined in
2811 // 3. If the second operand of the nvj is newified, (which means
2812 // first operand is also a reg), first reg is not defined in
2814 if (PacketSU->getInstr()->getDesc().mayStore() ||
2815 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2817 (!secondRegMatch && NextMI->getOperand(1).isReg() &&
2818 PacketSU->getInstr()->modifiesRegister(
2819 NextMI->getOperand(1).getReg(), QRI)) ||
2822 PacketSU->getInstr()->modifiesRegister(
2823 NextMI->getOperand(0).getReg(), QRI))) {
2829 GlueToNewValueJump = true;
2835 if (SUJ->isSucc(SUI)) {
2836 for (unsigned i = 0;
2837 (i < SUJ->Succs.size()) && !FoundSequentialDependence;
2840 if (SUJ->Succs[i].getSUnit() != SUI) {
2844 SDep::Kind DepType = SUJ->Succs[i].getKind();
2846 // For direct calls:
2847 // Ignore register dependences for call instructions for
2848 // packetization purposes except for those due to r31 and
2849 // predicate registers.
2851 // For indirect calls:
2852 // Same as direct calls + check for true dependences to the register
2853 // used in the indirect call.
2855 // We completely ignore Order dependences for call instructions
2858 // Ignore register dependences for return instructions like jumpr,
2859 // dealloc return unless we have dependencies on the explicit uses
2860 // of the registers used by jumpr (like r31) or dealloc return
2861 // (like r29 or r30).
2863 // TODO: Currently, jumpr is handling only return of r31. So, the
2864 // following logic (specificaly IsCallDependent) is working fine.
2865 // We need to enable jumpr for register other than r31 and then,
2866 // we need to rework the last part, where it handles indirect call
2867 // of that (IsCallDependent) function. Bug 6216 is opened for this.
2869 unsigned DepReg = 0;
2870 const TargetRegisterClass* RC = NULL;
2871 if (DepType == SDep::Data) {
2872 DepReg = SUJ->Succs[i].getReg();
2873 RC = QRI->getMinimalPhysRegClass(DepReg);
2875 if ((MCIDI.isCall() || MCIDI.isReturn()) &&
2876 (!IsRegDependence(DepType) ||
2877 !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
2881 // For instructions that can be promoted to dot-new, try to promote.
2882 else if ((DepType == SDep::Data) &&
2883 CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
2884 PromoteToDotNew(I, DepType, II, RC)) {
2885 PromotedToDotNew = true;
2889 else if ((DepType == SDep::Data) &&
2890 (QII->isNewValueJump(I))) {
2894 // For predicated instructions, if the predicates are complements
2895 // then there can be no dependence.
2896 else if (QII->isPredicated(I) &&
2897 QII->isPredicated(J) &&
2898 ArePredicatesComplements(I, J, MIToSUnit)) {
2902 else if (IsDirectJump(I) &&
2903 !MCIDJ.isBranch() &&
2905 (DepType == SDep::Order)) {
2906 // Ignore Order dependences between unconditional direct branches
2907 // and non-control-flow instructions
2910 else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
2911 (DepType != SDep::Output)) {
2912 // Ignore all dependences for jumps except for true and output
2917 // Ignore output dependences due to superregs. We can
2918 // write to two different subregisters of R1:0 for instance
2919 // in the same cycle
2924 // If neither I nor J defines DepReg, then this is a
2925 // superfluous output dependence. The dependence must be of the
2929 // and there is an output dependence between the two instructions
2932 // We want to ignore these dependences.
2933 // Ideally, the dependence constructor should annotate such
2934 // dependences. We can then avoid this relatively expensive check.
2936 else if (DepType == SDep::Output) {
2937 // DepReg is the register that's responsible for the dependence.
2938 unsigned DepReg = SUJ->Succs[i].getReg();
2940 // Check if I and J really defines DepReg.
2941 if (I->definesRegister(DepReg) ||
2942 J->definesRegister(DepReg)) {
2943 FoundSequentialDependence = true;
2948 // We ignore Order dependences for
2949 // 1. Two loads unless they are volatile.
2950 // 2. Two stores in V4 unless they are volatile.
2951 else if ((DepType == SDep::Order) &&
2952 !I->hasOrderedMemoryRef() &&
2953 !J->hasOrderedMemoryRef()) {
2954 if (QRI->Subtarget.hasV4TOps() &&
2955 // hexagonv4 allows dual store.
2956 MCIDI.mayStore() && MCIDJ.mayStore()) {
2959 // store followed by store-- not OK on V2
2960 // store followed by load -- not OK on all (OK if addresses
2962 // load followed by store -- OK on all
2963 // load followed by load -- OK on all
2964 else if ( !MCIDJ.mayStore()) {
2968 FoundSequentialDependence = true;
2973 // For V4, special case ALLOCFRAME. Even though there is dependency
2974 // between ALLOCAFRAME and subsequent store, allow it to be
2975 // packetized in a same packet. This implies that the store is using
2976 // caller's SP. Hense, offset needs to be updated accordingly.
2977 else if (DepType == SDep::Data
2978 && QRI->Subtarget.hasV4TOps()
2979 && J->getOpcode() == Hexagon::ALLOCFRAME
2980 && (I->getOpcode() == Hexagon::STrid
2981 || I->getOpcode() == Hexagon::STriw
2982 || I->getOpcode() == Hexagon::STrib)
2983 && I->getOperand(0).getReg() == QRI->getStackRegister()
2984 && QII->isValidOffset(I->getOpcode(),
2985 I->getOperand(1).getImm() -
2986 (FrameSize + HEXAGON_LRFP_SIZE)))
2988 GlueAllocframeStore = true;
2989 // Since this store is to be glued with allocframe in the same
2990 // packet, it will use SP of the previous stack frame, i.e
2991 // caller's SP. Therefore, we need to recalculate offset according
2993 I->getOperand(1).setImm(I->getOperand(1).getImm() -
2994 (FrameSize + HEXAGON_LRFP_SIZE));
2998 // Skip over anti-dependences. Two instructions that are
2999 // anti-dependent can share a packet
3001 else if (DepType != SDep::Anti) {
3002 FoundSequentialDependence = true;
3007 if (FoundSequentialDependence) {
3016 // isLegalToPruneDependencies
3017 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
3018 MachineInstr *I = SUI->getInstr();
3019 assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
3021 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3025 // Check if the instruction was promoted to a dot-new. If so, demote it
3026 // back into a dot-old.
3027 if (PromotedToDotNew) {
3031 // Check if the instruction (must be a store) was glued with an Allocframe
3032 // instruction. If so, restore its offset to its original value, i.e. use
3033 // curent SP instead of caller's SP.
3034 if (GlueAllocframeStore) {
3035 I->getOperand(1).setImm(I->getOperand(1).getImm() +
3036 FrameSize + HEXAGON_LRFP_SIZE);
3044 MachineBasicBlock::iterator
3045 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
3047 MachineBasicBlock::iterator MII = MI;
3048 MachineBasicBlock *MBB = MI->getParent();
3050 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3052 if (GlueToNewValueJump) {
3055 MachineInstr *nvjMI = MII;
3056 assert(ResourceTracker->canReserveResources(MI));
3057 ResourceTracker->reserveResources(MI);
3058 if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
3059 !tryAllocateResourcesForConstExt(MI)) {
3061 ResourceTracker->reserveResources(MI);
3062 assert(canReserveResourcesForConstExt(MI) &&
3063 "Ensure that there is a slot");
3064 reserveResourcesForConstExt(MI);
3065 // Reserve resources for new value jump constant extender.
3066 assert(canReserveResourcesForConstExt(MI) &&
3067 "Ensure that there is a slot");
3068 reserveResourcesForConstExt(nvjMI);
3069 assert(ResourceTracker->canReserveResources(nvjMI) &&
3070 "Ensure that there is a slot");
3072 } else if ( // Extended instruction takes two slots in the packet.
3073 // Try reserve and allocate 4-byte in the current packet first.
3074 (QII->isExtended(nvjMI)
3075 && (!tryAllocateResourcesForConstExt(nvjMI)
3076 || !ResourceTracker->canReserveResources(nvjMI)))
3077 || // For non-extended instruction, no need to allocate extra 4 bytes.
3078 (!QII->isExtended(nvjMI) &&
3079 !ResourceTracker->canReserveResources(nvjMI)))
3082 // A new and empty packet starts.
3083 // We are sure that the resources requirements can be satisfied.
3084 // Therefore, do not need to call "canReserveResources" anymore.
3085 ResourceTracker->reserveResources(MI);
3086 if (QII->isExtended(nvjMI))
3087 reserveResourcesForConstExt(nvjMI);
3089 // Here, we are sure that "reserveResources" would succeed.
3090 ResourceTracker->reserveResources(nvjMI);
3091 CurrentPacketMIs.push_back(MI);
3092 CurrentPacketMIs.push_back(nvjMI);
3094 if ( (QII->isExtended(MI) || QII->isConstExtended(MI))
3095 && ( !tryAllocateResourcesForConstExt(MI)
3096 || !ResourceTracker->canReserveResources(MI)))
3099 // Check if the instruction was promoted to a dot-new. If so, demote it
3100 // back into a dot-old
3101 if (PromotedToDotNew) {
3104 reserveResourcesForConstExt(MI);
3106 // In case that "MI" is not an extended insn,
3107 // the resource availability has already been checked.
3108 ResourceTracker->reserveResources(MI);
3109 CurrentPacketMIs.push_back(MI);
3114 //===----------------------------------------------------------------------===//
3115 // Public Constructor Functions
3116 //===----------------------------------------------------------------------===//
3118 FunctionPass *llvm::createHexagonPacketizer() {
3119 return new HexagonPacketizer();