1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "packets"
21 #include "HexagonMachineFunctionInfo.h"
22 #include "HexagonRegisterInfo.h"
23 #include "HexagonSubtarget.h"
24 #include "HexagonTargetMachine.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/CodeGen/DFAPacketizer.h"
28 #include "llvm/CodeGen/LatencyPriorityQueue.h"
29 #include "llvm/CodeGen/MachineDominators.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/ScheduleDAG.h"
38 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
39 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
40 #include "llvm/CodeGen/SchedulerRegistry.h"
41 #include "llvm/MC/MCInstrItineraries.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetRegisterInfo.h"
54 class HexagonPacketizer : public MachineFunctionPass {
58 HexagonPacketizer() : MachineFunctionPass(ID) {}
60 void getAnalysisUsage(AnalysisUsage &AU) const {
62 AU.addRequired<MachineDominatorTree>();
63 AU.addPreserved<MachineDominatorTree>();
64 AU.addRequired<MachineLoopInfo>();
65 AU.addPreserved<MachineLoopInfo>();
66 MachineFunctionPass::getAnalysisUsage(AU);
69 const char *getPassName() const {
70 return "Hexagon Packetizer";
73 bool runOnMachineFunction(MachineFunction &Fn);
75 char HexagonPacketizer::ID = 0;
77 class HexagonPacketizerList : public VLIWPacketizerList {
81 // Has the instruction been promoted to a dot-new instruction.
82 bool PromotedToDotNew;
84 // Has the instruction been glued to allocframe.
85 bool GlueAllocframeStore;
87 // Has the feeder instruction been glued to new value jump.
88 bool GlueToNewValueJump;
90 // Check if there is a dependence between some instruction already in this
91 // packet and this instruction.
94 // Only check for dependence if there are resources available to
95 // schedule this instruction.
96 bool FoundSequentialDependence;
100 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
101 MachineDominatorTree &MDT);
103 // initPacketizerState - initialize some internal flags.
104 void initPacketizerState();
106 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
107 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
109 // isSoloInstruction - return true if instruction MI can not be packetized
110 // with any other instruction, which means that MI itself is a packet.
111 bool isSoloInstruction(MachineInstr *MI);
113 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
115 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
117 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
119 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
121 MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
123 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
124 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
125 MachineBasicBlock::iterator &MII,
126 const TargetRegisterClass* RC);
127 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
129 std::map <MachineInstr*, SUnit*> MIToSUnit,
130 MachineBasicBlock::iterator &MII,
131 const TargetRegisterClass* RC);
132 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
134 std::map <MachineInstr*, SUnit*> MIToSUnit,
135 MachineBasicBlock::iterator &MII);
136 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
138 std::map <MachineInstr*, SUnit*> MIToSUnit);
139 bool DemoteToDotOld(MachineInstr* MI);
140 bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
141 std::map <MachineInstr*, SUnit*> MIToSUnit);
142 bool RestrictingDepExistInPacket(MachineInstr*,
143 unsigned, std::map <MachineInstr*, SUnit*>);
144 bool isNewifiable(MachineInstr* MI);
145 bool isCondInst(MachineInstr* MI);
146 bool IsNewifyStore (MachineInstr* MI);
147 bool tryAllocateResourcesForConstExt(MachineInstr* MI);
148 bool canReserveResourcesForConstExt(MachineInstr *MI);
149 void reserveResourcesForConstExt(MachineInstr* MI);
150 bool isNewValueInst(MachineInstr* MI);
151 bool isDotNewInst(MachineInstr* MI);
155 // HexagonPacketizerList Ctor.
156 HexagonPacketizerList::HexagonPacketizerList(
157 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
158 : VLIWPacketizerList(MF, MLI, MDT, true){
161 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
162 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
163 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
164 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
166 // Instantiate the packetizer.
167 HexagonPacketizerList Packetizer(Fn, MLI, MDT);
169 // DFA state table should not be empty.
170 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
173 // Loop over all basic blocks and remove KILL pseudo-instructions
174 // These instructions confuse the dependence analysis. Consider:
176 // R0 = KILL R0, D0 (Insn 1)
178 // Here, Insn 1 will result in the dependence graph not emitting an output
179 // dependence between Insn 0 and Insn 2. This can lead to incorrect
182 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
183 MBB != MBBe; ++MBB) {
184 MachineBasicBlock::iterator End = MBB->end();
185 MachineBasicBlock::iterator MI = MBB->begin();
188 MachineBasicBlock::iterator DeleteMI = MI;
190 MBB->erase(DeleteMI);
198 // Loop over all of the basic blocks.
199 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
200 MBB != MBBe; ++MBB) {
201 // Find scheduling regions and schedule / packetize each region.
202 unsigned RemainingCount = MBB->size();
203 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
204 RegionEnd != MBB->begin();) {
205 // The next region starts above the previous region. Look backward in the
206 // instruction stream until we find the nearest boundary.
207 MachineBasicBlock::iterator I = RegionEnd;
208 for(;I != MBB->begin(); --I, --RemainingCount) {
209 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
214 // Skip empty scheduling regions.
215 if (I == RegionEnd) {
216 RegionEnd = llvm::prior(RegionEnd);
220 // Skip regions with one instruction.
221 if (I == llvm::prior(RegionEnd)) {
222 RegionEnd = llvm::prior(RegionEnd);
226 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
235 static bool IsIndirectCall(MachineInstr* MI) {
236 return ((MI->getOpcode() == Hexagon::CALLR) ||
237 (MI->getOpcode() == Hexagon::CALLRv3));
240 // Reserve resources for constant extender. Trigure an assertion if
242 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
243 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
244 MachineFunction *MF = MI->getParent()->getParent();
245 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
248 if (ResourceTracker->canReserveResources(PseudoMI)) {
249 ResourceTracker->reserveResources(PseudoMI);
250 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
252 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
253 llvm_unreachable("can not reserve resources for constant extender.");
258 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
259 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
260 assert(QII->isExtended(MI) &&
261 "Should only be called for constant extended instructions");
262 MachineFunction *MF = MI->getParent()->getParent();
263 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
265 bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
266 MF->DeleteMachineInstr(PseudoMI);
270 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
271 // true, otherwise, return false.
272 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
273 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
274 MachineFunction *MF = MI->getParent()->getParent();
275 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
278 if (ResourceTracker->canReserveResources(PseudoMI)) {
279 ResourceTracker->reserveResources(PseudoMI);
280 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
283 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
289 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
293 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
294 const HexagonRegisterInfo* QRI =
295 (const HexagonRegisterInfo *) TM.getRegisterInfo();
297 // Check for lr dependence
298 if (DepReg == QRI->getRARegister()) {
302 if (QII->isDeallocRet(MI)) {
303 if (DepReg == QRI->getFrameRegister() ||
304 DepReg == QRI->getStackRegister())
308 // Check if this is a predicate dependence
309 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
310 if (RC == &Hexagon::PredRegsRegClass) {
315 // Lastly check for an operand used in an indirect call
316 // If we had an attribute for checking if an instruction is an indirect call,
317 // then we could have avoided this relatively brittle implementation of
320 // Assumes that the first operand of the CALLr is the function address
322 if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
323 MachineOperand MO = MI->getOperand(0);
324 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
332 static bool IsRegDependence(const SDep::Kind DepType) {
333 return (DepType == SDep::Data || DepType == SDep::Anti ||
334 DepType == SDep::Output);
337 static bool IsDirectJump(MachineInstr* MI) {
338 return (MI->getOpcode() == Hexagon::JMP);
341 static bool IsSchedBarrier(MachineInstr* MI) {
342 switch (MI->getOpcode()) {
343 case Hexagon::BARRIER:
349 static bool IsControlFlow(MachineInstr* MI) {
350 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
353 bool HexagonPacketizerList::isNewValueInst(MachineInstr* MI) {
354 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
355 if (QII->isNewValueJump(MI))
358 if (QII->isNewValueStore(MI))
364 // Function returns true if an instruction can be promoted to the new-value
365 // store. It will always return false for v2 and v3.
366 // It lists all the conditional and unconditional stores that can be promoted
367 // to the new-value stores.
369 bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
370 const HexagonRegisterInfo* QRI =
371 (const HexagonRegisterInfo *) TM.getRegisterInfo();
372 switch (MI->getOpcode())
376 case Hexagon::STrib_indexed:
377 case Hexagon::STrib_indexed_shl_V4:
378 case Hexagon::STrib_shl_V4:
379 case Hexagon::STb_GP_V4:
380 case Hexagon::POST_STbri:
381 case Hexagon::STrib_cPt:
382 case Hexagon::STrib_cdnPt_V4:
383 case Hexagon::STrib_cNotPt:
384 case Hexagon::STrib_cdnNotPt_V4:
385 case Hexagon::STrib_indexed_cPt:
386 case Hexagon::STrib_indexed_cdnPt_V4:
387 case Hexagon::STrib_indexed_cNotPt:
388 case Hexagon::STrib_indexed_cdnNotPt_V4:
389 case Hexagon::STrib_indexed_shl_cPt_V4:
390 case Hexagon::STrib_indexed_shl_cdnPt_V4:
391 case Hexagon::STrib_indexed_shl_cNotPt_V4:
392 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
393 case Hexagon::POST_STbri_cPt:
394 case Hexagon::POST_STbri_cdnPt_V4:
395 case Hexagon::POST_STbri_cNotPt:
396 case Hexagon::POST_STbri_cdnNotPt_V4:
397 case Hexagon::STb_GP_cPt_V4:
398 case Hexagon::STb_GP_cNotPt_V4:
399 case Hexagon::STb_GP_cdnPt_V4:
400 case Hexagon::STb_GP_cdnNotPt_V4:
404 case Hexagon::STrih_indexed:
405 case Hexagon::STrih_indexed_shl_V4:
406 case Hexagon::STrih_shl_V4:
407 case Hexagon::STh_GP_V4:
408 case Hexagon::POST_SThri:
409 case Hexagon::STrih_cPt:
410 case Hexagon::STrih_cdnPt_V4:
411 case Hexagon::STrih_cNotPt:
412 case Hexagon::STrih_cdnNotPt_V4:
413 case Hexagon::STrih_indexed_cPt:
414 case Hexagon::STrih_indexed_cdnPt_V4:
415 case Hexagon::STrih_indexed_cNotPt:
416 case Hexagon::STrih_indexed_cdnNotPt_V4:
417 case Hexagon::STrih_indexed_shl_cPt_V4:
418 case Hexagon::STrih_indexed_shl_cdnPt_V4:
419 case Hexagon::STrih_indexed_shl_cNotPt_V4:
420 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
421 case Hexagon::POST_SThri_cPt:
422 case Hexagon::POST_SThri_cdnPt_V4:
423 case Hexagon::POST_SThri_cNotPt:
424 case Hexagon::POST_SThri_cdnNotPt_V4:
425 case Hexagon::STh_GP_cPt_V4:
426 case Hexagon::STh_GP_cNotPt_V4:
427 case Hexagon::STh_GP_cdnPt_V4:
428 case Hexagon::STh_GP_cdnNotPt_V4:
432 case Hexagon::STriw_indexed:
433 case Hexagon::STriw_indexed_shl_V4:
434 case Hexagon::STriw_shl_V4:
435 case Hexagon::STw_GP_V4:
436 case Hexagon::POST_STwri:
437 case Hexagon::STriw_cPt:
438 case Hexagon::STriw_cdnPt_V4:
439 case Hexagon::STriw_cNotPt:
440 case Hexagon::STriw_cdnNotPt_V4:
441 case Hexagon::STriw_indexed_cPt:
442 case Hexagon::STriw_indexed_cdnPt_V4:
443 case Hexagon::STriw_indexed_cNotPt:
444 case Hexagon::STriw_indexed_cdnNotPt_V4:
445 case Hexagon::STriw_indexed_shl_cPt_V4:
446 case Hexagon::STriw_indexed_shl_cdnPt_V4:
447 case Hexagon::STriw_indexed_shl_cNotPt_V4:
448 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
449 case Hexagon::POST_STwri_cPt:
450 case Hexagon::POST_STwri_cdnPt_V4:
451 case Hexagon::POST_STwri_cNotPt:
452 case Hexagon::POST_STwri_cdnNotPt_V4:
453 case Hexagon::STw_GP_cPt_V4:
454 case Hexagon::STw_GP_cNotPt_V4:
455 case Hexagon::STw_GP_cdnPt_V4:
456 case Hexagon::STw_GP_cdnNotPt_V4:
457 return QRI->Subtarget.hasV4TOps();
462 static bool IsLoopN(MachineInstr *MI) {
463 return (MI->getOpcode() == Hexagon::LOOP0_i ||
464 MI->getOpcode() == Hexagon::LOOP0_r);
467 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
468 /// callee-saved register.
469 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
470 const TargetRegisterInfo *TRI) {
471 for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
472 unsigned CalleeSavedReg = *CSR;
473 if (MI->modifiesRegister(CalleeSavedReg, TRI))
479 // Return the new value instruction for a given store.
480 static int GetDotNewOp(const int opc) {
482 default: llvm_unreachable("Unknown .new type");
483 // store new value byte
485 return Hexagon::STrib_nv_V4;
487 case Hexagon::STrib_indexed:
488 return Hexagon::STrib_indexed_nv_V4;
490 case Hexagon::STrib_indexed_shl_V4:
491 return Hexagon::STrib_indexed_shl_nv_V4;
493 case Hexagon::STrib_shl_V4:
494 return Hexagon::STrib_shl_nv_V4;
496 case Hexagon::STb_GP_V4:
497 return Hexagon::STb_GP_nv_V4;
499 case Hexagon::POST_STbri:
500 return Hexagon::POST_STbri_nv_V4;
502 case Hexagon::STrib_cPt:
503 return Hexagon::STrib_cPt_nv_V4;
505 case Hexagon::STrib_cdnPt_V4:
506 return Hexagon::STrib_cdnPt_nv_V4;
508 case Hexagon::STrib_cNotPt:
509 return Hexagon::STrib_cNotPt_nv_V4;
511 case Hexagon::STrib_cdnNotPt_V4:
512 return Hexagon::STrib_cdnNotPt_nv_V4;
514 case Hexagon::STrib_indexed_cPt:
515 return Hexagon::STrib_indexed_cPt_nv_V4;
517 case Hexagon::STrib_indexed_cdnPt_V4:
518 return Hexagon::STrib_indexed_cdnPt_nv_V4;
520 case Hexagon::STrib_indexed_cNotPt:
521 return Hexagon::STrib_indexed_cNotPt_nv_V4;
523 case Hexagon::STrib_indexed_cdnNotPt_V4:
524 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
526 case Hexagon::STrib_indexed_shl_cPt_V4:
527 return Hexagon::STrib_indexed_shl_cPt_nv_V4;
529 case Hexagon::STrib_indexed_shl_cdnPt_V4:
530 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
532 case Hexagon::STrib_indexed_shl_cNotPt_V4:
533 return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
535 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
536 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
538 case Hexagon::POST_STbri_cPt:
539 return Hexagon::POST_STbri_cPt_nv_V4;
541 case Hexagon::POST_STbri_cdnPt_V4:
542 return Hexagon::POST_STbri_cdnPt_nv_V4;
544 case Hexagon::POST_STbri_cNotPt:
545 return Hexagon::POST_STbri_cNotPt_nv_V4;
547 case Hexagon::POST_STbri_cdnNotPt_V4:
548 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
550 case Hexagon::STb_GP_cPt_V4:
551 return Hexagon::STb_GP_cPt_nv_V4;
553 case Hexagon::STb_GP_cNotPt_V4:
554 return Hexagon::STb_GP_cNotPt_nv_V4;
556 case Hexagon::STb_GP_cdnPt_V4:
557 return Hexagon::STb_GP_cdnPt_nv_V4;
559 case Hexagon::STb_GP_cdnNotPt_V4:
560 return Hexagon::STb_GP_cdnNotPt_nv_V4;
562 // store new value halfword
564 return Hexagon::STrih_nv_V4;
566 case Hexagon::STrih_indexed:
567 return Hexagon::STrih_indexed_nv_V4;
569 case Hexagon::STrih_indexed_shl_V4:
570 return Hexagon::STrih_indexed_shl_nv_V4;
572 case Hexagon::STrih_shl_V4:
573 return Hexagon::STrih_shl_nv_V4;
575 case Hexagon::STh_GP_V4:
576 return Hexagon::STh_GP_nv_V4;
578 case Hexagon::POST_SThri:
579 return Hexagon::POST_SThri_nv_V4;
581 case Hexagon::STrih_cPt:
582 return Hexagon::STrih_cPt_nv_V4;
584 case Hexagon::STrih_cdnPt_V4:
585 return Hexagon::STrih_cdnPt_nv_V4;
587 case Hexagon::STrih_cNotPt:
588 return Hexagon::STrih_cNotPt_nv_V4;
590 case Hexagon::STrih_cdnNotPt_V4:
591 return Hexagon::STrih_cdnNotPt_nv_V4;
593 case Hexagon::STrih_indexed_cPt:
594 return Hexagon::STrih_indexed_cPt_nv_V4;
596 case Hexagon::STrih_indexed_cdnPt_V4:
597 return Hexagon::STrih_indexed_cdnPt_nv_V4;
599 case Hexagon::STrih_indexed_cNotPt:
600 return Hexagon::STrih_indexed_cNotPt_nv_V4;
602 case Hexagon::STrih_indexed_cdnNotPt_V4:
603 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
605 case Hexagon::STrih_indexed_shl_cPt_V4:
606 return Hexagon::STrih_indexed_shl_cPt_nv_V4;
608 case Hexagon::STrih_indexed_shl_cdnPt_V4:
609 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
611 case Hexagon::STrih_indexed_shl_cNotPt_V4:
612 return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
614 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
615 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
617 case Hexagon::POST_SThri_cPt:
618 return Hexagon::POST_SThri_cPt_nv_V4;
620 case Hexagon::POST_SThri_cdnPt_V4:
621 return Hexagon::POST_SThri_cdnPt_nv_V4;
623 case Hexagon::POST_SThri_cNotPt:
624 return Hexagon::POST_SThri_cNotPt_nv_V4;
626 case Hexagon::POST_SThri_cdnNotPt_V4:
627 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
629 case Hexagon::STh_GP_cPt_V4:
630 return Hexagon::STh_GP_cPt_nv_V4;
632 case Hexagon::STh_GP_cNotPt_V4:
633 return Hexagon::STh_GP_cNotPt_nv_V4;
635 case Hexagon::STh_GP_cdnPt_V4:
636 return Hexagon::STh_GP_cdnPt_nv_V4;
638 case Hexagon::STh_GP_cdnNotPt_V4:
639 return Hexagon::STh_GP_cdnNotPt_nv_V4;
641 // store new value word
643 return Hexagon::STriw_nv_V4;
645 case Hexagon::STriw_indexed:
646 return Hexagon::STriw_indexed_nv_V4;
648 case Hexagon::STriw_indexed_shl_V4:
649 return Hexagon::STriw_indexed_shl_nv_V4;
651 case Hexagon::STriw_shl_V4:
652 return Hexagon::STriw_shl_nv_V4;
654 case Hexagon::STw_GP_V4:
655 return Hexagon::STw_GP_nv_V4;
657 case Hexagon::POST_STwri:
658 return Hexagon::POST_STwri_nv_V4;
660 case Hexagon::STriw_cPt:
661 return Hexagon::STriw_cPt_nv_V4;
663 case Hexagon::STriw_cdnPt_V4:
664 return Hexagon::STriw_cdnPt_nv_V4;
666 case Hexagon::STriw_cNotPt:
667 return Hexagon::STriw_cNotPt_nv_V4;
669 case Hexagon::STriw_cdnNotPt_V4:
670 return Hexagon::STriw_cdnNotPt_nv_V4;
672 case Hexagon::STriw_indexed_cPt:
673 return Hexagon::STriw_indexed_cPt_nv_V4;
675 case Hexagon::STriw_indexed_cdnPt_V4:
676 return Hexagon::STriw_indexed_cdnPt_nv_V4;
678 case Hexagon::STriw_indexed_cNotPt:
679 return Hexagon::STriw_indexed_cNotPt_nv_V4;
681 case Hexagon::STriw_indexed_cdnNotPt_V4:
682 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
684 case Hexagon::STriw_indexed_shl_cPt_V4:
685 return Hexagon::STriw_indexed_shl_cPt_nv_V4;
687 case Hexagon::STriw_indexed_shl_cdnPt_V4:
688 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
690 case Hexagon::STriw_indexed_shl_cNotPt_V4:
691 return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
693 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
694 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
696 case Hexagon::POST_STwri_cPt:
697 return Hexagon::POST_STwri_cPt_nv_V4;
699 case Hexagon::POST_STwri_cdnPt_V4:
700 return Hexagon::POST_STwri_cdnPt_nv_V4;
702 case Hexagon::POST_STwri_cNotPt:
703 return Hexagon::POST_STwri_cNotPt_nv_V4;
705 case Hexagon::POST_STwri_cdnNotPt_V4:
706 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
708 case Hexagon::STw_GP_cPt_V4:
709 return Hexagon::STw_GP_cPt_nv_V4;
711 case Hexagon::STw_GP_cNotPt_V4:
712 return Hexagon::STw_GP_cNotPt_nv_V4;
714 case Hexagon::STw_GP_cdnPt_V4:
715 return Hexagon::STw_GP_cdnPt_nv_V4;
717 case Hexagon::STw_GP_cdnNotPt_V4:
718 return Hexagon::STw_GP_cdnNotPt_nv_V4;
723 // Return .new predicate version for an instruction
724 static int GetDotNewPredOp(const int opc) {
726 default: llvm_unreachable("Unknown .new type");
727 // Conditional stores
728 // Store byte conditionally
729 case Hexagon::STrib_cPt :
730 return Hexagon::STrib_cdnPt_V4;
732 case Hexagon::STrib_cNotPt :
733 return Hexagon::STrib_cdnNotPt_V4;
735 case Hexagon::STrib_indexed_cPt :
736 return Hexagon::STrib_indexed_cdnPt_V4;
738 case Hexagon::STrib_indexed_cNotPt :
739 return Hexagon::STrib_indexed_cdnNotPt_V4;
741 case Hexagon::STrib_imm_cPt_V4 :
742 return Hexagon::STrib_imm_cdnPt_V4;
744 case Hexagon::STrib_imm_cNotPt_V4 :
745 return Hexagon::STrib_imm_cdnNotPt_V4;
747 case Hexagon::POST_STbri_cPt :
748 return Hexagon::POST_STbri_cdnPt_V4;
750 case Hexagon::POST_STbri_cNotPt :
751 return Hexagon::POST_STbri_cdnNotPt_V4;
753 case Hexagon::STrib_indexed_shl_cPt_V4 :
754 return Hexagon::STrib_indexed_shl_cdnPt_V4;
756 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
757 return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
759 case Hexagon::STb_GP_cPt_V4 :
760 return Hexagon::STb_GP_cdnPt_V4;
762 case Hexagon::STb_GP_cNotPt_V4 :
763 return Hexagon::STb_GP_cdnNotPt_V4;
765 // Store doubleword conditionally
766 case Hexagon::STrid_cPt :
767 return Hexagon::STrid_cdnPt_V4;
769 case Hexagon::STrid_cNotPt :
770 return Hexagon::STrid_cdnNotPt_V4;
772 case Hexagon::STrid_indexed_cPt :
773 return Hexagon::STrid_indexed_cdnPt_V4;
775 case Hexagon::STrid_indexed_cNotPt :
776 return Hexagon::STrid_indexed_cdnNotPt_V4;
778 case Hexagon::STrid_indexed_shl_cPt_V4 :
779 return Hexagon::STrid_indexed_shl_cdnPt_V4;
781 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
782 return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
784 case Hexagon::POST_STdri_cPt :
785 return Hexagon::POST_STdri_cdnPt_V4;
787 case Hexagon::POST_STdri_cNotPt :
788 return Hexagon::POST_STdri_cdnNotPt_V4;
790 case Hexagon::STd_GP_cPt_V4 :
791 return Hexagon::STd_GP_cdnPt_V4;
793 case Hexagon::STd_GP_cNotPt_V4 :
794 return Hexagon::STd_GP_cdnNotPt_V4;
796 // Store halfword conditionally
797 case Hexagon::STrih_cPt :
798 return Hexagon::STrih_cdnPt_V4;
800 case Hexagon::STrih_cNotPt :
801 return Hexagon::STrih_cdnNotPt_V4;
803 case Hexagon::STrih_indexed_cPt :
804 return Hexagon::STrih_indexed_cdnPt_V4;
806 case Hexagon::STrih_indexed_cNotPt :
807 return Hexagon::STrih_indexed_cdnNotPt_V4;
809 case Hexagon::STrih_imm_cPt_V4 :
810 return Hexagon::STrih_imm_cdnPt_V4;
812 case Hexagon::STrih_imm_cNotPt_V4 :
813 return Hexagon::STrih_imm_cdnNotPt_V4;
815 case Hexagon::STrih_indexed_shl_cPt_V4 :
816 return Hexagon::STrih_indexed_shl_cdnPt_V4;
818 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
819 return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
821 case Hexagon::POST_SThri_cPt :
822 return Hexagon::POST_SThri_cdnPt_V4;
824 case Hexagon::POST_SThri_cNotPt :
825 return Hexagon::POST_SThri_cdnNotPt_V4;
827 case Hexagon::STh_GP_cPt_V4 :
828 return Hexagon::STh_GP_cdnPt_V4;
830 case Hexagon::STh_GP_cNotPt_V4 :
831 return Hexagon::STh_GP_cdnNotPt_V4;
833 // Store word conditionally
834 case Hexagon::STriw_cPt :
835 return Hexagon::STriw_cdnPt_V4;
837 case Hexagon::STriw_cNotPt :
838 return Hexagon::STriw_cdnNotPt_V4;
840 case Hexagon::STriw_indexed_cPt :
841 return Hexagon::STriw_indexed_cdnPt_V4;
843 case Hexagon::STriw_indexed_cNotPt :
844 return Hexagon::STriw_indexed_cdnNotPt_V4;
846 case Hexagon::STriw_imm_cPt_V4 :
847 return Hexagon::STriw_imm_cdnPt_V4;
849 case Hexagon::STriw_imm_cNotPt_V4 :
850 return Hexagon::STriw_imm_cdnNotPt_V4;
852 case Hexagon::STriw_indexed_shl_cPt_V4 :
853 return Hexagon::STriw_indexed_shl_cdnPt_V4;
855 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
856 return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
858 case Hexagon::POST_STwri_cPt :
859 return Hexagon::POST_STwri_cdnPt_V4;
861 case Hexagon::POST_STwri_cNotPt :
862 return Hexagon::POST_STwri_cdnNotPt_V4;
864 case Hexagon::STw_GP_cPt_V4 :
865 return Hexagon::STw_GP_cdnPt_V4;
867 case Hexagon::STw_GP_cNotPt_V4 :
868 return Hexagon::STw_GP_cdnNotPt_V4;
872 return Hexagon::JMP_cdnPt;
874 case Hexagon::JMP_cNot:
875 return Hexagon::JMP_cdnNotPt;
877 case Hexagon::JMPR_cPt:
878 return Hexagon::JMPR_cdnPt_V3;
880 case Hexagon::JMPR_cNotPt:
881 return Hexagon::JMPR_cdnNotPt_V3;
883 // Conditional Transfers
884 case Hexagon::TFR_cPt:
885 return Hexagon::TFR_cdnPt;
887 case Hexagon::TFR_cNotPt:
888 return Hexagon::TFR_cdnNotPt;
890 case Hexagon::TFRI_cPt:
891 return Hexagon::TFRI_cdnPt;
893 case Hexagon::TFRI_cNotPt:
894 return Hexagon::TFRI_cdnNotPt;
897 case Hexagon::LDrid_cPt :
898 return Hexagon::LDrid_cdnPt;
900 case Hexagon::LDrid_cNotPt :
901 return Hexagon::LDrid_cdnNotPt;
903 case Hexagon::LDrid_indexed_cPt :
904 return Hexagon::LDrid_indexed_cdnPt;
906 case Hexagon::LDrid_indexed_cNotPt :
907 return Hexagon::LDrid_indexed_cdnNotPt;
909 case Hexagon::POST_LDrid_cPt :
910 return Hexagon::POST_LDrid_cdnPt_V4;
912 case Hexagon::POST_LDrid_cNotPt :
913 return Hexagon::POST_LDrid_cdnNotPt_V4;
916 case Hexagon::LDriw_cPt :
917 return Hexagon::LDriw_cdnPt;
919 case Hexagon::LDriw_cNotPt :
920 return Hexagon::LDriw_cdnNotPt;
922 case Hexagon::LDriw_indexed_cPt :
923 return Hexagon::LDriw_indexed_cdnPt;
925 case Hexagon::LDriw_indexed_cNotPt :
926 return Hexagon::LDriw_indexed_cdnNotPt;
928 case Hexagon::POST_LDriw_cPt :
929 return Hexagon::POST_LDriw_cdnPt_V4;
931 case Hexagon::POST_LDriw_cNotPt :
932 return Hexagon::POST_LDriw_cdnNotPt_V4;
935 case Hexagon::LDrih_cPt :
936 return Hexagon::LDrih_cdnPt;
938 case Hexagon::LDrih_cNotPt :
939 return Hexagon::LDrih_cdnNotPt;
941 case Hexagon::LDrih_indexed_cPt :
942 return Hexagon::LDrih_indexed_cdnPt;
944 case Hexagon::LDrih_indexed_cNotPt :
945 return Hexagon::LDrih_indexed_cdnNotPt;
947 case Hexagon::POST_LDrih_cPt :
948 return Hexagon::POST_LDrih_cdnPt_V4;
950 case Hexagon::POST_LDrih_cNotPt :
951 return Hexagon::POST_LDrih_cdnNotPt_V4;
954 case Hexagon::LDrib_cPt :
955 return Hexagon::LDrib_cdnPt;
957 case Hexagon::LDrib_cNotPt :
958 return Hexagon::LDrib_cdnNotPt;
960 case Hexagon::LDrib_indexed_cPt :
961 return Hexagon::LDrib_indexed_cdnPt;
963 case Hexagon::LDrib_indexed_cNotPt :
964 return Hexagon::LDrib_indexed_cdnNotPt;
966 case Hexagon::POST_LDrib_cPt :
967 return Hexagon::POST_LDrib_cdnPt_V4;
969 case Hexagon::POST_LDrib_cNotPt :
970 return Hexagon::POST_LDrib_cdnNotPt_V4;
972 // Load unsigned halfword
973 case Hexagon::LDriuh_cPt :
974 return Hexagon::LDriuh_cdnPt;
976 case Hexagon::LDriuh_cNotPt :
977 return Hexagon::LDriuh_cdnNotPt;
979 case Hexagon::LDriuh_indexed_cPt :
980 return Hexagon::LDriuh_indexed_cdnPt;
982 case Hexagon::LDriuh_indexed_cNotPt :
983 return Hexagon::LDriuh_indexed_cdnNotPt;
985 case Hexagon::POST_LDriuh_cPt :
986 return Hexagon::POST_LDriuh_cdnPt_V4;
988 case Hexagon::POST_LDriuh_cNotPt :
989 return Hexagon::POST_LDriuh_cdnNotPt_V4;
991 // Load unsigned byte
992 case Hexagon::LDriub_cPt :
993 return Hexagon::LDriub_cdnPt;
995 case Hexagon::LDriub_cNotPt :
996 return Hexagon::LDriub_cdnNotPt;
998 case Hexagon::LDriub_indexed_cPt :
999 return Hexagon::LDriub_indexed_cdnPt;
1001 case Hexagon::LDriub_indexed_cNotPt :
1002 return Hexagon::LDriub_indexed_cdnNotPt;
1004 case Hexagon::POST_LDriub_cPt :
1005 return Hexagon::POST_LDriub_cdnPt_V4;
1007 case Hexagon::POST_LDriub_cNotPt :
1008 return Hexagon::POST_LDriub_cdnNotPt_V4;
1010 // V4 indexed+scaled load
1012 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1013 return Hexagon::LDrid_indexed_shl_cdnPt_V4;
1015 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1016 return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
1018 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1019 return Hexagon::LDrib_indexed_shl_cdnPt_V4;
1021 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1022 return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
1024 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1025 return Hexagon::LDriub_indexed_shl_cdnPt_V4;
1027 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1028 return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
1030 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1031 return Hexagon::LDrih_indexed_shl_cdnPt_V4;
1033 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1034 return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
1036 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1037 return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
1039 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1040 return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
1042 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1043 return Hexagon::LDriw_indexed_shl_cdnPt_V4;
1045 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1046 return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
1048 // V4 global address load
1050 case Hexagon::LDd_GP_cPt_V4:
1051 return Hexagon::LDd_GP_cdnPt_V4;
1053 case Hexagon::LDd_GP_cNotPt_V4:
1054 return Hexagon::LDd_GP_cdnNotPt_V4;
1056 case Hexagon::LDb_GP_cPt_V4:
1057 return Hexagon::LDb_GP_cdnPt_V4;
1059 case Hexagon::LDb_GP_cNotPt_V4:
1060 return Hexagon::LDb_GP_cdnNotPt_V4;
1062 case Hexagon::LDub_GP_cPt_V4:
1063 return Hexagon::LDub_GP_cdnPt_V4;
1065 case Hexagon::LDub_GP_cNotPt_V4:
1066 return Hexagon::LDub_GP_cdnNotPt_V4;
1068 case Hexagon::LDh_GP_cPt_V4:
1069 return Hexagon::LDh_GP_cdnPt_V4;
1071 case Hexagon::LDh_GP_cNotPt_V4:
1072 return Hexagon::LDh_GP_cdnNotPt_V4;
1074 case Hexagon::LDuh_GP_cPt_V4:
1075 return Hexagon::LDuh_GP_cdnPt_V4;
1077 case Hexagon::LDuh_GP_cNotPt_V4:
1078 return Hexagon::LDuh_GP_cdnNotPt_V4;
1080 case Hexagon::LDw_GP_cPt_V4:
1081 return Hexagon::LDw_GP_cdnPt_V4;
1083 case Hexagon::LDw_GP_cNotPt_V4:
1084 return Hexagon::LDw_GP_cdnNotPt_V4;
1086 // Conditional store new-value byte
1087 case Hexagon::STrib_cPt_nv_V4 :
1088 return Hexagon::STrib_cdnPt_nv_V4;
1089 case Hexagon::STrib_cNotPt_nv_V4 :
1090 return Hexagon::STrib_cdnNotPt_nv_V4;
1092 case Hexagon::STrib_indexed_cPt_nv_V4 :
1093 return Hexagon::STrib_indexed_cdnPt_nv_V4;
1094 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1095 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
1097 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1098 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
1099 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1100 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
1102 case Hexagon::POST_STbri_cPt_nv_V4 :
1103 return Hexagon::POST_STbri_cdnPt_nv_V4;
1104 case Hexagon::POST_STbri_cNotPt_nv_V4 :
1105 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
1107 case Hexagon::STb_GP_cPt_nv_V4 :
1108 return Hexagon::STb_GP_cdnPt_nv_V4;
1110 case Hexagon::STb_GP_cNotPt_nv_V4 :
1111 return Hexagon::STb_GP_cdnNotPt_nv_V4;
1113 // Conditional store new-value halfword
1114 case Hexagon::STrih_cPt_nv_V4 :
1115 return Hexagon::STrih_cdnPt_nv_V4;
1116 case Hexagon::STrih_cNotPt_nv_V4 :
1117 return Hexagon::STrih_cdnNotPt_nv_V4;
1119 case Hexagon::STrih_indexed_cPt_nv_V4 :
1120 return Hexagon::STrih_indexed_cdnPt_nv_V4;
1121 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1122 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
1124 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1125 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
1126 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1127 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
1129 case Hexagon::POST_SThri_cPt_nv_V4 :
1130 return Hexagon::POST_SThri_cdnPt_nv_V4;
1131 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1132 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
1134 case Hexagon::STh_GP_cPt_nv_V4 :
1135 return Hexagon::STh_GP_cdnPt_nv_V4;
1137 case Hexagon::STh_GP_cNotPt_nv_V4 :
1138 return Hexagon::STh_GP_cdnNotPt_nv_V4;
1140 // Conditional store new-value word
1141 case Hexagon::STriw_cPt_nv_V4 :
1142 return Hexagon::STriw_cdnPt_nv_V4;
1143 case Hexagon::STriw_cNotPt_nv_V4 :
1144 return Hexagon::STriw_cdnNotPt_nv_V4;
1146 case Hexagon::STriw_indexed_cPt_nv_V4 :
1147 return Hexagon::STriw_indexed_cdnPt_nv_V4;
1148 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1149 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
1151 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1152 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
1153 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1154 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
1156 case Hexagon::POST_STwri_cPt_nv_V4 :
1157 return Hexagon::POST_STwri_cdnPt_nv_V4;
1158 case Hexagon::POST_STwri_cNotPt_nv_V4:
1159 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
1161 case Hexagon::STw_GP_cPt_nv_V4 :
1162 return Hexagon::STw_GP_cdnPt_nv_V4;
1164 case Hexagon::STw_GP_cNotPt_nv_V4 :
1165 return Hexagon::STw_GP_cdnNotPt_nv_V4;
1168 case Hexagon::ADD_ri_cPt :
1169 return Hexagon::ADD_ri_cdnPt;
1170 case Hexagon::ADD_ri_cNotPt :
1171 return Hexagon::ADD_ri_cdnNotPt;
1173 case Hexagon::ADD_rr_cPt :
1174 return Hexagon::ADD_rr_cdnPt;
1175 case Hexagon::ADD_rr_cNotPt :
1176 return Hexagon::ADD_rr_cdnNotPt;
1178 // Conditional logical Operations
1179 case Hexagon::XOR_rr_cPt :
1180 return Hexagon::XOR_rr_cdnPt;
1181 case Hexagon::XOR_rr_cNotPt :
1182 return Hexagon::XOR_rr_cdnNotPt;
1184 case Hexagon::AND_rr_cPt :
1185 return Hexagon::AND_rr_cdnPt;
1186 case Hexagon::AND_rr_cNotPt :
1187 return Hexagon::AND_rr_cdnNotPt;
1189 case Hexagon::OR_rr_cPt :
1190 return Hexagon::OR_rr_cdnPt;
1191 case Hexagon::OR_rr_cNotPt :
1192 return Hexagon::OR_rr_cdnNotPt;
1194 // Conditional Subtract
1195 case Hexagon::SUB_rr_cPt :
1196 return Hexagon::SUB_rr_cdnPt;
1197 case Hexagon::SUB_rr_cNotPt :
1198 return Hexagon::SUB_rr_cdnNotPt;
1200 // Conditional combine
1201 case Hexagon::COMBINE_rr_cPt :
1202 return Hexagon::COMBINE_rr_cdnPt;
1203 case Hexagon::COMBINE_rr_cNotPt :
1204 return Hexagon::COMBINE_rr_cdnNotPt;
1206 case Hexagon::ASLH_cPt_V4 :
1207 return Hexagon::ASLH_cdnPt_V4;
1208 case Hexagon::ASLH_cNotPt_V4 :
1209 return Hexagon::ASLH_cdnNotPt_V4;
1211 case Hexagon::ASRH_cPt_V4 :
1212 return Hexagon::ASRH_cdnPt_V4;
1213 case Hexagon::ASRH_cNotPt_V4 :
1214 return Hexagon::ASRH_cdnNotPt_V4;
1216 case Hexagon::SXTB_cPt_V4 :
1217 return Hexagon::SXTB_cdnPt_V4;
1218 case Hexagon::SXTB_cNotPt_V4 :
1219 return Hexagon::SXTB_cdnNotPt_V4;
1221 case Hexagon::SXTH_cPt_V4 :
1222 return Hexagon::SXTH_cdnPt_V4;
1223 case Hexagon::SXTH_cNotPt_V4 :
1224 return Hexagon::SXTH_cdnNotPt_V4;
1226 case Hexagon::ZXTB_cPt_V4 :
1227 return Hexagon::ZXTB_cdnPt_V4;
1228 case Hexagon::ZXTB_cNotPt_V4 :
1229 return Hexagon::ZXTB_cdnNotPt_V4;
1231 case Hexagon::ZXTH_cPt_V4 :
1232 return Hexagon::ZXTH_cdnPt_V4;
1233 case Hexagon::ZXTH_cNotPt_V4 :
1234 return Hexagon::ZXTH_cdnNotPt_V4;
1238 // Returns true if an instruction can be promoted to .new predicate
1239 // or new-value store.
1240 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
1241 if ( isCondInst(MI) || IsNewifyStore(MI))
1247 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
1248 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1249 const MCInstrDesc& TID = MI->getDesc();
1250 // bug 5670: until that is fixed,
1251 // this portion is disabled.
1252 if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
1253 || QII->isConditionalTransfer(MI)
1254 || QII->isConditionalALU32(MI)
1255 || QII->isConditionalLoad(MI)
1256 || QII->isConditionalStore(MI)) {
1263 // Promote an instructiont to its .new form.
1264 // At this time, we have already made a call to CanPromoteToDotNew
1265 // and made sure that it can *indeed* be promoted.
1266 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
1267 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
1268 const TargetRegisterClass* RC) {
1270 assert (DepType == SDep::Data);
1271 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1274 if (RC == &Hexagon::PredRegsRegClass)
1275 NewOpcode = GetDotNewPredOp(MI->getOpcode());
1277 NewOpcode = GetDotNewOp(MI->getOpcode());
1278 MI->setDesc(QII->get(NewOpcode));
1283 // Returns the most basic instruction for the .new predicated instructions and
1284 // new-value stores.
1285 // For example, all of the following instructions will be converted back to the
1286 // same instruction:
1287 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1288 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1289 // 3) if (p0.new) memw(R0+#0) = R1 --->
1291 // To understand the translation of instruction 1 to its original form, consider
1292 // a packet with 3 instructions.
1293 // { p0 = cmp.eq(R0,R1)
1294 // if (p0.new) R2 = add(R3, R4)
1295 // R5 = add (R3, R1)
1297 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
1299 // This instruction can be part of the previous packet only if both p0 and R2
1300 // are promoted to .new values. This promotion happens in steps, first
1301 // predicate register is promoted to .new and in the next iteration R2 is
1302 // promoted. Therefore, in case of dependence check failure (due to R5) during
1303 // next iteration, it should be converted back to its most basic form.
1305 static int GetDotOldOp(const int opc) {
1307 default: llvm_unreachable("Unknown .old type");
1308 case Hexagon::TFR_cdnPt:
1309 return Hexagon::TFR_cPt;
1311 case Hexagon::TFR_cdnNotPt:
1312 return Hexagon::TFR_cNotPt;
1314 case Hexagon::TFRI_cdnPt:
1315 return Hexagon::TFRI_cPt;
1317 case Hexagon::TFRI_cdnNotPt:
1318 return Hexagon::TFRI_cNotPt;
1320 case Hexagon::JMP_cdnPt:
1321 return Hexagon::JMP_c;
1323 case Hexagon::JMP_cdnNotPt:
1324 return Hexagon::JMP_cNot;
1326 case Hexagon::JMPR_cdnPt_V3:
1327 return Hexagon::JMPR_cPt;
1329 case Hexagon::JMPR_cdnNotPt_V3:
1330 return Hexagon::JMPR_cNotPt;
1334 case Hexagon::LDrid_cdnPt :
1335 return Hexagon::LDrid_cPt;
1337 case Hexagon::LDrid_cdnNotPt :
1338 return Hexagon::LDrid_cNotPt;
1340 case Hexagon::LDrid_indexed_cdnPt :
1341 return Hexagon::LDrid_indexed_cPt;
1343 case Hexagon::LDrid_indexed_cdnNotPt :
1344 return Hexagon::LDrid_indexed_cNotPt;
1346 case Hexagon::POST_LDrid_cdnPt_V4 :
1347 return Hexagon::POST_LDrid_cPt;
1349 case Hexagon::POST_LDrid_cdnNotPt_V4 :
1350 return Hexagon::POST_LDrid_cNotPt;
1354 case Hexagon::LDriw_cdnPt :
1355 return Hexagon::LDriw_cPt;
1357 case Hexagon::LDriw_cdnNotPt :
1358 return Hexagon::LDriw_cNotPt;
1360 case Hexagon::LDriw_indexed_cdnPt :
1361 return Hexagon::LDriw_indexed_cPt;
1363 case Hexagon::LDriw_indexed_cdnNotPt :
1364 return Hexagon::LDriw_indexed_cNotPt;
1366 case Hexagon::POST_LDriw_cdnPt_V4 :
1367 return Hexagon::POST_LDriw_cPt;
1369 case Hexagon::POST_LDriw_cdnNotPt_V4 :
1370 return Hexagon::POST_LDriw_cNotPt;
1374 case Hexagon::LDrih_cdnPt :
1375 return Hexagon::LDrih_cPt;
1377 case Hexagon::LDrih_cdnNotPt :
1378 return Hexagon::LDrih_cNotPt;
1380 case Hexagon::LDrih_indexed_cdnPt :
1381 return Hexagon::LDrih_indexed_cPt;
1383 case Hexagon::LDrih_indexed_cdnNotPt :
1384 return Hexagon::LDrih_indexed_cNotPt;
1386 case Hexagon::POST_LDrih_cdnPt_V4 :
1387 return Hexagon::POST_LDrih_cPt;
1389 case Hexagon::POST_LDrih_cdnNotPt_V4 :
1390 return Hexagon::POST_LDrih_cNotPt;
1394 case Hexagon::LDrib_cdnPt :
1395 return Hexagon::LDrib_cPt;
1397 case Hexagon::LDrib_cdnNotPt :
1398 return Hexagon::LDrib_cNotPt;
1400 case Hexagon::LDrib_indexed_cdnPt :
1401 return Hexagon::LDrib_indexed_cPt;
1403 case Hexagon::LDrib_indexed_cdnNotPt :
1404 return Hexagon::LDrib_indexed_cNotPt;
1406 case Hexagon::POST_LDrib_cdnPt_V4 :
1407 return Hexagon::POST_LDrib_cPt;
1409 case Hexagon::POST_LDrib_cdnNotPt_V4 :
1410 return Hexagon::POST_LDrib_cNotPt;
1412 // Load unsigned half
1414 case Hexagon::LDriuh_cdnPt :
1415 return Hexagon::LDriuh_cPt;
1417 case Hexagon::LDriuh_cdnNotPt :
1418 return Hexagon::LDriuh_cNotPt;
1420 case Hexagon::LDriuh_indexed_cdnPt :
1421 return Hexagon::LDriuh_indexed_cPt;
1423 case Hexagon::LDriuh_indexed_cdnNotPt :
1424 return Hexagon::LDriuh_indexed_cNotPt;
1426 case Hexagon::POST_LDriuh_cdnPt_V4 :
1427 return Hexagon::POST_LDriuh_cPt;
1429 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
1430 return Hexagon::POST_LDriuh_cNotPt;
1432 // Load unsigned byte
1433 case Hexagon::LDriub_cdnPt :
1434 return Hexagon::LDriub_cPt;
1436 case Hexagon::LDriub_cdnNotPt :
1437 return Hexagon::LDriub_cNotPt;
1439 case Hexagon::LDriub_indexed_cdnPt :
1440 return Hexagon::LDriub_indexed_cPt;
1442 case Hexagon::LDriub_indexed_cdnNotPt :
1443 return Hexagon::LDriub_indexed_cNotPt;
1445 case Hexagon::POST_LDriub_cdnPt_V4 :
1446 return Hexagon::POST_LDriub_cPt;
1448 case Hexagon::POST_LDriub_cdnNotPt_V4 :
1449 return Hexagon::POST_LDriub_cNotPt;
1451 // V4 indexed+scaled Load
1453 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1454 return Hexagon::LDrid_indexed_shl_cPt_V4;
1456 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
1457 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1459 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1460 return Hexagon::LDrib_indexed_shl_cPt_V4;
1462 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
1463 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1465 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1466 return Hexagon::LDriub_indexed_shl_cPt_V4;
1468 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
1469 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1471 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1472 return Hexagon::LDrih_indexed_shl_cPt_V4;
1474 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
1475 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1477 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1478 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1480 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
1481 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1483 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1484 return Hexagon::LDriw_indexed_shl_cPt_V4;
1486 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
1487 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1489 // V4 global address load
1491 case Hexagon::LDd_GP_cdnPt_V4:
1492 return Hexagon::LDd_GP_cPt_V4;
1494 case Hexagon::LDd_GP_cdnNotPt_V4:
1495 return Hexagon::LDd_GP_cNotPt_V4;
1497 case Hexagon::LDb_GP_cdnPt_V4:
1498 return Hexagon::LDb_GP_cPt_V4;
1500 case Hexagon::LDb_GP_cdnNotPt_V4:
1501 return Hexagon::LDb_GP_cNotPt_V4;
1503 case Hexagon::LDub_GP_cdnPt_V4:
1504 return Hexagon::LDub_GP_cPt_V4;
1506 case Hexagon::LDub_GP_cdnNotPt_V4:
1507 return Hexagon::LDub_GP_cNotPt_V4;
1509 case Hexagon::LDh_GP_cdnPt_V4:
1510 return Hexagon::LDh_GP_cPt_V4;
1512 case Hexagon::LDh_GP_cdnNotPt_V4:
1513 return Hexagon::LDh_GP_cNotPt_V4;
1515 case Hexagon::LDuh_GP_cdnPt_V4:
1516 return Hexagon::LDuh_GP_cPt_V4;
1518 case Hexagon::LDuh_GP_cdnNotPt_V4:
1519 return Hexagon::LDuh_GP_cNotPt_V4;
1521 case Hexagon::LDw_GP_cdnPt_V4:
1522 return Hexagon::LDw_GP_cPt_V4;
1524 case Hexagon::LDw_GP_cdnNotPt_V4:
1525 return Hexagon::LDw_GP_cNotPt_V4;
1529 case Hexagon::ADD_ri_cdnPt :
1530 return Hexagon::ADD_ri_cPt;
1531 case Hexagon::ADD_ri_cdnNotPt :
1532 return Hexagon::ADD_ri_cNotPt;
1534 case Hexagon::ADD_rr_cdnPt :
1535 return Hexagon::ADD_rr_cPt;
1536 case Hexagon::ADD_rr_cdnNotPt:
1537 return Hexagon::ADD_rr_cNotPt;
1539 // Conditional logical Operations
1541 case Hexagon::XOR_rr_cdnPt :
1542 return Hexagon::XOR_rr_cPt;
1543 case Hexagon::XOR_rr_cdnNotPt :
1544 return Hexagon::XOR_rr_cNotPt;
1546 case Hexagon::AND_rr_cdnPt :
1547 return Hexagon::AND_rr_cPt;
1548 case Hexagon::AND_rr_cdnNotPt :
1549 return Hexagon::AND_rr_cNotPt;
1551 case Hexagon::OR_rr_cdnPt :
1552 return Hexagon::OR_rr_cPt;
1553 case Hexagon::OR_rr_cdnNotPt :
1554 return Hexagon::OR_rr_cNotPt;
1556 // Conditional Subtract
1558 case Hexagon::SUB_rr_cdnPt :
1559 return Hexagon::SUB_rr_cPt;
1560 case Hexagon::SUB_rr_cdnNotPt :
1561 return Hexagon::SUB_rr_cNotPt;
1563 // Conditional combine
1565 case Hexagon::COMBINE_rr_cdnPt :
1566 return Hexagon::COMBINE_rr_cPt;
1567 case Hexagon::COMBINE_rr_cdnNotPt :
1568 return Hexagon::COMBINE_rr_cNotPt;
1570 // Conditional shift operations
1572 case Hexagon::ASLH_cdnPt_V4 :
1573 return Hexagon::ASLH_cPt_V4;
1574 case Hexagon::ASLH_cdnNotPt_V4 :
1575 return Hexagon::ASLH_cNotPt_V4;
1577 case Hexagon::ASRH_cdnPt_V4 :
1578 return Hexagon::ASRH_cPt_V4;
1579 case Hexagon::ASRH_cdnNotPt_V4 :
1580 return Hexagon::ASRH_cNotPt_V4;
1582 case Hexagon::SXTB_cdnPt_V4 :
1583 return Hexagon::SXTB_cPt_V4;
1584 case Hexagon::SXTB_cdnNotPt_V4 :
1585 return Hexagon::SXTB_cNotPt_V4;
1587 case Hexagon::SXTH_cdnPt_V4 :
1588 return Hexagon::SXTH_cPt_V4;
1589 case Hexagon::SXTH_cdnNotPt_V4 :
1590 return Hexagon::SXTH_cNotPt_V4;
1592 case Hexagon::ZXTB_cdnPt_V4 :
1593 return Hexagon::ZXTB_cPt_V4;
1594 case Hexagon::ZXTB_cdnNotPt_V4 :
1595 return Hexagon::ZXTB_cNotPt_V4;
1597 case Hexagon::ZXTH_cdnPt_V4 :
1598 return Hexagon::ZXTH_cPt_V4;
1599 case Hexagon::ZXTH_cdnNotPt_V4 :
1600 return Hexagon::ZXTH_cNotPt_V4;
1604 case Hexagon::STrib_imm_cdnPt_V4 :
1605 return Hexagon::STrib_imm_cPt_V4;
1607 case Hexagon::STrib_imm_cdnNotPt_V4 :
1608 return Hexagon::STrib_imm_cNotPt_V4;
1610 case Hexagon::STrib_cdnPt_nv_V4 :
1611 case Hexagon::STrib_cPt_nv_V4 :
1612 case Hexagon::STrib_cdnPt_V4 :
1613 return Hexagon::STrib_cPt;
1615 case Hexagon::STrib_cdnNotPt_nv_V4 :
1616 case Hexagon::STrib_cNotPt_nv_V4 :
1617 case Hexagon::STrib_cdnNotPt_V4 :
1618 return Hexagon::STrib_cNotPt;
1620 case Hexagon::STrib_indexed_cdnPt_V4 :
1621 case Hexagon::STrib_indexed_cPt_nv_V4 :
1622 case Hexagon::STrib_indexed_cdnPt_nv_V4 :
1623 return Hexagon::STrib_indexed_cPt;
1625 case Hexagon::STrib_indexed_cdnNotPt_V4 :
1626 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1627 case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
1628 return Hexagon::STrib_indexed_cNotPt;
1630 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1631 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1632 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1633 return Hexagon::STrib_indexed_shl_cPt_V4;
1635 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1636 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1637 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
1638 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1640 case Hexagon::POST_STbri_cdnPt_nv_V4 :
1641 case Hexagon::POST_STbri_cPt_nv_V4 :
1642 case Hexagon::POST_STbri_cdnPt_V4 :
1643 return Hexagon::POST_STbri_cPt;
1645 case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
1646 case Hexagon::POST_STbri_cNotPt_nv_V4:
1647 case Hexagon::POST_STbri_cdnNotPt_V4 :
1648 return Hexagon::POST_STbri_cNotPt;
1650 case Hexagon::STb_GP_cdnPt_nv_V4:
1651 case Hexagon::STb_GP_cdnPt_V4:
1652 case Hexagon::STb_GP_cPt_nv_V4:
1653 return Hexagon::STb_GP_cPt_V4;
1655 case Hexagon::STb_GP_cdnNotPt_nv_V4:
1656 case Hexagon::STb_GP_cdnNotPt_V4:
1657 case Hexagon::STb_GP_cNotPt_nv_V4:
1658 return Hexagon::STb_GP_cNotPt_V4;
1660 // Store new-value byte - unconditional
1661 case Hexagon::STrib_nv_V4:
1662 return Hexagon::STrib;
1664 case Hexagon::STrib_indexed_nv_V4:
1665 return Hexagon::STrib_indexed;
1667 case Hexagon::STrib_indexed_shl_nv_V4:
1668 return Hexagon::STrib_indexed_shl_V4;
1670 case Hexagon::STrib_shl_nv_V4:
1671 return Hexagon::STrib_shl_V4;
1673 case Hexagon::STb_GP_nv_V4:
1674 return Hexagon::STb_GP_V4;
1676 case Hexagon::POST_STbri_nv_V4:
1677 return Hexagon::POST_STbri;
1680 case Hexagon::STrih_imm_cdnPt_V4 :
1681 return Hexagon::STrih_imm_cPt_V4;
1683 case Hexagon::STrih_imm_cdnNotPt_V4 :
1684 return Hexagon::STrih_imm_cNotPt_V4;
1686 case Hexagon::STrih_cdnPt_nv_V4 :
1687 case Hexagon::STrih_cPt_nv_V4 :
1688 case Hexagon::STrih_cdnPt_V4 :
1689 return Hexagon::STrih_cPt;
1691 case Hexagon::STrih_cdnNotPt_nv_V4 :
1692 case Hexagon::STrih_cNotPt_nv_V4 :
1693 case Hexagon::STrih_cdnNotPt_V4 :
1694 return Hexagon::STrih_cNotPt;
1696 case Hexagon::STrih_indexed_cdnPt_nv_V4:
1697 case Hexagon::STrih_indexed_cPt_nv_V4 :
1698 case Hexagon::STrih_indexed_cdnPt_V4 :
1699 return Hexagon::STrih_indexed_cPt;
1701 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1702 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1703 case Hexagon::STrih_indexed_cdnNotPt_V4 :
1704 return Hexagon::STrih_indexed_cNotPt;
1706 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
1707 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1708 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1709 return Hexagon::STrih_indexed_shl_cPt_V4;
1711 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
1712 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1713 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
1714 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1716 case Hexagon::POST_SThri_cdnPt_nv_V4 :
1717 case Hexagon::POST_SThri_cPt_nv_V4 :
1718 case Hexagon::POST_SThri_cdnPt_V4 :
1719 return Hexagon::POST_SThri_cPt;
1721 case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
1722 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1723 case Hexagon::POST_SThri_cdnNotPt_V4 :
1724 return Hexagon::POST_SThri_cNotPt;
1726 case Hexagon::STh_GP_cdnPt_nv_V4:
1727 case Hexagon::STh_GP_cdnPt_V4:
1728 case Hexagon::STh_GP_cPt_nv_V4:
1729 return Hexagon::STh_GP_cPt_V4;
1731 case Hexagon::STh_GP_cdnNotPt_nv_V4:
1732 case Hexagon::STh_GP_cdnNotPt_V4:
1733 case Hexagon::STh_GP_cNotPt_nv_V4:
1734 return Hexagon::STh_GP_cNotPt_V4;
1736 // Store new-value halfword - unconditional
1738 case Hexagon::STrih_nv_V4:
1739 return Hexagon::STrih;
1741 case Hexagon::STrih_indexed_nv_V4:
1742 return Hexagon::STrih_indexed;
1744 case Hexagon::STrih_indexed_shl_nv_V4:
1745 return Hexagon::STrih_indexed_shl_V4;
1747 case Hexagon::STrih_shl_nv_V4:
1748 return Hexagon::STrih_shl_V4;
1750 case Hexagon::STh_GP_nv_V4:
1751 return Hexagon::STh_GP_V4;
1753 case Hexagon::POST_SThri_nv_V4:
1754 return Hexagon::POST_SThri;
1758 case Hexagon::STriw_imm_cdnPt_V4 :
1759 return Hexagon::STriw_imm_cPt_V4;
1761 case Hexagon::STriw_imm_cdnNotPt_V4 :
1762 return Hexagon::STriw_imm_cNotPt_V4;
1764 case Hexagon::STriw_cdnPt_nv_V4 :
1765 case Hexagon::STriw_cPt_nv_V4 :
1766 case Hexagon::STriw_cdnPt_V4 :
1767 return Hexagon::STriw_cPt;
1769 case Hexagon::STriw_cdnNotPt_nv_V4 :
1770 case Hexagon::STriw_cNotPt_nv_V4 :
1771 case Hexagon::STriw_cdnNotPt_V4 :
1772 return Hexagon::STriw_cNotPt;
1774 case Hexagon::STriw_indexed_cdnPt_nv_V4 :
1775 case Hexagon::STriw_indexed_cPt_nv_V4 :
1776 case Hexagon::STriw_indexed_cdnPt_V4 :
1777 return Hexagon::STriw_indexed_cPt;
1779 case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
1780 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1781 case Hexagon::STriw_indexed_cdnNotPt_V4 :
1782 return Hexagon::STriw_indexed_cNotPt;
1784 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
1785 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1786 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1787 return Hexagon::STriw_indexed_shl_cPt_V4;
1789 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
1790 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1791 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
1792 return Hexagon::STriw_indexed_shl_cNotPt_V4;
1794 case Hexagon::POST_STwri_cdnPt_nv_V4 :
1795 case Hexagon::POST_STwri_cPt_nv_V4 :
1796 case Hexagon::POST_STwri_cdnPt_V4 :
1797 return Hexagon::POST_STwri_cPt;
1799 case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
1800 case Hexagon::POST_STwri_cNotPt_nv_V4 :
1801 case Hexagon::POST_STwri_cdnNotPt_V4 :
1802 return Hexagon::POST_STwri_cNotPt;
1804 case Hexagon::STw_GP_cdnPt_nv_V4:
1805 case Hexagon::STw_GP_cdnPt_V4:
1806 case Hexagon::STw_GP_cPt_nv_V4:
1807 return Hexagon::STw_GP_cPt_V4;
1809 case Hexagon::STw_GP_cdnNotPt_nv_V4:
1810 case Hexagon::STw_GP_cdnNotPt_V4:
1811 case Hexagon::STw_GP_cNotPt_nv_V4:
1812 return Hexagon::STw_GP_cNotPt_V4;
1814 // Store new-value word - unconditional
1816 case Hexagon::STriw_nv_V4:
1817 return Hexagon::STriw;
1819 case Hexagon::STriw_indexed_nv_V4:
1820 return Hexagon::STriw_indexed;
1822 case Hexagon::STriw_indexed_shl_nv_V4:
1823 return Hexagon::STriw_indexed_shl_V4;
1825 case Hexagon::STriw_shl_nv_V4:
1826 return Hexagon::STriw_shl_V4;
1828 case Hexagon::STw_GP_nv_V4:
1829 return Hexagon::STw_GP_V4;
1831 case Hexagon::POST_STwri_nv_V4:
1832 return Hexagon::POST_STwri;
1836 case Hexagon::STrid_cdnPt_V4 :
1837 return Hexagon::STrid_cPt;
1839 case Hexagon::STrid_cdnNotPt_V4 :
1840 return Hexagon::STrid_cNotPt;
1842 case Hexagon::STrid_indexed_cdnPt_V4 :
1843 return Hexagon::STrid_indexed_cPt;
1845 case Hexagon::STrid_indexed_cdnNotPt_V4 :
1846 return Hexagon::STrid_indexed_cNotPt;
1848 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1849 return Hexagon::STrid_indexed_shl_cPt_V4;
1851 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
1852 return Hexagon::STrid_indexed_shl_cNotPt_V4;
1854 case Hexagon::POST_STdri_cdnPt_V4 :
1855 return Hexagon::POST_STdri_cPt;
1857 case Hexagon::POST_STdri_cdnNotPt_V4 :
1858 return Hexagon::POST_STdri_cNotPt;
1860 case Hexagon::STd_GP_cdnPt_V4 :
1861 return Hexagon::STd_GP_cPt_V4;
1863 case Hexagon::STd_GP_cdnNotPt_V4 :
1864 return Hexagon::STd_GP_cNotPt_V4;
1869 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
1870 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1871 int NewOpcode = GetDotOldOp(MI->getOpcode());
1872 MI->setDesc(QII->get(NewOpcode));
1876 // Returns true if an instruction is predicated on p0 and false if it's
1877 // predicated on !p0.
1879 static bool GetPredicateSense(MachineInstr* MI,
1880 const HexagonInstrInfo *QII) {
1882 switch (MI->getOpcode()) {
1883 default: llvm_unreachable("Unknown predicate sense of the instruction");
1884 case Hexagon::TFR_cPt:
1885 case Hexagon::TFR_cdnPt:
1886 case Hexagon::TFRI_cPt:
1887 case Hexagon::TFRI_cdnPt:
1888 case Hexagon::STrib_cPt :
1889 case Hexagon::STrib_cdnPt_V4 :
1890 case Hexagon::STrib_indexed_cPt :
1891 case Hexagon::STrib_indexed_cdnPt_V4 :
1892 case Hexagon::STrib_indexed_shl_cPt_V4 :
1893 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1894 case Hexagon::POST_STbri_cPt :
1895 case Hexagon::POST_STbri_cdnPt_V4 :
1896 case Hexagon::STrih_cPt :
1897 case Hexagon::STrih_cdnPt_V4 :
1898 case Hexagon::STrih_indexed_cPt :
1899 case Hexagon::STrih_indexed_cdnPt_V4 :
1900 case Hexagon::STrih_indexed_shl_cPt_V4 :
1901 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1902 case Hexagon::POST_SThri_cPt :
1903 case Hexagon::POST_SThri_cdnPt_V4 :
1904 case Hexagon::STriw_cPt :
1905 case Hexagon::STriw_cdnPt_V4 :
1906 case Hexagon::STriw_indexed_cPt :
1907 case Hexagon::STriw_indexed_cdnPt_V4 :
1908 case Hexagon::STriw_indexed_shl_cPt_V4 :
1909 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1910 case Hexagon::POST_STwri_cPt :
1911 case Hexagon::POST_STwri_cdnPt_V4 :
1912 case Hexagon::STrib_imm_cPt_V4 :
1913 case Hexagon::STrib_imm_cdnPt_V4 :
1914 case Hexagon::STrid_cPt :
1915 case Hexagon::STrid_cdnPt_V4 :
1916 case Hexagon::STrid_indexed_cPt :
1917 case Hexagon::STrid_indexed_cdnPt_V4 :
1918 case Hexagon::STrid_indexed_shl_cPt_V4 :
1919 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1920 case Hexagon::POST_STdri_cPt :
1921 case Hexagon::POST_STdri_cdnPt_V4 :
1922 case Hexagon::STrih_imm_cPt_V4 :
1923 case Hexagon::STrih_imm_cdnPt_V4 :
1924 case Hexagon::STriw_imm_cPt_V4 :
1925 case Hexagon::STriw_imm_cdnPt_V4 :
1926 case Hexagon::JMP_cdnPt :
1927 case Hexagon::LDrid_cPt :
1928 case Hexagon::LDrid_cdnPt :
1929 case Hexagon::LDrid_indexed_cPt :
1930 case Hexagon::LDrid_indexed_cdnPt :
1931 case Hexagon::POST_LDrid_cPt :
1932 case Hexagon::POST_LDrid_cdnPt_V4 :
1933 case Hexagon::LDriw_cPt :
1934 case Hexagon::LDriw_cdnPt :
1935 case Hexagon::LDriw_indexed_cPt :
1936 case Hexagon::LDriw_indexed_cdnPt :
1937 case Hexagon::POST_LDriw_cPt :
1938 case Hexagon::POST_LDriw_cdnPt_V4 :
1939 case Hexagon::LDrih_cPt :
1940 case Hexagon::LDrih_cdnPt :
1941 case Hexagon::LDrih_indexed_cPt :
1942 case Hexagon::LDrih_indexed_cdnPt :
1943 case Hexagon::POST_LDrih_cPt :
1944 case Hexagon::POST_LDrih_cdnPt_V4 :
1945 case Hexagon::LDrib_cPt :
1946 case Hexagon::LDrib_cdnPt :
1947 case Hexagon::LDrib_indexed_cPt :
1948 case Hexagon::LDrib_indexed_cdnPt :
1949 case Hexagon::POST_LDrib_cPt :
1950 case Hexagon::POST_LDrib_cdnPt_V4 :
1951 case Hexagon::LDriuh_cPt :
1952 case Hexagon::LDriuh_cdnPt :
1953 case Hexagon::LDriuh_indexed_cPt :
1954 case Hexagon::LDriuh_indexed_cdnPt :
1955 case Hexagon::POST_LDriuh_cPt :
1956 case Hexagon::POST_LDriuh_cdnPt_V4 :
1957 case Hexagon::LDriub_cPt :
1958 case Hexagon::LDriub_cdnPt :
1959 case Hexagon::LDriub_indexed_cPt :
1960 case Hexagon::LDriub_indexed_cdnPt :
1961 case Hexagon::POST_LDriub_cPt :
1962 case Hexagon::POST_LDriub_cdnPt_V4 :
1963 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1964 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1965 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1966 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1967 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1968 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1969 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1970 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1971 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1972 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1973 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1974 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1975 case Hexagon::ADD_ri_cPt :
1976 case Hexagon::ADD_ri_cdnPt :
1977 case Hexagon::ADD_rr_cPt :
1978 case Hexagon::ADD_rr_cdnPt :
1979 case Hexagon::XOR_rr_cPt :
1980 case Hexagon::XOR_rr_cdnPt :
1981 case Hexagon::AND_rr_cPt :
1982 case Hexagon::AND_rr_cdnPt :
1983 case Hexagon::OR_rr_cPt :
1984 case Hexagon::OR_rr_cdnPt :
1985 case Hexagon::SUB_rr_cPt :
1986 case Hexagon::SUB_rr_cdnPt :
1987 case Hexagon::COMBINE_rr_cPt :
1988 case Hexagon::COMBINE_rr_cdnPt :
1989 case Hexagon::ASLH_cPt_V4 :
1990 case Hexagon::ASLH_cdnPt_V4 :
1991 case Hexagon::ASRH_cPt_V4 :
1992 case Hexagon::ASRH_cdnPt_V4 :
1993 case Hexagon::SXTB_cPt_V4 :
1994 case Hexagon::SXTB_cdnPt_V4 :
1995 case Hexagon::SXTH_cPt_V4 :
1996 case Hexagon::SXTH_cdnPt_V4 :
1997 case Hexagon::ZXTB_cPt_V4 :
1998 case Hexagon::ZXTB_cdnPt_V4 :
1999 case Hexagon::ZXTH_cPt_V4 :
2000 case Hexagon::ZXTH_cdnPt_V4 :
2001 case Hexagon::LDd_GP_cPt_V4 :
2002 case Hexagon::LDb_GP_cPt_V4 :
2003 case Hexagon::LDub_GP_cPt_V4 :
2004 case Hexagon::LDh_GP_cPt_V4 :
2005 case Hexagon::LDuh_GP_cPt_V4 :
2006 case Hexagon::LDw_GP_cPt_V4 :
2007 case Hexagon::STd_GP_cPt_V4 :
2008 case Hexagon::STb_GP_cPt_V4 :
2009 case Hexagon::STh_GP_cPt_V4 :
2010 case Hexagon::STw_GP_cPt_V4 :
2011 case Hexagon::LDd_GP_cdnPt_V4 :
2012 case Hexagon::LDb_GP_cdnPt_V4 :
2013 case Hexagon::LDub_GP_cdnPt_V4 :
2014 case Hexagon::LDh_GP_cdnPt_V4 :
2015 case Hexagon::LDuh_GP_cdnPt_V4 :
2016 case Hexagon::LDw_GP_cdnPt_V4 :
2017 case Hexagon::STd_GP_cdnPt_V4 :
2018 case Hexagon::STb_GP_cdnPt_V4 :
2019 case Hexagon::STh_GP_cdnPt_V4 :
2020 case Hexagon::STw_GP_cdnPt_V4 :
2023 case Hexagon::TFR_cNotPt:
2024 case Hexagon::TFR_cdnNotPt:
2025 case Hexagon::TFRI_cNotPt:
2026 case Hexagon::TFRI_cdnNotPt:
2027 case Hexagon::STrib_cNotPt :
2028 case Hexagon::STrib_cdnNotPt_V4 :
2029 case Hexagon::STrib_indexed_cNotPt :
2030 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2031 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2032 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2033 case Hexagon::POST_STbri_cNotPt :
2034 case Hexagon::POST_STbri_cdnNotPt_V4 :
2035 case Hexagon::STrih_cNotPt :
2036 case Hexagon::STrih_cdnNotPt_V4 :
2037 case Hexagon::STrih_indexed_cNotPt :
2038 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2039 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2040 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2041 case Hexagon::POST_SThri_cNotPt :
2042 case Hexagon::POST_SThri_cdnNotPt_V4 :
2043 case Hexagon::STriw_cNotPt :
2044 case Hexagon::STriw_cdnNotPt_V4 :
2045 case Hexagon::STriw_indexed_cNotPt :
2046 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2047 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2048 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2049 case Hexagon::POST_STwri_cNotPt :
2050 case Hexagon::POST_STwri_cdnNotPt_V4 :
2051 case Hexagon::STrib_imm_cNotPt_V4 :
2052 case Hexagon::STrib_imm_cdnNotPt_V4 :
2053 case Hexagon::STrid_cNotPt :
2054 case Hexagon::STrid_cdnNotPt_V4 :
2055 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2056 case Hexagon::STrid_indexed_cNotPt :
2057 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
2058 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2059 case Hexagon::POST_STdri_cNotPt :
2060 case Hexagon::POST_STdri_cdnNotPt_V4 :
2061 case Hexagon::STrih_imm_cNotPt_V4 :
2062 case Hexagon::STrih_imm_cdnNotPt_V4 :
2063 case Hexagon::STriw_imm_cNotPt_V4 :
2064 case Hexagon::STriw_imm_cdnNotPt_V4 :
2065 case Hexagon::JMP_cdnNotPt :
2066 case Hexagon::LDrid_cNotPt :
2067 case Hexagon::LDrid_cdnNotPt :
2068 case Hexagon::LDrid_indexed_cNotPt :
2069 case Hexagon::LDrid_indexed_cdnNotPt :
2070 case Hexagon::POST_LDrid_cNotPt :
2071 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2072 case Hexagon::LDriw_cNotPt :
2073 case Hexagon::LDriw_cdnNotPt :
2074 case Hexagon::LDriw_indexed_cNotPt :
2075 case Hexagon::LDriw_indexed_cdnNotPt :
2076 case Hexagon::POST_LDriw_cNotPt :
2077 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2078 case Hexagon::LDrih_cNotPt :
2079 case Hexagon::LDrih_cdnNotPt :
2080 case Hexagon::LDrih_indexed_cNotPt :
2081 case Hexagon::LDrih_indexed_cdnNotPt :
2082 case Hexagon::POST_LDrih_cNotPt :
2083 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2084 case Hexagon::LDrib_cNotPt :
2085 case Hexagon::LDrib_cdnNotPt :
2086 case Hexagon::LDrib_indexed_cNotPt :
2087 case Hexagon::LDrib_indexed_cdnNotPt :
2088 case Hexagon::POST_LDrib_cNotPt :
2089 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2090 case Hexagon::LDriuh_cNotPt :
2091 case Hexagon::LDriuh_cdnNotPt :
2092 case Hexagon::LDriuh_indexed_cNotPt :
2093 case Hexagon::LDriuh_indexed_cdnNotPt :
2094 case Hexagon::POST_LDriuh_cNotPt :
2095 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2096 case Hexagon::LDriub_cNotPt :
2097 case Hexagon::LDriub_cdnNotPt :
2098 case Hexagon::LDriub_indexed_cNotPt :
2099 case Hexagon::LDriub_indexed_cdnNotPt :
2100 case Hexagon::POST_LDriub_cNotPt :
2101 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2102 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2103 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2104 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2105 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2106 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2107 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2108 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2109 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2110 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2111 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2112 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2113 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2114 case Hexagon::ADD_ri_cNotPt :
2115 case Hexagon::ADD_ri_cdnNotPt :
2116 case Hexagon::ADD_rr_cNotPt :
2117 case Hexagon::ADD_rr_cdnNotPt :
2118 case Hexagon::XOR_rr_cNotPt :
2119 case Hexagon::XOR_rr_cdnNotPt :
2120 case Hexagon::AND_rr_cNotPt :
2121 case Hexagon::AND_rr_cdnNotPt :
2122 case Hexagon::OR_rr_cNotPt :
2123 case Hexagon::OR_rr_cdnNotPt :
2124 case Hexagon::SUB_rr_cNotPt :
2125 case Hexagon::SUB_rr_cdnNotPt :
2126 case Hexagon::COMBINE_rr_cNotPt :
2127 case Hexagon::COMBINE_rr_cdnNotPt :
2128 case Hexagon::ASLH_cNotPt_V4 :
2129 case Hexagon::ASLH_cdnNotPt_V4 :
2130 case Hexagon::ASRH_cNotPt_V4 :
2131 case Hexagon::ASRH_cdnNotPt_V4 :
2132 case Hexagon::SXTB_cNotPt_V4 :
2133 case Hexagon::SXTB_cdnNotPt_V4 :
2134 case Hexagon::SXTH_cNotPt_V4 :
2135 case Hexagon::SXTH_cdnNotPt_V4 :
2136 case Hexagon::ZXTB_cNotPt_V4 :
2137 case Hexagon::ZXTB_cdnNotPt_V4 :
2138 case Hexagon::ZXTH_cNotPt_V4 :
2139 case Hexagon::ZXTH_cdnNotPt_V4 :
2141 case Hexagon::LDd_GP_cNotPt_V4 :
2142 case Hexagon::LDb_GP_cNotPt_V4 :
2143 case Hexagon::LDub_GP_cNotPt_V4 :
2144 case Hexagon::LDh_GP_cNotPt_V4 :
2145 case Hexagon::LDuh_GP_cNotPt_V4 :
2146 case Hexagon::LDw_GP_cNotPt_V4 :
2147 case Hexagon::STd_GP_cNotPt_V4 :
2148 case Hexagon::STb_GP_cNotPt_V4 :
2149 case Hexagon::STh_GP_cNotPt_V4 :
2150 case Hexagon::STw_GP_cNotPt_V4 :
2151 case Hexagon::LDd_GP_cdnNotPt_V4 :
2152 case Hexagon::LDb_GP_cdnNotPt_V4 :
2153 case Hexagon::LDub_GP_cdnNotPt_V4 :
2154 case Hexagon::LDh_GP_cdnNotPt_V4 :
2155 case Hexagon::LDuh_GP_cdnNotPt_V4 :
2156 case Hexagon::LDw_GP_cdnNotPt_V4 :
2157 case Hexagon::STd_GP_cdnNotPt_V4 :
2158 case Hexagon::STb_GP_cdnNotPt_V4 :
2159 case Hexagon::STh_GP_cdnNotPt_V4 :
2160 case Hexagon::STw_GP_cdnNotPt_V4 :
2163 // return *some value* to avoid compiler warning
2167 bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
2168 if (isNewValueInst(MI))
2171 switch (MI->getOpcode()) {
2172 case Hexagon::TFR_cdnNotPt:
2173 case Hexagon::TFR_cdnPt:
2174 case Hexagon::TFRI_cdnNotPt:
2175 case Hexagon::TFRI_cdnPt:
2176 case Hexagon::LDrid_cdnPt :
2177 case Hexagon::LDrid_cdnNotPt :
2178 case Hexagon::LDrid_indexed_cdnPt :
2179 case Hexagon::LDrid_indexed_cdnNotPt :
2180 case Hexagon::POST_LDrid_cdnPt_V4 :
2181 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2182 case Hexagon::LDriw_cdnPt :
2183 case Hexagon::LDriw_cdnNotPt :
2184 case Hexagon::LDriw_indexed_cdnPt :
2185 case Hexagon::LDriw_indexed_cdnNotPt :
2186 case Hexagon::POST_LDriw_cdnPt_V4 :
2187 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2188 case Hexagon::LDrih_cdnPt :
2189 case Hexagon::LDrih_cdnNotPt :
2190 case Hexagon::LDrih_indexed_cdnPt :
2191 case Hexagon::LDrih_indexed_cdnNotPt :
2192 case Hexagon::POST_LDrih_cdnPt_V4 :
2193 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2194 case Hexagon::LDrib_cdnPt :
2195 case Hexagon::LDrib_cdnNotPt :
2196 case Hexagon::LDrib_indexed_cdnPt :
2197 case Hexagon::LDrib_indexed_cdnNotPt :
2198 case Hexagon::POST_LDrib_cdnPt_V4 :
2199 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2200 case Hexagon::LDriuh_cdnPt :
2201 case Hexagon::LDriuh_cdnNotPt :
2202 case Hexagon::LDriuh_indexed_cdnPt :
2203 case Hexagon::LDriuh_indexed_cdnNotPt :
2204 case Hexagon::POST_LDriuh_cdnPt_V4 :
2205 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2206 case Hexagon::LDriub_cdnPt :
2207 case Hexagon::LDriub_cdnNotPt :
2208 case Hexagon::LDriub_indexed_cdnPt :
2209 case Hexagon::LDriub_indexed_cdnNotPt :
2210 case Hexagon::POST_LDriub_cdnPt_V4 :
2211 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2213 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
2214 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2215 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
2216 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2217 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
2218 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2219 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
2220 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2221 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
2222 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2223 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
2224 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2227 case Hexagon::ADD_ri_cdnPt:
2228 case Hexagon::ADD_ri_cdnNotPt:
2229 case Hexagon::ADD_rr_cdnPt:
2230 case Hexagon::ADD_rr_cdnNotPt:
2232 // Conditional logical operations
2233 case Hexagon::XOR_rr_cdnPt :
2234 case Hexagon::XOR_rr_cdnNotPt :
2235 case Hexagon::AND_rr_cdnPt :
2236 case Hexagon::AND_rr_cdnNotPt :
2237 case Hexagon::OR_rr_cdnPt :
2238 case Hexagon::OR_rr_cdnNotPt :
2240 // Conditonal subtract
2241 case Hexagon::SUB_rr_cdnPt :
2242 case Hexagon::SUB_rr_cdnNotPt :
2244 // Conditional combine
2245 case Hexagon::COMBINE_rr_cdnPt :
2246 case Hexagon::COMBINE_rr_cdnNotPt :
2248 // Conditional shift operations
2249 case Hexagon::ASLH_cdnPt_V4:
2250 case Hexagon::ASLH_cdnNotPt_V4:
2251 case Hexagon::ASRH_cdnPt_V4:
2252 case Hexagon::ASRH_cdnNotPt_V4:
2253 case Hexagon::SXTB_cdnPt_V4:
2254 case Hexagon::SXTB_cdnNotPt_V4:
2255 case Hexagon::SXTH_cdnPt_V4:
2256 case Hexagon::SXTH_cdnNotPt_V4:
2257 case Hexagon::ZXTB_cdnPt_V4:
2258 case Hexagon::ZXTB_cdnNotPt_V4:
2259 case Hexagon::ZXTH_cdnPt_V4:
2260 case Hexagon::ZXTH_cdnNotPt_V4:
2262 // Conditional stores
2263 case Hexagon::STrib_imm_cdnPt_V4 :
2264 case Hexagon::STrib_imm_cdnNotPt_V4 :
2265 case Hexagon::STrib_cdnPt_V4 :
2266 case Hexagon::STrib_cdnNotPt_V4 :
2267 case Hexagon::STrib_indexed_cdnPt_V4 :
2268 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2269 case Hexagon::POST_STbri_cdnPt_V4 :
2270 case Hexagon::POST_STbri_cdnNotPt_V4 :
2271 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
2272 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2274 // Store doubleword conditionally
2275 case Hexagon::STrid_indexed_cdnPt_V4 :
2276 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2277 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2278 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2279 case Hexagon::POST_STdri_cdnPt_V4 :
2280 case Hexagon::POST_STdri_cdnNotPt_V4 :
2282 // Store halfword conditionally
2283 case Hexagon::STrih_cdnPt_V4 :
2284 case Hexagon::STrih_cdnNotPt_V4 :
2285 case Hexagon::STrih_indexed_cdnPt_V4 :
2286 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2287 case Hexagon::STrih_imm_cdnPt_V4 :
2288 case Hexagon::STrih_imm_cdnNotPt_V4 :
2289 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
2290 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2291 case Hexagon::POST_SThri_cdnPt_V4 :
2292 case Hexagon::POST_SThri_cdnNotPt_V4 :
2294 // Store word conditionally
2295 case Hexagon::STriw_cdnPt_V4 :
2296 case Hexagon::STriw_cdnNotPt_V4 :
2297 case Hexagon::STriw_indexed_cdnPt_V4 :
2298 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2299 case Hexagon::STriw_imm_cdnPt_V4 :
2300 case Hexagon::STriw_imm_cdnNotPt_V4 :
2301 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2302 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2303 case Hexagon::POST_STwri_cdnPt_V4 :
2304 case Hexagon::POST_STwri_cdnNotPt_V4 :
2306 case Hexagon::LDd_GP_cdnPt_V4:
2307 case Hexagon::LDd_GP_cdnNotPt_V4:
2308 case Hexagon::LDb_GP_cdnPt_V4:
2309 case Hexagon::LDb_GP_cdnNotPt_V4:
2310 case Hexagon::LDub_GP_cdnPt_V4:
2311 case Hexagon::LDub_GP_cdnNotPt_V4:
2312 case Hexagon::LDh_GP_cdnPt_V4:
2313 case Hexagon::LDh_GP_cdnNotPt_V4:
2314 case Hexagon::LDuh_GP_cdnPt_V4:
2315 case Hexagon::LDuh_GP_cdnNotPt_V4:
2316 case Hexagon::LDw_GP_cdnPt_V4:
2317 case Hexagon::LDw_GP_cdnNotPt_V4:
2319 case Hexagon::STd_GP_cdnPt_V4:
2320 case Hexagon::STd_GP_cdnNotPt_V4:
2321 case Hexagon::STb_GP_cdnPt_V4:
2322 case Hexagon::STb_GP_cdnNotPt_V4:
2323 case Hexagon::STh_GP_cdnPt_V4:
2324 case Hexagon::STh_GP_cdnNotPt_V4:
2325 case Hexagon::STw_GP_cdnPt_V4:
2326 case Hexagon::STw_GP_cdnNotPt_V4:
2332 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
2333 const HexagonInstrInfo *QII) {
2334 assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
2336 // Post Increment means duplicates. Use dense map to find duplicates in the
2337 // list. Caution: Densemap initializes with the minimum of 64 buckets,
2338 // whereas there are at most 5 operands in the post increment.
2339 DenseMap<unsigned, unsigned> DefRegsSet;
2340 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2341 if (MI->getOperand(opNum).isReg() &&
2342 MI->getOperand(opNum).isDef()) {
2343 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
2346 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2347 if (MI->getOperand(opNum).isReg() &&
2348 MI->getOperand(opNum).isUse()) {
2349 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
2350 return MI->getOperand(opNum);
2354 if (MI->getDesc().mayLoad()) {
2355 // The 2nd operand is always the post increment operand in load.
2356 assert(MI->getOperand(1).isReg() &&
2357 "Post increment operand has be to a register.");
2358 return (MI->getOperand(1));
2360 if (MI->getDesc().mayStore()) {
2361 // The 1st operand is always the post increment operand in store.
2362 assert(MI->getOperand(0).isReg() &&
2363 "Post increment operand has be to a register.");
2364 return (MI->getOperand(0));
2367 // we should never come here.
2368 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
2371 // get the value being stored
2372 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
2373 // value being stored is always the last operand.
2374 return (MI->getOperand(MI->getNumOperands()-1));
2377 // can be new value store?
2378 // Following restrictions are to be respected in convert a store into
2379 // a new value store.
2380 // 1. If an instruction uses auto-increment, its address register cannot
2381 // be a new-value register. Arch Spec 5.4.2.1
2382 // 2. If an instruction uses absolute-set addressing mode,
2383 // its address register cannot be a new-value register.
2384 // Arch Spec 5.4.2.1.TODO: This is not enabled as
2385 // as absolute-set address mode patters are not implemented.
2386 // 3. If an instruction produces a 64-bit result, its registers cannot be used
2387 // as new-value registers. Arch Spec 5.4.2.2.
2388 // 4. If the instruction that sets a new-value register is conditional, then
2389 // the instruction that uses the new-value register must also be conditional,
2390 // and both must always have their predicates evaluate identically.
2391 // Arch Spec 5.4.2.3.
2392 // 5. There is an implied restriction of a packet can not have another store,
2393 // if there is a new value store in the packet. Corollary, if there is
2394 // already a store in a packet, there can not be a new value store.
2395 // Arch Spec: 3.4.4.2
2396 bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
2397 MachineInstr *PacketMI, unsigned DepReg,
2398 std::map <MachineInstr*, SUnit*> MIToSUnit)
2400 // Make sure we are looking at the store
2401 if (!IsNewifyStore(MI))
2404 // Make sure there is dependency and can be new value'ed
2405 if (GetStoreValueOperand(MI).isReg() &&
2406 GetStoreValueOperand(MI).getReg() != DepReg)
2409 const HexagonRegisterInfo* QRI =
2410 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2411 const MCInstrDesc& MCID = PacketMI->getDesc();
2412 // first operand is always the result
2414 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2415 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
2417 // if there is already an store in the packet, no can do new value store
2418 // Arch Spec 3.4.4.2.
2419 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
2420 VE = CurrentPacketMIs.end();
2422 SUnit* PacketSU = MIToSUnit[*VI];
2423 if (PacketSU->getInstr()->getDesc().mayStore() ||
2424 // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
2425 // then we don't need this
2426 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2427 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
2431 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
2432 // new value store constraint: double regs can not feed into new value store
2433 // arch spec section: 5.4.2.2
2437 // Make sure it's NOT the post increment register that we are going to
2439 if (QII->isPostIncrement(MI) &&
2440 MI->getDesc().mayStore() &&
2441 GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
2445 if (QII->isPostIncrement(PacketMI) &&
2446 PacketMI->getDesc().mayLoad() &&
2447 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
2448 // if source is post_inc, or absolute-set addressing,
2449 // it can not feed into new value store
2450 // r3 = memw(r2++#4)
2451 // memw(r30 + #-1404) = r2.new -> can not be new value store
2452 // arch spec section: 5.4.2.1
2456 // If the source that feeds the store is predicated, new value store must
2457 // also be also predicated.
2458 if (QII->isPredicated(PacketMI)) {
2459 if (!QII->isPredicated(MI))
2462 // Check to make sure that they both will have their predicates
2463 // evaluate identically
2464 unsigned predRegNumSrc = 0;
2465 unsigned predRegNumDst = 0;
2466 const TargetRegisterClass* predRegClass = NULL;
2468 // Get predicate register used in the source instruction
2469 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2470 if ( PacketMI->getOperand(opNum).isReg())
2471 predRegNumSrc = PacketMI->getOperand(opNum).getReg();
2472 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
2473 if (predRegClass == &Hexagon::PredRegsRegClass) {
2477 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2478 ("predicate register not found in a predicated PacketMI instruction"));
2480 // Get predicate register used in new-value store instruction
2481 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2482 if ( MI->getOperand(opNum).isReg())
2483 predRegNumDst = MI->getOperand(opNum).getReg();
2484 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
2485 if (predRegClass == &Hexagon::PredRegsRegClass) {
2489 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2490 ("predicate register not found in a predicated MI instruction"));
2492 // New-value register producer and user (store) need to satisfy these
2494 // 1) Both instructions should be predicated on the same register.
2495 // 2) If producer of the new-value register is .new predicated then store
2496 // should also be .new predicated and if producer is not .new predicated
2497 // then store should not be .new predicated.
2498 // 3) Both new-value register producer and user should have same predicate
2499 // sense, i.e, either both should be negated or both should be none negated.
2501 if (( predRegNumDst != predRegNumSrc) ||
2502 isDotNewInst(PacketMI) != isDotNewInst(MI) ||
2503 GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
2508 // Make sure that other than the new-value register no other store instruction
2509 // register has been modified in the same packet. Predicate registers can be
2510 // modified by they should not be modified between the producer and the store
2511 // instruction as it will make them both conditional on different values.
2512 // We already know this to be true for all the instructions before and
2513 // including PacketMI. Howerver, we need to perform the check for the
2514 // remaining instructions in the packet.
2516 std::vector<MachineInstr*>::iterator VI;
2517 std::vector<MachineInstr*>::iterator VE;
2518 unsigned StartCheck = 0;
2520 for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
2522 SUnit* TempSU = MIToSUnit[*VI];
2523 MachineInstr* TempMI = TempSU->getInstr();
2525 // Following condition is true for all the instructions until PacketMI is
2526 // reached (StartCheck is set to 0 before the for loop).
2527 // StartCheck flag is 1 for all the instructions after PacketMI.
2528 if (TempMI != PacketMI && !StartCheck) // start processing only after
2529 continue; // encountering PacketMI
2532 if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
2535 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2536 if (MI->getOperand(opNum).isReg() &&
2537 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
2543 // Make sure that for non POST_INC stores:
2544 // 1. The only use of reg is DepReg and no other registers.
2545 // This handles V4 base+index registers.
2546 // The following store can not be dot new.
2547 // Eg. r0 = add(r0, #3)a
2548 // memw(r1+r0<<#2) = r0
2549 if (!QII->isPostIncrement(MI) &&
2550 GetStoreValueOperand(MI).isReg() &&
2551 GetStoreValueOperand(MI).getReg() == DepReg) {
2552 for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
2553 if (MI->getOperand(opNum).isReg() &&
2554 MI->getOperand(opNum).getReg() == DepReg) {
2558 // 2. If data definition is because of implicit definition of the register,
2559 // do not newify the store. Eg.
2560 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
2561 // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
2562 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2563 if (PacketMI->getOperand(opNum).isReg() &&
2564 PacketMI->getOperand(opNum).getReg() == DepReg &&
2565 PacketMI->getOperand(opNum).isDef() &&
2566 PacketMI->getOperand(opNum).isImplicit()) {
2572 // Can be dot new store.
2576 // can this MI to promoted to either
2577 // new value store or new value jump
2578 bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
2579 SUnit *PacketSU, unsigned DepReg,
2580 std::map <MachineInstr*, SUnit*> MIToSUnit,
2581 MachineBasicBlock::iterator &MII)
2584 const HexagonRegisterInfo* QRI =
2585 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2586 if (!QRI->Subtarget.hasV4TOps() ||
2590 MachineInstr *PacketMI = PacketSU->getInstr();
2592 // Check to see the store can be new value'ed.
2593 if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
2596 // Check to see the compare/jump can be new value'ed.
2597 // This is done as a pass on its own. Don't need to check it here.
2601 // Check to see if an instruction can be dot new
2602 // There are three kinds.
2603 // 1. dot new on predicate - V2/V3/V4
2604 // 2. dot new on stores NV/ST - V4
2605 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
2606 bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
2607 SUnit *PacketSU, unsigned DepReg,
2608 std::map <MachineInstr*, SUnit*> MIToSUnit,
2609 MachineBasicBlock::iterator &MII,
2610 const TargetRegisterClass* RC )
2612 // already a dot new instruction
2613 if (isDotNewInst(MI) && !IsNewifyStore(MI))
2616 if (!isNewifiable(MI))
2620 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
2622 else if (RC != &Hexagon::PredRegsRegClass &&
2623 !IsNewifyStore(MI)) // MI is not a new-value store
2626 // Create a dot new machine instruction to see if resources can be
2627 // allocated. If not, bail out now.
2628 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2629 int NewOpcode = GetDotNewOp(MI->getOpcode());
2630 const MCInstrDesc &desc = QII->get(NewOpcode);
2632 MachineInstr *NewMI =
2633 MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
2634 bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
2635 MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
2637 if (!ResourcesAvailable)
2640 // new value store only
2641 // new new value jump generated as a passes
2642 if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
2649 // Go through the packet instructions and search for anti dependency
2650 // between them and DepReg from MI
2651 // Consider this case:
2653 // a) %R1<def> = TFRI_cdNotPt %P3, 2
2656 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
2657 // c) %P3<def> = TFR_PdRs %R23
2658 // d) %R1<def> = TFRI_cdnPt %P3, 4
2660 // The P3 from a) and d) will be complements after
2661 // a)'s P3 is converted to .new form
2662 // Anti Dep between c) and b) is irrelevant for this case
2663 bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
2665 std::map <MachineInstr*, SUnit*> MIToSUnit) {
2667 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2668 SUnit* PacketSUDep = MIToSUnit[MI];
2670 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2671 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2673 // We only care for dependencies to predicated instructions
2674 if(!QII->isPredicated(*VIN)) continue;
2676 // Scheduling Unit for current insn in the packet
2677 SUnit* PacketSU = MIToSUnit[*VIN];
2679 // Look at dependencies between current members of the packet
2680 // and predicate defining instruction MI.
2681 // Make sure that dependency is on the exact register
2683 if (PacketSU->isSucc(PacketSUDep)) {
2684 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2685 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
2686 (PacketSU->Succs[i].getKind() == SDep::Anti) &&
2687 (PacketSU->Succs[i].getReg() == DepReg)) {
2698 // Given two predicated instructions, this function detects whether
2699 // the predicates are complements
2700 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
2701 MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
2703 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2704 // Currently can only reason about conditional transfers
2705 if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
2709 // Scheduling unit for candidate
2710 SUnit* SU = MIToSUnit[MI1];
2712 // One corner case deals with the following scenario:
2714 // a) %R24<def> = TFR_cPt %P0, %R25
2718 // b) %R25<def> = TFR_cNotPt %P0, %R24
2719 // c) %P0<def> = CMPEQri %R26, 1
2722 // On general check a) and b) are complements, but
2723 // presence of c) will convert a) to .new form, and
2724 // then it is not a complement
2725 // We attempt to detect it by analyzing existing
2726 // dependencies in the packet
2728 // Analyze relationships between all existing members of the packet.
2729 // Look for Anti dependecy on the same predicate reg
2730 // as used in the candidate
2731 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2732 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2734 // Scheduling Unit for current insn in the packet
2735 SUnit* PacketSU = MIToSUnit[*VIN];
2737 // If this instruction in the packet is succeeded by the candidate...
2738 if (PacketSU->isSucc(SU)) {
2739 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2740 // The corner case exist when there is true data
2741 // dependency between candidate and one of current
2742 // packet members, this dep is on predicate reg, and
2743 // there already exist anti dep on the same pred in
2745 if (PacketSU->Succs[i].getSUnit() == SU &&
2746 Hexagon::PredRegsRegClass.contains(
2747 PacketSU->Succs[i].getReg()) &&
2748 PacketSU->Succs[i].getKind() == SDep::Data &&
2749 // Here I know that *VIN is predicate setting instruction
2750 // with true data dep to candidate on the register
2751 // we care about - c) in the above example.
2752 // Now I need to see if there is an anti dependency
2753 // from c) to any other instruction in the
2754 // same packet on the pred reg of interest
2755 RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
2763 // If the above case does not apply, check regular
2764 // complement condition.
2765 // Check that the predicate register is the same and
2766 // that the predicate sense is different
2767 // We also need to differentiate .old vs. .new:
2768 // !p0 is not complimentary to p0.new
2769 return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
2770 (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
2771 (isDotNewInst(MI1) == isDotNewInst(MI2)));
2774 // initPacketizerState - Initialize packetizer flags
2775 void HexagonPacketizerList::initPacketizerState() {
2778 PromotedToDotNew = false;
2779 GlueToNewValueJump = false;
2780 GlueAllocframeStore = false;
2781 FoundSequentialDependence = false;
2786 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
2787 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
2788 MachineBasicBlock *MBB) {
2789 if (MI->isDebugValue())
2792 // We must print out inline assembly
2793 if (MI->isInlineAsm())
2796 // We check if MI has any functional units mapped to it.
2797 // If it doesn't, we ignore the instruction.
2798 const MCInstrDesc& TID = MI->getDesc();
2799 unsigned SchedClass = TID.getSchedClass();
2800 const InstrStage* IS =
2801 ResourceTracker->getInstrItins()->beginStage(SchedClass);
2802 unsigned FuncUnits = IS->getUnits();
2806 // isSoloInstruction: - Returns true for instructions that must be
2807 // scheduled in their own packet.
2808 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
2810 if (MI->isInlineAsm())
2813 if (MI->isEHLabel())
2816 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
2817 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
2818 // They must not be grouped with other instructions in a packet.
2819 if (IsSchedBarrier(MI))
2825 // isLegalToPacketizeTogether:
2826 // SUI is the current instruction that is out side of the current packet.
2827 // SUJ is the current instruction inside the current packet against which that
2828 // SUI will be packetized.
2829 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
2830 MachineInstr *I = SUI->getInstr();
2831 MachineInstr *J = SUJ->getInstr();
2832 assert(I && J && "Unable to packetize null instruction!");
2834 const MCInstrDesc &MCIDI = I->getDesc();
2835 const MCInstrDesc &MCIDJ = J->getDesc();
2837 MachineBasicBlock::iterator II = I;
2839 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
2840 const HexagonRegisterInfo* QRI =
2841 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2842 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2844 // Inline asm cannot go in the packet.
2845 if (I->getOpcode() == Hexagon::INLINEASM)
2846 llvm_unreachable("Should not meet inline asm here!");
2848 if (isSoloInstruction(I))
2849 llvm_unreachable("Should not meet solo instr here!");
2851 // A save callee-save register function call can only be in a packet
2852 // with instructions that don't write to the callee-save registers.
2853 if ((QII->isSaveCalleeSavedRegsCall(I) &&
2854 DoesModifyCalleeSavedReg(J, QRI)) ||
2855 (QII->isSaveCalleeSavedRegsCall(J) &&
2856 DoesModifyCalleeSavedReg(I, QRI))) {
2861 // Two control flow instructions cannot go in the same packet.
2862 if (IsControlFlow(I) && IsControlFlow(J)) {
2867 // A LoopN instruction cannot appear in the same packet as a jump or call.
2868 if (IsLoopN(I) && ( IsDirectJump(J)
2870 || QII->isDeallocRet(J))) {
2874 if (IsLoopN(J) && ( IsDirectJump(I)
2876 || QII->isDeallocRet(I))) {
2881 // dealloc_return cannot appear in the same packet as a conditional or
2882 // unconditional jump.
2883 if (QII->isDeallocRet(I) && ( MCIDJ.isBranch()
2885 || MCIDJ.isBarrier())) {
2891 // V4 allows dual store. But does not allow second store, if the
2892 // first store is not in SLOT0. New value store, new value jump,
2893 // dealloc_return and memop always take SLOT0.
2894 // Arch spec 3.4.4.2
2895 if (QRI->Subtarget.hasV4TOps()) {
2897 if (MCIDI.mayStore() && MCIDJ.mayStore() && isNewValueInst(J)) {
2902 if ( (QII->isMemOp(J) && MCIDI.mayStore())
2903 || (MCIDJ.mayStore() && QII->isMemOp(I))
2904 || (QII->isMemOp(J) && QII->isMemOp(I))) {
2910 if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
2915 // If an instruction feeds new value jump, glue it.
2916 MachineBasicBlock::iterator NextMII = I;
2918 MachineInstr *NextMI = NextMII;
2920 if (QII->isNewValueJump(NextMI)) {
2922 bool secondRegMatch = false;
2923 bool maintainNewValueJump = false;
2925 if (NextMI->getOperand(1).isReg() &&
2926 I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
2927 secondRegMatch = true;
2928 maintainNewValueJump = true;
2931 if (!secondRegMatch &&
2932 I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
2933 maintainNewValueJump = true;
2936 for (std::vector<MachineInstr*>::iterator
2937 VI = CurrentPacketMIs.begin(),
2938 VE = CurrentPacketMIs.end();
2939 (VI != VE && maintainNewValueJump); ++VI) {
2940 SUnit* PacketSU = MIToSUnit[*VI];
2942 // NVJ can not be part of the dual jump - Arch Spec: section 7.8
2943 if (PacketSU->getInstr()->getDesc().isCall()) {
2948 // 1. Packet does not have a store in it.
2949 // 2. If the first operand of the nvj is newified, and the second
2950 // operand is also a reg, it (second reg) is not defined in
2952 // 3. If the second operand of the nvj is newified, (which means
2953 // first operand is also a reg), first reg is not defined in
2955 if (PacketSU->getInstr()->getDesc().mayStore() ||
2956 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2958 (!secondRegMatch && NextMI->getOperand(1).isReg() &&
2959 PacketSU->getInstr()->modifiesRegister(
2960 NextMI->getOperand(1).getReg(), QRI)) ||
2963 PacketSU->getInstr()->modifiesRegister(
2964 NextMI->getOperand(0).getReg(), QRI))) {
2970 GlueToNewValueJump = true;
2976 if (SUJ->isSucc(SUI)) {
2977 for (unsigned i = 0;
2978 (i < SUJ->Succs.size()) && !FoundSequentialDependence;
2981 if (SUJ->Succs[i].getSUnit() != SUI) {
2985 SDep::Kind DepType = SUJ->Succs[i].getKind();
2987 // For direct calls:
2988 // Ignore register dependences for call instructions for
2989 // packetization purposes except for those due to r31 and
2990 // predicate registers.
2992 // For indirect calls:
2993 // Same as direct calls + check for true dependences to the register
2994 // used in the indirect call.
2996 // We completely ignore Order dependences for call instructions
2999 // Ignore register dependences for return instructions like jumpr,
3000 // dealloc return unless we have dependencies on the explicit uses
3001 // of the registers used by jumpr (like r31) or dealloc return
3002 // (like r29 or r30).
3004 // TODO: Currently, jumpr is handling only return of r31. So, the
3005 // following logic (specificaly IsCallDependent) is working fine.
3006 // We need to enable jumpr for register other than r31 and then,
3007 // we need to rework the last part, where it handles indirect call
3008 // of that (IsCallDependent) function. Bug 6216 is opened for this.
3010 unsigned DepReg = 0;
3011 const TargetRegisterClass* RC = NULL;
3012 if (DepType == SDep::Data) {
3013 DepReg = SUJ->Succs[i].getReg();
3014 RC = QRI->getMinimalPhysRegClass(DepReg);
3016 if ((MCIDI.isCall() || MCIDI.isReturn()) &&
3017 (!IsRegDependence(DepType) ||
3018 !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
3022 // For instructions that can be promoted to dot-new, try to promote.
3023 else if ((DepType == SDep::Data) &&
3024 CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
3025 PromoteToDotNew(I, DepType, II, RC)) {
3026 PromotedToDotNew = true;
3030 else if ((DepType == SDep::Data) &&
3031 (QII->isNewValueJump(I))) {
3035 // For predicated instructions, if the predicates are complements
3036 // then there can be no dependence.
3037 else if (QII->isPredicated(I) &&
3038 QII->isPredicated(J) &&
3039 ArePredicatesComplements(I, J, MIToSUnit)) {
3043 else if (IsDirectJump(I) &&
3044 !MCIDJ.isBranch() &&
3046 (DepType == SDep::Order)) {
3047 // Ignore Order dependences between unconditional direct branches
3048 // and non-control-flow instructions
3051 else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
3052 (DepType != SDep::Output)) {
3053 // Ignore all dependences for jumps except for true and output
3058 // Ignore output dependences due to superregs. We can
3059 // write to two different subregisters of R1:0 for instance
3060 // in the same cycle
3065 // If neither I nor J defines DepReg, then this is a
3066 // superfluous output dependence. The dependence must be of the
3070 // and there is an output dependence between the two instructions
3073 // We want to ignore these dependences.
3074 // Ideally, the dependence constructor should annotate such
3075 // dependences. We can then avoid this relatively expensive check.
3077 else if (DepType == SDep::Output) {
3078 // DepReg is the register that's responsible for the dependence.
3079 unsigned DepReg = SUJ->Succs[i].getReg();
3081 // Check if I and J really defines DepReg.
3082 if (I->definesRegister(DepReg) ||
3083 J->definesRegister(DepReg)) {
3084 FoundSequentialDependence = true;
3089 // We ignore Order dependences for
3090 // 1. Two loads unless they are volatile.
3091 // 2. Two stores in V4 unless they are volatile.
3092 else if ((DepType == SDep::Order) &&
3093 !I->hasOrderedMemoryRef() &&
3094 !J->hasOrderedMemoryRef()) {
3095 if (QRI->Subtarget.hasV4TOps() &&
3096 // hexagonv4 allows dual store.
3097 MCIDI.mayStore() && MCIDJ.mayStore()) {
3100 // store followed by store-- not OK on V2
3101 // store followed by load -- not OK on all (OK if addresses
3103 // load followed by store -- OK on all
3104 // load followed by load -- OK on all
3105 else if ( !MCIDJ.mayStore()) {
3109 FoundSequentialDependence = true;
3114 // For V4, special case ALLOCFRAME. Even though there is dependency
3115 // between ALLOCAFRAME and subsequent store, allow it to be
3116 // packetized in a same packet. This implies that the store is using
3117 // caller's SP. Hense, offset needs to be updated accordingly.
3118 else if (DepType == SDep::Data
3119 && QRI->Subtarget.hasV4TOps()
3120 && J->getOpcode() == Hexagon::ALLOCFRAME
3121 && (I->getOpcode() == Hexagon::STrid
3122 || I->getOpcode() == Hexagon::STriw
3123 || I->getOpcode() == Hexagon::STrib)
3124 && I->getOperand(0).getReg() == QRI->getStackRegister()
3125 && QII->isValidOffset(I->getOpcode(),
3126 I->getOperand(1).getImm() -
3127 (FrameSize + HEXAGON_LRFP_SIZE)))
3129 GlueAllocframeStore = true;
3130 // Since this store is to be glued with allocframe in the same
3131 // packet, it will use SP of the previous stack frame, i.e
3132 // caller's SP. Therefore, we need to recalculate offset according
3134 I->getOperand(1).setImm(I->getOperand(1).getImm() -
3135 (FrameSize + HEXAGON_LRFP_SIZE));
3139 // Skip over anti-dependences. Two instructions that are
3140 // anti-dependent can share a packet
3142 else if (DepType != SDep::Anti) {
3143 FoundSequentialDependence = true;
3148 if (FoundSequentialDependence) {
3157 // isLegalToPruneDependencies
3158 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
3159 MachineInstr *I = SUI->getInstr();
3160 assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
3162 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3166 // Check if the instruction was promoted to a dot-new. If so, demote it
3167 // back into a dot-old.
3168 if (PromotedToDotNew) {
3172 // Check if the instruction (must be a store) was glued with an Allocframe
3173 // instruction. If so, restore its offset to its original value, i.e. use
3174 // curent SP instead of caller's SP.
3175 if (GlueAllocframeStore) {
3176 I->getOperand(1).setImm(I->getOperand(1).getImm() +
3177 FrameSize + HEXAGON_LRFP_SIZE);
3185 MachineBasicBlock::iterator
3186 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
3188 MachineBasicBlock::iterator MII = MI;
3189 MachineBasicBlock *MBB = MI->getParent();
3191 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3193 if (GlueToNewValueJump) {
3196 MachineInstr *nvjMI = MII;
3197 assert(ResourceTracker->canReserveResources(MI));
3198 ResourceTracker->reserveResources(MI);
3199 if (QII->isExtended(MI) &&
3200 !tryAllocateResourcesForConstExt(MI)) {
3202 ResourceTracker->reserveResources(MI);
3203 assert(canReserveResourcesForConstExt(MI) &&
3204 "Ensure that there is a slot");
3205 reserveResourcesForConstExt(MI);
3206 // Reserve resources for new value jump constant extender.
3207 assert(canReserveResourcesForConstExt(MI) &&
3208 "Ensure that there is a slot");
3209 reserveResourcesForConstExt(nvjMI);
3210 assert(ResourceTracker->canReserveResources(nvjMI) &&
3211 "Ensure that there is a slot");
3213 } else if ( // Extended instruction takes two slots in the packet.
3214 // Try reserve and allocate 4-byte in the current packet first.
3215 (QII->isExtended(nvjMI)
3216 && (!tryAllocateResourcesForConstExt(nvjMI)
3217 || !ResourceTracker->canReserveResources(nvjMI)))
3218 || // For non-extended instruction, no need to allocate extra 4 bytes.
3219 (!QII->isExtended(nvjMI) &&
3220 !ResourceTracker->canReserveResources(nvjMI)))
3223 // A new and empty packet starts.
3224 // We are sure that the resources requirements can be satisfied.
3225 // Therefore, do not need to call "canReserveResources" anymore.
3226 ResourceTracker->reserveResources(MI);
3227 if (QII->isExtended(nvjMI))
3228 reserveResourcesForConstExt(nvjMI);
3230 // Here, we are sure that "reserveResources" would succeed.
3231 ResourceTracker->reserveResources(nvjMI);
3232 CurrentPacketMIs.push_back(MI);
3233 CurrentPacketMIs.push_back(nvjMI);
3235 if ( QII->isExtended(MI)
3236 && ( !tryAllocateResourcesForConstExt(MI)
3237 || !ResourceTracker->canReserveResources(MI)))
3240 // Check if the instruction was promoted to a dot-new. If so, demote it
3241 // back into a dot-old
3242 if (PromotedToDotNew) {
3245 reserveResourcesForConstExt(MI);
3247 // In case that "MI" is not an extended insn,
3248 // the resource availability has already been checked.
3249 ResourceTracker->reserveResources(MI);
3250 CurrentPacketMIs.push_back(MI);
3255 //===----------------------------------------------------------------------===//
3256 // Public Constructor Functions
3257 //===----------------------------------------------------------------------===//
3259 FunctionPass *llvm::createHexagonPacketizer() {
3260 return new HexagonPacketizer();