1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "packets"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/ScheduleDAG.h"
26 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
27 #include "llvm/CodeGen/LatencyPriorityQueue.h"
28 #include "llvm/CodeGen/SchedulerRegistry.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/Statistic.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/MC/MCInstrItineraries.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
45 #include "HexagonTargetMachine.h"
46 #include "HexagonRegisterInfo.h"
47 #include "HexagonSubtarget.h"
48 #include "HexagonMachineFunctionInfo.h"
55 class HexagonPacketizer : public MachineFunctionPass {
59 HexagonPacketizer() : MachineFunctionPass(ID) {}
61 void getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addRequired<MachineDominatorTree>();
64 AU.addPreserved<MachineDominatorTree>();
65 AU.addRequired<MachineLoopInfo>();
66 AU.addPreserved<MachineLoopInfo>();
67 MachineFunctionPass::getAnalysisUsage(AU);
70 const char *getPassName() const {
71 return "Hexagon Packetizer";
74 bool runOnMachineFunction(MachineFunction &Fn);
76 char HexagonPacketizer::ID = 0;
78 class HexagonPacketizerList : public VLIWPacketizerList {
82 // Has the instruction been promoted to a dot-new instruction.
83 bool PromotedToDotNew;
85 // Has the instruction been glued to allocframe.
86 bool GlueAllocframeStore;
88 // Has the feeder instruction been glued to new value jump.
89 bool GlueToNewValueJump;
91 // Check if there is a dependence between some instruction already in this
92 // packet and this instruction.
95 // Only check for dependence if there are resources available to
96 // schedule this instruction.
97 bool FoundSequentialDependence;
101 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
102 MachineDominatorTree &MDT);
104 // initPacketizerState - initialize some internal flags.
105 void initPacketizerState();
107 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
108 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
110 // isSoloInstruction - return true if instruction MI can not be packetized
111 // with any other instruction, which means that MI itself is a packet.
112 bool isSoloInstruction(MachineInstr *MI);
114 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
116 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
118 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
120 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
122 MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
124 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
125 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
126 MachineBasicBlock::iterator &MII,
127 const TargetRegisterClass* RC);
128 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
130 std::map <MachineInstr*, SUnit*> MIToSUnit,
131 MachineBasicBlock::iterator &MII,
132 const TargetRegisterClass* RC);
133 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
135 std::map <MachineInstr*, SUnit*> MIToSUnit,
136 MachineBasicBlock::iterator &MII);
137 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
139 std::map <MachineInstr*, SUnit*> MIToSUnit);
140 bool DemoteToDotOld(MachineInstr* MI);
141 bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
142 std::map <MachineInstr*, SUnit*> MIToSUnit);
143 bool RestrictingDepExistInPacket(MachineInstr*,
144 unsigned, std::map <MachineInstr*, SUnit*>);
145 bool isNewifiable(MachineInstr* MI);
146 bool isCondInst(MachineInstr* MI);
147 bool IsNewifyStore (MachineInstr* MI);
148 bool tryAllocateResourcesForConstExt(MachineInstr* MI);
149 bool canReserveResourcesForConstExt(MachineInstr *MI);
150 void reserveResourcesForConstExt(MachineInstr* MI);
151 bool isNewValueInst(MachineInstr* MI);
155 // HexagonPacketizerList Ctor.
156 HexagonPacketizerList::HexagonPacketizerList(
157 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
158 : VLIWPacketizerList(MF, MLI, MDT, true){
161 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
162 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
163 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
164 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
166 // Instantiate the packetizer.
167 HexagonPacketizerList Packetizer(Fn, MLI, MDT);
169 // DFA state table should not be empty.
170 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
173 // Loop over all basic blocks and remove KILL pseudo-instructions
174 // These instructions confuse the dependence analysis. Consider:
176 // R0 = KILL R0, D0 (Insn 1)
178 // Here, Insn 1 will result in the dependence graph not emitting an output
179 // dependence between Insn 0 and Insn 2. This can lead to incorrect
182 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
183 MBB != MBBe; ++MBB) {
184 MachineBasicBlock::iterator End = MBB->end();
185 MachineBasicBlock::iterator MI = MBB->begin();
188 MachineBasicBlock::iterator DeleteMI = MI;
190 MBB->erase(DeleteMI);
198 // Loop over all of the basic blocks.
199 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
200 MBB != MBBe; ++MBB) {
201 // Find scheduling regions and schedule / packetize each region.
202 unsigned RemainingCount = MBB->size();
203 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
204 RegionEnd != MBB->begin();) {
205 // The next region starts above the previous region. Look backward in the
206 // instruction stream until we find the nearest boundary.
207 MachineBasicBlock::iterator I = RegionEnd;
208 for(;I != MBB->begin(); --I, --RemainingCount) {
209 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
214 // Skip empty scheduling regions.
215 if (I == RegionEnd) {
216 RegionEnd = llvm::prior(RegionEnd);
220 // Skip regions with one instruction.
221 if (I == llvm::prior(RegionEnd)) {
222 RegionEnd = llvm::prior(RegionEnd);
226 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
235 static bool IsIndirectCall(MachineInstr* MI) {
236 return ((MI->getOpcode() == Hexagon::CALLR) ||
237 (MI->getOpcode() == Hexagon::CALLRv3));
240 // Reserve resources for constant extender. Trigure an assertion if
242 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
243 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
244 MachineFunction *MF = MI->getParent()->getParent();
245 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
248 if (ResourceTracker->canReserveResources(PseudoMI)) {
249 ResourceTracker->reserveResources(PseudoMI);
250 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
252 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
253 llvm_unreachable("can not reserve resources for constant extender.");
258 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
259 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
260 assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
261 "Should only be called for constant extended instructions");
262 MachineFunction *MF = MI->getParent()->getParent();
263 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
265 bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
266 MF->DeleteMachineInstr(PseudoMI);
270 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
271 // true, otherwise, return false.
272 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
273 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
274 MachineFunction *MF = MI->getParent()->getParent();
275 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
278 if (ResourceTracker->canReserveResources(PseudoMI)) {
279 ResourceTracker->reserveResources(PseudoMI);
280 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
283 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
289 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
293 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
294 const HexagonRegisterInfo* QRI =
295 (const HexagonRegisterInfo *) TM.getRegisterInfo();
297 // Check for lr dependence
298 if (DepReg == QRI->getRARegister()) {
302 if (QII->isDeallocRet(MI)) {
303 if (DepReg == QRI->getFrameRegister() ||
304 DepReg == QRI->getStackRegister())
308 // Check if this is a predicate dependence
309 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
310 if (RC == &Hexagon::PredRegsRegClass) {
315 // Lastly check for an operand used in an indirect call
316 // If we had an attribute for checking if an instruction is an indirect call,
317 // then we could have avoided this relatively brittle implementation of
320 // Assumes that the first operand of the CALLr is the function address
322 if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
323 MachineOperand MO = MI->getOperand(0);
324 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
332 static bool IsRegDependence(const SDep::Kind DepType) {
333 return (DepType == SDep::Data || DepType == SDep::Anti ||
334 DepType == SDep::Output);
337 static bool IsDirectJump(MachineInstr* MI) {
338 return (MI->getOpcode() == Hexagon::JMP);
341 static bool IsSchedBarrier(MachineInstr* MI) {
342 switch (MI->getOpcode()) {
343 case Hexagon::BARRIER:
349 static bool IsControlFlow(MachineInstr* MI) {
350 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
353 // Function returns true if an instruction can be promoted to the new-value
354 // store. It will always return false for v2 and v3.
355 // It lists all the conditional and unconditional stores that can be promoted
356 // to the new-value stores.
358 bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
359 const HexagonRegisterInfo* QRI =
360 (const HexagonRegisterInfo *) TM.getRegisterInfo();
361 switch (MI->getOpcode())
365 case Hexagon::STrib_indexed:
366 case Hexagon::STrib_indexed_shl_V4:
367 case Hexagon::STrib_shl_V4:
368 case Hexagon::STb_GP_V4:
369 case Hexagon::POST_STbri:
370 case Hexagon::STrib_cPt:
371 case Hexagon::STrib_cdnPt_V4:
372 case Hexagon::STrib_cNotPt:
373 case Hexagon::STrib_cdnNotPt_V4:
374 case Hexagon::STrib_indexed_cPt:
375 case Hexagon::STrib_indexed_cdnPt_V4:
376 case Hexagon::STrib_indexed_cNotPt:
377 case Hexagon::STrib_indexed_cdnNotPt_V4:
378 case Hexagon::STrib_indexed_shl_cPt_V4:
379 case Hexagon::STrib_indexed_shl_cdnPt_V4:
380 case Hexagon::STrib_indexed_shl_cNotPt_V4:
381 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
382 case Hexagon::POST_STbri_cPt:
383 case Hexagon::POST_STbri_cdnPt_V4:
384 case Hexagon::POST_STbri_cNotPt:
385 case Hexagon::POST_STbri_cdnNotPt_V4:
386 case Hexagon::STb_GP_cPt_V4:
387 case Hexagon::STb_GP_cNotPt_V4:
388 case Hexagon::STb_GP_cdnPt_V4:
389 case Hexagon::STb_GP_cdnNotPt_V4:
393 case Hexagon::STrih_indexed:
394 case Hexagon::STrih_indexed_shl_V4:
395 case Hexagon::STrih_shl_V4:
396 case Hexagon::STh_GP_V4:
397 case Hexagon::POST_SThri:
398 case Hexagon::STrih_cPt:
399 case Hexagon::STrih_cdnPt_V4:
400 case Hexagon::STrih_cNotPt:
401 case Hexagon::STrih_cdnNotPt_V4:
402 case Hexagon::STrih_indexed_cPt:
403 case Hexagon::STrih_indexed_cdnPt_V4:
404 case Hexagon::STrih_indexed_cNotPt:
405 case Hexagon::STrih_indexed_cdnNotPt_V4:
406 case Hexagon::STrih_indexed_shl_cPt_V4:
407 case Hexagon::STrih_indexed_shl_cdnPt_V4:
408 case Hexagon::STrih_indexed_shl_cNotPt_V4:
409 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
410 case Hexagon::POST_SThri_cPt:
411 case Hexagon::POST_SThri_cdnPt_V4:
412 case Hexagon::POST_SThri_cNotPt:
413 case Hexagon::POST_SThri_cdnNotPt_V4:
414 case Hexagon::STh_GP_cPt_V4:
415 case Hexagon::STh_GP_cNotPt_V4:
416 case Hexagon::STh_GP_cdnPt_V4:
417 case Hexagon::STh_GP_cdnNotPt_V4:
421 case Hexagon::STriw_indexed:
422 case Hexagon::STriw_indexed_shl_V4:
423 case Hexagon::STriw_shl_V4:
424 case Hexagon::STw_GP_V4:
425 case Hexagon::POST_STwri:
426 case Hexagon::STriw_cPt:
427 case Hexagon::STriw_cdnPt_V4:
428 case Hexagon::STriw_cNotPt:
429 case Hexagon::STriw_cdnNotPt_V4:
430 case Hexagon::STriw_indexed_cPt:
431 case Hexagon::STriw_indexed_cdnPt_V4:
432 case Hexagon::STriw_indexed_cNotPt:
433 case Hexagon::STriw_indexed_cdnNotPt_V4:
434 case Hexagon::STriw_indexed_shl_cPt_V4:
435 case Hexagon::STriw_indexed_shl_cdnPt_V4:
436 case Hexagon::STriw_indexed_shl_cNotPt_V4:
437 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
438 case Hexagon::POST_STwri_cPt:
439 case Hexagon::POST_STwri_cdnPt_V4:
440 case Hexagon::POST_STwri_cNotPt:
441 case Hexagon::POST_STwri_cdnNotPt_V4:
442 case Hexagon::STw_GP_cPt_V4:
443 case Hexagon::STw_GP_cNotPt_V4:
444 case Hexagon::STw_GP_cdnPt_V4:
445 case Hexagon::STw_GP_cdnNotPt_V4:
446 return QRI->Subtarget.hasV4TOps();
451 static bool IsLoopN(MachineInstr *MI) {
452 return (MI->getOpcode() == Hexagon::LOOP0_i ||
453 MI->getOpcode() == Hexagon::LOOP0_r);
456 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
457 /// callee-saved register.
458 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
459 const TargetRegisterInfo *TRI) {
460 for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
461 unsigned CalleeSavedReg = *CSR;
462 if (MI->modifiesRegister(CalleeSavedReg, TRI))
468 // Return the new value instruction for a given store.
469 static int GetDotNewOp(const int opc) {
471 default: llvm_unreachable("Unknown .new type");
472 // store new value byte
474 return Hexagon::STrib_nv_V4;
476 case Hexagon::STrib_indexed:
477 return Hexagon::STrib_indexed_nv_V4;
479 case Hexagon::STrib_indexed_shl_V4:
480 return Hexagon::STrib_indexed_shl_nv_V4;
482 case Hexagon::STrib_shl_V4:
483 return Hexagon::STrib_shl_nv_V4;
485 case Hexagon::STb_GP_V4:
486 return Hexagon::STb_GP_nv_V4;
488 case Hexagon::POST_STbri:
489 return Hexagon::POST_STbri_nv_V4;
491 case Hexagon::STrib_cPt:
492 return Hexagon::STrib_cPt_nv_V4;
494 case Hexagon::STrib_cdnPt_V4:
495 return Hexagon::STrib_cdnPt_nv_V4;
497 case Hexagon::STrib_cNotPt:
498 return Hexagon::STrib_cNotPt_nv_V4;
500 case Hexagon::STrib_cdnNotPt_V4:
501 return Hexagon::STrib_cdnNotPt_nv_V4;
503 case Hexagon::STrib_indexed_cPt:
504 return Hexagon::STrib_indexed_cPt_nv_V4;
506 case Hexagon::STrib_indexed_cdnPt_V4:
507 return Hexagon::STrib_indexed_cdnPt_nv_V4;
509 case Hexagon::STrib_indexed_cNotPt:
510 return Hexagon::STrib_indexed_cNotPt_nv_V4;
512 case Hexagon::STrib_indexed_cdnNotPt_V4:
513 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
515 case Hexagon::STrib_indexed_shl_cPt_V4:
516 return Hexagon::STrib_indexed_shl_cPt_nv_V4;
518 case Hexagon::STrib_indexed_shl_cdnPt_V4:
519 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
521 case Hexagon::STrib_indexed_shl_cNotPt_V4:
522 return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
524 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
525 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
527 case Hexagon::POST_STbri_cPt:
528 return Hexagon::POST_STbri_cPt_nv_V4;
530 case Hexagon::POST_STbri_cdnPt_V4:
531 return Hexagon::POST_STbri_cdnPt_nv_V4;
533 case Hexagon::POST_STbri_cNotPt:
534 return Hexagon::POST_STbri_cNotPt_nv_V4;
536 case Hexagon::POST_STbri_cdnNotPt_V4:
537 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
539 case Hexagon::STb_GP_cPt_V4:
540 return Hexagon::STb_GP_cPt_nv_V4;
542 case Hexagon::STb_GP_cNotPt_V4:
543 return Hexagon::STb_GP_cNotPt_nv_V4;
545 case Hexagon::STb_GP_cdnPt_V4:
546 return Hexagon::STb_GP_cdnPt_nv_V4;
548 case Hexagon::STb_GP_cdnNotPt_V4:
549 return Hexagon::STb_GP_cdnNotPt_nv_V4;
551 // store new value halfword
553 return Hexagon::STrih_nv_V4;
555 case Hexagon::STrih_indexed:
556 return Hexagon::STrih_indexed_nv_V4;
558 case Hexagon::STrih_indexed_shl_V4:
559 return Hexagon::STrih_indexed_shl_nv_V4;
561 case Hexagon::STrih_shl_V4:
562 return Hexagon::STrih_shl_nv_V4;
564 case Hexagon::STh_GP_V4:
565 return Hexagon::STh_GP_nv_V4;
567 case Hexagon::POST_SThri:
568 return Hexagon::POST_SThri_nv_V4;
570 case Hexagon::STrih_cPt:
571 return Hexagon::STrih_cPt_nv_V4;
573 case Hexagon::STrih_cdnPt_V4:
574 return Hexagon::STrih_cdnPt_nv_V4;
576 case Hexagon::STrih_cNotPt:
577 return Hexagon::STrih_cNotPt_nv_V4;
579 case Hexagon::STrih_cdnNotPt_V4:
580 return Hexagon::STrih_cdnNotPt_nv_V4;
582 case Hexagon::STrih_indexed_cPt:
583 return Hexagon::STrih_indexed_cPt_nv_V4;
585 case Hexagon::STrih_indexed_cdnPt_V4:
586 return Hexagon::STrih_indexed_cdnPt_nv_V4;
588 case Hexagon::STrih_indexed_cNotPt:
589 return Hexagon::STrih_indexed_cNotPt_nv_V4;
591 case Hexagon::STrih_indexed_cdnNotPt_V4:
592 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
594 case Hexagon::STrih_indexed_shl_cPt_V4:
595 return Hexagon::STrih_indexed_shl_cPt_nv_V4;
597 case Hexagon::STrih_indexed_shl_cdnPt_V4:
598 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
600 case Hexagon::STrih_indexed_shl_cNotPt_V4:
601 return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
603 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
604 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
606 case Hexagon::POST_SThri_cPt:
607 return Hexagon::POST_SThri_cPt_nv_V4;
609 case Hexagon::POST_SThri_cdnPt_V4:
610 return Hexagon::POST_SThri_cdnPt_nv_V4;
612 case Hexagon::POST_SThri_cNotPt:
613 return Hexagon::POST_SThri_cNotPt_nv_V4;
615 case Hexagon::POST_SThri_cdnNotPt_V4:
616 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
618 case Hexagon::STh_GP_cPt_V4:
619 return Hexagon::STh_GP_cPt_nv_V4;
621 case Hexagon::STh_GP_cNotPt_V4:
622 return Hexagon::STh_GP_cNotPt_nv_V4;
624 case Hexagon::STh_GP_cdnPt_V4:
625 return Hexagon::STh_GP_cdnPt_nv_V4;
627 case Hexagon::STh_GP_cdnNotPt_V4:
628 return Hexagon::STh_GP_cdnNotPt_nv_V4;
630 // store new value word
632 return Hexagon::STriw_nv_V4;
634 case Hexagon::STriw_indexed:
635 return Hexagon::STriw_indexed_nv_V4;
637 case Hexagon::STriw_indexed_shl_V4:
638 return Hexagon::STriw_indexed_shl_nv_V4;
640 case Hexagon::STriw_shl_V4:
641 return Hexagon::STriw_shl_nv_V4;
643 case Hexagon::STw_GP_V4:
644 return Hexagon::STw_GP_nv_V4;
646 case Hexagon::POST_STwri:
647 return Hexagon::POST_STwri_nv_V4;
649 case Hexagon::STriw_cPt:
650 return Hexagon::STriw_cPt_nv_V4;
652 case Hexagon::STriw_cdnPt_V4:
653 return Hexagon::STriw_cdnPt_nv_V4;
655 case Hexagon::STriw_cNotPt:
656 return Hexagon::STriw_cNotPt_nv_V4;
658 case Hexagon::STriw_cdnNotPt_V4:
659 return Hexagon::STriw_cdnNotPt_nv_V4;
661 case Hexagon::STriw_indexed_cPt:
662 return Hexagon::STriw_indexed_cPt_nv_V4;
664 case Hexagon::STriw_indexed_cdnPt_V4:
665 return Hexagon::STriw_indexed_cdnPt_nv_V4;
667 case Hexagon::STriw_indexed_cNotPt:
668 return Hexagon::STriw_indexed_cNotPt_nv_V4;
670 case Hexagon::STriw_indexed_cdnNotPt_V4:
671 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
673 case Hexagon::STriw_indexed_shl_cPt_V4:
674 return Hexagon::STriw_indexed_shl_cPt_nv_V4;
676 case Hexagon::STriw_indexed_shl_cdnPt_V4:
677 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
679 case Hexagon::STriw_indexed_shl_cNotPt_V4:
680 return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
682 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
683 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
685 case Hexagon::POST_STwri_cPt:
686 return Hexagon::POST_STwri_cPt_nv_V4;
688 case Hexagon::POST_STwri_cdnPt_V4:
689 return Hexagon::POST_STwri_cdnPt_nv_V4;
691 case Hexagon::POST_STwri_cNotPt:
692 return Hexagon::POST_STwri_cNotPt_nv_V4;
694 case Hexagon::POST_STwri_cdnNotPt_V4:
695 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
697 case Hexagon::STw_GP_cPt_V4:
698 return Hexagon::STw_GP_cPt_nv_V4;
700 case Hexagon::STw_GP_cNotPt_V4:
701 return Hexagon::STw_GP_cNotPt_nv_V4;
703 case Hexagon::STw_GP_cdnPt_V4:
704 return Hexagon::STw_GP_cdnPt_nv_V4;
706 case Hexagon::STw_GP_cdnNotPt_V4:
707 return Hexagon::STw_GP_cdnNotPt_nv_V4;
712 // Return .new predicate version for an instruction
713 static int GetDotNewPredOp(const int opc) {
715 default: llvm_unreachable("Unknown .new type");
716 // Conditional stores
717 // Store byte conditionally
718 case Hexagon::STrib_cPt :
719 return Hexagon::STrib_cdnPt_V4;
721 case Hexagon::STrib_cNotPt :
722 return Hexagon::STrib_cdnNotPt_V4;
724 case Hexagon::STrib_indexed_cPt :
725 return Hexagon::STrib_indexed_cdnPt_V4;
727 case Hexagon::STrib_indexed_cNotPt :
728 return Hexagon::STrib_indexed_cdnNotPt_V4;
730 case Hexagon::STrib_imm_cPt_V4 :
731 return Hexagon::STrib_imm_cdnPt_V4;
733 case Hexagon::STrib_imm_cNotPt_V4 :
734 return Hexagon::STrib_imm_cdnNotPt_V4;
736 case Hexagon::POST_STbri_cPt :
737 return Hexagon::POST_STbri_cdnPt_V4;
739 case Hexagon::POST_STbri_cNotPt :
740 return Hexagon::POST_STbri_cdnNotPt_V4;
742 case Hexagon::STrib_indexed_shl_cPt_V4 :
743 return Hexagon::STrib_indexed_shl_cdnPt_V4;
745 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
746 return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
748 case Hexagon::STb_GP_cPt_V4 :
749 return Hexagon::STb_GP_cdnPt_V4;
751 case Hexagon::STb_GP_cNotPt_V4 :
752 return Hexagon::STb_GP_cdnNotPt_V4;
754 // Store doubleword conditionally
755 case Hexagon::STrid_cPt :
756 return Hexagon::STrid_cdnPt_V4;
758 case Hexagon::STrid_cNotPt :
759 return Hexagon::STrid_cdnNotPt_V4;
761 case Hexagon::STrid_indexed_cPt :
762 return Hexagon::STrid_indexed_cdnPt_V4;
764 case Hexagon::STrid_indexed_cNotPt :
765 return Hexagon::STrid_indexed_cdnNotPt_V4;
767 case Hexagon::STrid_indexed_shl_cPt_V4 :
768 return Hexagon::STrid_indexed_shl_cdnPt_V4;
770 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
771 return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
773 case Hexagon::POST_STdri_cPt :
774 return Hexagon::POST_STdri_cdnPt_V4;
776 case Hexagon::POST_STdri_cNotPt :
777 return Hexagon::POST_STdri_cdnNotPt_V4;
779 case Hexagon::STd_GP_cPt_V4 :
780 return Hexagon::STd_GP_cdnPt_V4;
782 case Hexagon::STd_GP_cNotPt_V4 :
783 return Hexagon::STd_GP_cdnNotPt_V4;
785 // Store halfword conditionally
786 case Hexagon::STrih_cPt :
787 return Hexagon::STrih_cdnPt_V4;
789 case Hexagon::STrih_cNotPt :
790 return Hexagon::STrih_cdnNotPt_V4;
792 case Hexagon::STrih_indexed_cPt :
793 return Hexagon::STrih_indexed_cdnPt_V4;
795 case Hexagon::STrih_indexed_cNotPt :
796 return Hexagon::STrih_indexed_cdnNotPt_V4;
798 case Hexagon::STrih_imm_cPt_V4 :
799 return Hexagon::STrih_imm_cdnPt_V4;
801 case Hexagon::STrih_imm_cNotPt_V4 :
802 return Hexagon::STrih_imm_cdnNotPt_V4;
804 case Hexagon::STrih_indexed_shl_cPt_V4 :
805 return Hexagon::STrih_indexed_shl_cdnPt_V4;
807 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
808 return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
810 case Hexagon::POST_SThri_cPt :
811 return Hexagon::POST_SThri_cdnPt_V4;
813 case Hexagon::POST_SThri_cNotPt :
814 return Hexagon::POST_SThri_cdnNotPt_V4;
816 case Hexagon::STh_GP_cPt_V4 :
817 return Hexagon::STh_GP_cdnPt_V4;
819 case Hexagon::STh_GP_cNotPt_V4 :
820 return Hexagon::STh_GP_cdnNotPt_V4;
822 // Store word conditionally
823 case Hexagon::STriw_cPt :
824 return Hexagon::STriw_cdnPt_V4;
826 case Hexagon::STriw_cNotPt :
827 return Hexagon::STriw_cdnNotPt_V4;
829 case Hexagon::STriw_indexed_cPt :
830 return Hexagon::STriw_indexed_cdnPt_V4;
832 case Hexagon::STriw_indexed_cNotPt :
833 return Hexagon::STriw_indexed_cdnNotPt_V4;
835 case Hexagon::STriw_imm_cPt_V4 :
836 return Hexagon::STriw_imm_cdnPt_V4;
838 case Hexagon::STriw_imm_cNotPt_V4 :
839 return Hexagon::STriw_imm_cdnNotPt_V4;
841 case Hexagon::STriw_indexed_shl_cPt_V4 :
842 return Hexagon::STriw_indexed_shl_cdnPt_V4;
844 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
845 return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
847 case Hexagon::POST_STwri_cPt :
848 return Hexagon::POST_STwri_cdnPt_V4;
850 case Hexagon::POST_STwri_cNotPt :
851 return Hexagon::POST_STwri_cdnNotPt_V4;
853 case Hexagon::STw_GP_cPt_V4 :
854 return Hexagon::STw_GP_cdnPt_V4;
856 case Hexagon::STw_GP_cNotPt_V4 :
857 return Hexagon::STw_GP_cdnNotPt_V4;
861 return Hexagon::JMP_cdnPt;
863 case Hexagon::JMP_cNot:
864 return Hexagon::JMP_cdnNotPt;
866 case Hexagon::JMPR_cPt:
867 return Hexagon::JMPR_cdnPt_V3;
869 case Hexagon::JMPR_cNotPt:
870 return Hexagon::JMPR_cdnNotPt_V3;
872 // Conditional Transfers
873 case Hexagon::TFR_cPt:
874 return Hexagon::TFR_cdnPt;
876 case Hexagon::TFR_cNotPt:
877 return Hexagon::TFR_cdnNotPt;
879 case Hexagon::TFRI_cPt:
880 return Hexagon::TFRI_cdnPt;
882 case Hexagon::TFRI_cNotPt:
883 return Hexagon::TFRI_cdnNotPt;
886 case Hexagon::LDrid_cPt :
887 return Hexagon::LDrid_cdnPt;
889 case Hexagon::LDrid_cNotPt :
890 return Hexagon::LDrid_cdnNotPt;
892 case Hexagon::LDrid_indexed_cPt :
893 return Hexagon::LDrid_indexed_cdnPt;
895 case Hexagon::LDrid_indexed_cNotPt :
896 return Hexagon::LDrid_indexed_cdnNotPt;
898 case Hexagon::POST_LDrid_cPt :
899 return Hexagon::POST_LDrid_cdnPt_V4;
901 case Hexagon::POST_LDrid_cNotPt :
902 return Hexagon::POST_LDrid_cdnNotPt_V4;
905 case Hexagon::LDriw_cPt :
906 return Hexagon::LDriw_cdnPt;
908 case Hexagon::LDriw_cNotPt :
909 return Hexagon::LDriw_cdnNotPt;
911 case Hexagon::LDriw_indexed_cPt :
912 return Hexagon::LDriw_indexed_cdnPt;
914 case Hexagon::LDriw_indexed_cNotPt :
915 return Hexagon::LDriw_indexed_cdnNotPt;
917 case Hexagon::POST_LDriw_cPt :
918 return Hexagon::POST_LDriw_cdnPt_V4;
920 case Hexagon::POST_LDriw_cNotPt :
921 return Hexagon::POST_LDriw_cdnNotPt_V4;
924 case Hexagon::LDrih_cPt :
925 return Hexagon::LDrih_cdnPt;
927 case Hexagon::LDrih_cNotPt :
928 return Hexagon::LDrih_cdnNotPt;
930 case Hexagon::LDrih_indexed_cPt :
931 return Hexagon::LDrih_indexed_cdnPt;
933 case Hexagon::LDrih_indexed_cNotPt :
934 return Hexagon::LDrih_indexed_cdnNotPt;
936 case Hexagon::POST_LDrih_cPt :
937 return Hexagon::POST_LDrih_cdnPt_V4;
939 case Hexagon::POST_LDrih_cNotPt :
940 return Hexagon::POST_LDrih_cdnNotPt_V4;
943 case Hexagon::LDrib_cPt :
944 return Hexagon::LDrib_cdnPt;
946 case Hexagon::LDrib_cNotPt :
947 return Hexagon::LDrib_cdnNotPt;
949 case Hexagon::LDrib_indexed_cPt :
950 return Hexagon::LDrib_indexed_cdnPt;
952 case Hexagon::LDrib_indexed_cNotPt :
953 return Hexagon::LDrib_indexed_cdnNotPt;
955 case Hexagon::POST_LDrib_cPt :
956 return Hexagon::POST_LDrib_cdnPt_V4;
958 case Hexagon::POST_LDrib_cNotPt :
959 return Hexagon::POST_LDrib_cdnNotPt_V4;
961 // Load unsigned halfword
962 case Hexagon::LDriuh_cPt :
963 return Hexagon::LDriuh_cdnPt;
965 case Hexagon::LDriuh_cNotPt :
966 return Hexagon::LDriuh_cdnNotPt;
968 case Hexagon::LDriuh_indexed_cPt :
969 return Hexagon::LDriuh_indexed_cdnPt;
971 case Hexagon::LDriuh_indexed_cNotPt :
972 return Hexagon::LDriuh_indexed_cdnNotPt;
974 case Hexagon::POST_LDriuh_cPt :
975 return Hexagon::POST_LDriuh_cdnPt_V4;
977 case Hexagon::POST_LDriuh_cNotPt :
978 return Hexagon::POST_LDriuh_cdnNotPt_V4;
980 // Load unsigned byte
981 case Hexagon::LDriub_cPt :
982 return Hexagon::LDriub_cdnPt;
984 case Hexagon::LDriub_cNotPt :
985 return Hexagon::LDriub_cdnNotPt;
987 case Hexagon::LDriub_indexed_cPt :
988 return Hexagon::LDriub_indexed_cdnPt;
990 case Hexagon::LDriub_indexed_cNotPt :
991 return Hexagon::LDriub_indexed_cdnNotPt;
993 case Hexagon::POST_LDriub_cPt :
994 return Hexagon::POST_LDriub_cdnPt_V4;
996 case Hexagon::POST_LDriub_cNotPt :
997 return Hexagon::POST_LDriub_cdnNotPt_V4;
999 // V4 indexed+scaled load
1001 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1002 return Hexagon::LDrid_indexed_shl_cdnPt_V4;
1004 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1005 return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
1007 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1008 return Hexagon::LDrib_indexed_shl_cdnPt_V4;
1010 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1011 return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
1013 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1014 return Hexagon::LDriub_indexed_shl_cdnPt_V4;
1016 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1017 return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
1019 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1020 return Hexagon::LDrih_indexed_shl_cdnPt_V4;
1022 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1023 return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
1025 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1026 return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
1028 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1029 return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
1031 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1032 return Hexagon::LDriw_indexed_shl_cdnPt_V4;
1034 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1035 return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
1037 // V4 global address load
1039 case Hexagon::LDd_GP_cPt_V4:
1040 return Hexagon::LDd_GP_cdnPt_V4;
1042 case Hexagon::LDd_GP_cNotPt_V4:
1043 return Hexagon::LDd_GP_cdnNotPt_V4;
1045 case Hexagon::LDb_GP_cPt_V4:
1046 return Hexagon::LDb_GP_cdnPt_V4;
1048 case Hexagon::LDb_GP_cNotPt_V4:
1049 return Hexagon::LDb_GP_cdnNotPt_V4;
1051 case Hexagon::LDub_GP_cPt_V4:
1052 return Hexagon::LDub_GP_cdnPt_V4;
1054 case Hexagon::LDub_GP_cNotPt_V4:
1055 return Hexagon::LDub_GP_cdnNotPt_V4;
1057 case Hexagon::LDh_GP_cPt_V4:
1058 return Hexagon::LDh_GP_cdnPt_V4;
1060 case Hexagon::LDh_GP_cNotPt_V4:
1061 return Hexagon::LDh_GP_cdnNotPt_V4;
1063 case Hexagon::LDuh_GP_cPt_V4:
1064 return Hexagon::LDuh_GP_cdnPt_V4;
1066 case Hexagon::LDuh_GP_cNotPt_V4:
1067 return Hexagon::LDuh_GP_cdnNotPt_V4;
1069 case Hexagon::LDw_GP_cPt_V4:
1070 return Hexagon::LDw_GP_cdnPt_V4;
1072 case Hexagon::LDw_GP_cNotPt_V4:
1073 return Hexagon::LDw_GP_cdnNotPt_V4;
1075 // Conditional store new-value byte
1076 case Hexagon::STrib_cPt_nv_V4 :
1077 return Hexagon::STrib_cdnPt_nv_V4;
1078 case Hexagon::STrib_cNotPt_nv_V4 :
1079 return Hexagon::STrib_cdnNotPt_nv_V4;
1081 case Hexagon::STrib_indexed_cPt_nv_V4 :
1082 return Hexagon::STrib_indexed_cdnPt_nv_V4;
1083 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1084 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
1086 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1087 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
1088 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1089 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
1091 case Hexagon::POST_STbri_cPt_nv_V4 :
1092 return Hexagon::POST_STbri_cdnPt_nv_V4;
1093 case Hexagon::POST_STbri_cNotPt_nv_V4 :
1094 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
1096 case Hexagon::STb_GP_cPt_nv_V4 :
1097 return Hexagon::STb_GP_cdnPt_nv_V4;
1099 case Hexagon::STb_GP_cNotPt_nv_V4 :
1100 return Hexagon::STb_GP_cdnNotPt_nv_V4;
1102 // Conditional store new-value halfword
1103 case Hexagon::STrih_cPt_nv_V4 :
1104 return Hexagon::STrih_cdnPt_nv_V4;
1105 case Hexagon::STrih_cNotPt_nv_V4 :
1106 return Hexagon::STrih_cdnNotPt_nv_V4;
1108 case Hexagon::STrih_indexed_cPt_nv_V4 :
1109 return Hexagon::STrih_indexed_cdnPt_nv_V4;
1110 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1111 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
1113 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1114 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
1115 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1116 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
1118 case Hexagon::POST_SThri_cPt_nv_V4 :
1119 return Hexagon::POST_SThri_cdnPt_nv_V4;
1120 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1121 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
1123 case Hexagon::STh_GP_cPt_nv_V4 :
1124 return Hexagon::STh_GP_cdnPt_nv_V4;
1126 case Hexagon::STh_GP_cNotPt_nv_V4 :
1127 return Hexagon::STh_GP_cdnNotPt_nv_V4;
1129 // Conditional store new-value word
1130 case Hexagon::STriw_cPt_nv_V4 :
1131 return Hexagon::STriw_cdnPt_nv_V4;
1132 case Hexagon::STriw_cNotPt_nv_V4 :
1133 return Hexagon::STriw_cdnNotPt_nv_V4;
1135 case Hexagon::STriw_indexed_cPt_nv_V4 :
1136 return Hexagon::STriw_indexed_cdnPt_nv_V4;
1137 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1138 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
1140 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1141 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
1142 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1143 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
1145 case Hexagon::POST_STwri_cPt_nv_V4 :
1146 return Hexagon::POST_STwri_cdnPt_nv_V4;
1147 case Hexagon::POST_STwri_cNotPt_nv_V4:
1148 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
1150 case Hexagon::STw_GP_cPt_nv_V4 :
1151 return Hexagon::STw_GP_cdnPt_nv_V4;
1153 case Hexagon::STw_GP_cNotPt_nv_V4 :
1154 return Hexagon::STw_GP_cdnNotPt_nv_V4;
1157 case Hexagon::ADD_ri_cPt :
1158 return Hexagon::ADD_ri_cdnPt;
1159 case Hexagon::ADD_ri_cNotPt :
1160 return Hexagon::ADD_ri_cdnNotPt;
1162 case Hexagon::ADD_rr_cPt :
1163 return Hexagon::ADD_rr_cdnPt;
1164 case Hexagon::ADD_rr_cNotPt :
1165 return Hexagon::ADD_rr_cdnNotPt;
1167 // Conditional logical Operations
1168 case Hexagon::XOR_rr_cPt :
1169 return Hexagon::XOR_rr_cdnPt;
1170 case Hexagon::XOR_rr_cNotPt :
1171 return Hexagon::XOR_rr_cdnNotPt;
1173 case Hexagon::AND_rr_cPt :
1174 return Hexagon::AND_rr_cdnPt;
1175 case Hexagon::AND_rr_cNotPt :
1176 return Hexagon::AND_rr_cdnNotPt;
1178 case Hexagon::OR_rr_cPt :
1179 return Hexagon::OR_rr_cdnPt;
1180 case Hexagon::OR_rr_cNotPt :
1181 return Hexagon::OR_rr_cdnNotPt;
1183 // Conditional Subtract
1184 case Hexagon::SUB_rr_cPt :
1185 return Hexagon::SUB_rr_cdnPt;
1186 case Hexagon::SUB_rr_cNotPt :
1187 return Hexagon::SUB_rr_cdnNotPt;
1189 // Conditional combine
1190 case Hexagon::COMBINE_rr_cPt :
1191 return Hexagon::COMBINE_rr_cdnPt;
1192 case Hexagon::COMBINE_rr_cNotPt :
1193 return Hexagon::COMBINE_rr_cdnNotPt;
1195 case Hexagon::ASLH_cPt_V4 :
1196 return Hexagon::ASLH_cdnPt_V4;
1197 case Hexagon::ASLH_cNotPt_V4 :
1198 return Hexagon::ASLH_cdnNotPt_V4;
1200 case Hexagon::ASRH_cPt_V4 :
1201 return Hexagon::ASRH_cdnPt_V4;
1202 case Hexagon::ASRH_cNotPt_V4 :
1203 return Hexagon::ASRH_cdnNotPt_V4;
1205 case Hexagon::SXTB_cPt_V4 :
1206 return Hexagon::SXTB_cdnPt_V4;
1207 case Hexagon::SXTB_cNotPt_V4 :
1208 return Hexagon::SXTB_cdnNotPt_V4;
1210 case Hexagon::SXTH_cPt_V4 :
1211 return Hexagon::SXTH_cdnPt_V4;
1212 case Hexagon::SXTH_cNotPt_V4 :
1213 return Hexagon::SXTH_cdnNotPt_V4;
1215 case Hexagon::ZXTB_cPt_V4 :
1216 return Hexagon::ZXTB_cdnPt_V4;
1217 case Hexagon::ZXTB_cNotPt_V4 :
1218 return Hexagon::ZXTB_cdnNotPt_V4;
1220 case Hexagon::ZXTH_cPt_V4 :
1221 return Hexagon::ZXTH_cdnPt_V4;
1222 case Hexagon::ZXTH_cNotPt_V4 :
1223 return Hexagon::ZXTH_cdnNotPt_V4;
1227 // Returns true if an instruction can be promoted to .new predicate
1228 // or new-value store.
1229 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
1230 if ( isCondInst(MI) || IsNewifyStore(MI))
1236 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
1237 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1238 const MCInstrDesc& TID = MI->getDesc();
1239 // bug 5670: until that is fixed,
1240 // this portion is disabled.
1241 if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
1242 || QII->isConditionalTransfer(MI)
1243 || QII->isConditionalALU32(MI)
1244 || QII->isConditionalLoad(MI)
1245 || QII->isConditionalStore(MI)) {
1252 // Promote an instructiont to its .new form.
1253 // At this time, we have already made a call to CanPromoteToDotNew
1254 // and made sure that it can *indeed* be promoted.
1255 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
1256 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
1257 const TargetRegisterClass* RC) {
1259 assert (DepType == SDep::Data);
1260 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1263 if (RC == &Hexagon::PredRegsRegClass)
1264 NewOpcode = GetDotNewPredOp(MI->getOpcode());
1266 NewOpcode = GetDotNewOp(MI->getOpcode());
1267 MI->setDesc(QII->get(NewOpcode));
1272 // Returns the most basic instruction for the .new predicated instructions and
1273 // new-value stores.
1274 // For example, all of the following instructions will be converted back to the
1275 // same instruction:
1276 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1277 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1278 // 3) if (p0.new) memw(R0+#0) = R1 --->
1280 // To understand the translation of instruction 1 to its original form, consider
1281 // a packet with 3 instructions.
1282 // { p0 = cmp.eq(R0,R1)
1283 // if (p0.new) R2 = add(R3, R4)
1284 // R5 = add (R3, R1)
1286 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
1288 // This instruction can be part of the previous packet only if both p0 and R2
1289 // are promoted to .new values. This promotion happens in steps, first
1290 // predicate register is promoted to .new and in the next iteration R2 is
1291 // promoted. Therefore, in case of dependence check failure (due to R5) during
1292 // next iteration, it should be converted back to its most basic form.
1294 static int GetDotOldOp(const int opc) {
1296 default: llvm_unreachable("Unknown .old type");
1297 case Hexagon::TFR_cdnPt:
1298 return Hexagon::TFR_cPt;
1300 case Hexagon::TFR_cdnNotPt:
1301 return Hexagon::TFR_cNotPt;
1303 case Hexagon::TFRI_cdnPt:
1304 return Hexagon::TFRI_cPt;
1306 case Hexagon::TFRI_cdnNotPt:
1307 return Hexagon::TFRI_cNotPt;
1309 case Hexagon::JMP_cdnPt:
1310 return Hexagon::JMP_c;
1312 case Hexagon::JMP_cdnNotPt:
1313 return Hexagon::JMP_cNot;
1315 case Hexagon::JMPR_cdnPt_V3:
1316 return Hexagon::JMPR_cPt;
1318 case Hexagon::JMPR_cdnNotPt_V3:
1319 return Hexagon::JMPR_cNotPt;
1323 case Hexagon::LDrid_cdnPt :
1324 return Hexagon::LDrid_cPt;
1326 case Hexagon::LDrid_cdnNotPt :
1327 return Hexagon::LDrid_cNotPt;
1329 case Hexagon::LDrid_indexed_cdnPt :
1330 return Hexagon::LDrid_indexed_cPt;
1332 case Hexagon::LDrid_indexed_cdnNotPt :
1333 return Hexagon::LDrid_indexed_cNotPt;
1335 case Hexagon::POST_LDrid_cdnPt_V4 :
1336 return Hexagon::POST_LDrid_cPt;
1338 case Hexagon::POST_LDrid_cdnNotPt_V4 :
1339 return Hexagon::POST_LDrid_cNotPt;
1343 case Hexagon::LDriw_cdnPt :
1344 return Hexagon::LDriw_cPt;
1346 case Hexagon::LDriw_cdnNotPt :
1347 return Hexagon::LDriw_cNotPt;
1349 case Hexagon::LDriw_indexed_cdnPt :
1350 return Hexagon::LDriw_indexed_cPt;
1352 case Hexagon::LDriw_indexed_cdnNotPt :
1353 return Hexagon::LDriw_indexed_cNotPt;
1355 case Hexagon::POST_LDriw_cdnPt_V4 :
1356 return Hexagon::POST_LDriw_cPt;
1358 case Hexagon::POST_LDriw_cdnNotPt_V4 :
1359 return Hexagon::POST_LDriw_cNotPt;
1363 case Hexagon::LDrih_cdnPt :
1364 return Hexagon::LDrih_cPt;
1366 case Hexagon::LDrih_cdnNotPt :
1367 return Hexagon::LDrih_cNotPt;
1369 case Hexagon::LDrih_indexed_cdnPt :
1370 return Hexagon::LDrih_indexed_cPt;
1372 case Hexagon::LDrih_indexed_cdnNotPt :
1373 return Hexagon::LDrih_indexed_cNotPt;
1375 case Hexagon::POST_LDrih_cdnPt_V4 :
1376 return Hexagon::POST_LDrih_cPt;
1378 case Hexagon::POST_LDrih_cdnNotPt_V4 :
1379 return Hexagon::POST_LDrih_cNotPt;
1383 case Hexagon::LDrib_cdnPt :
1384 return Hexagon::LDrib_cPt;
1386 case Hexagon::LDrib_cdnNotPt :
1387 return Hexagon::LDrib_cNotPt;
1389 case Hexagon::LDrib_indexed_cdnPt :
1390 return Hexagon::LDrib_indexed_cPt;
1392 case Hexagon::LDrib_indexed_cdnNotPt :
1393 return Hexagon::LDrib_indexed_cNotPt;
1395 case Hexagon::POST_LDrib_cdnPt_V4 :
1396 return Hexagon::POST_LDrib_cPt;
1398 case Hexagon::POST_LDrib_cdnNotPt_V4 :
1399 return Hexagon::POST_LDrib_cNotPt;
1401 // Load unsigned half
1403 case Hexagon::LDriuh_cdnPt :
1404 return Hexagon::LDriuh_cPt;
1406 case Hexagon::LDriuh_cdnNotPt :
1407 return Hexagon::LDriuh_cNotPt;
1409 case Hexagon::LDriuh_indexed_cdnPt :
1410 return Hexagon::LDriuh_indexed_cPt;
1412 case Hexagon::LDriuh_indexed_cdnNotPt :
1413 return Hexagon::LDriuh_indexed_cNotPt;
1415 case Hexagon::POST_LDriuh_cdnPt_V4 :
1416 return Hexagon::POST_LDriuh_cPt;
1418 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
1419 return Hexagon::POST_LDriuh_cNotPt;
1421 // Load unsigned byte
1422 case Hexagon::LDriub_cdnPt :
1423 return Hexagon::LDriub_cPt;
1425 case Hexagon::LDriub_cdnNotPt :
1426 return Hexagon::LDriub_cNotPt;
1428 case Hexagon::LDriub_indexed_cdnPt :
1429 return Hexagon::LDriub_indexed_cPt;
1431 case Hexagon::LDriub_indexed_cdnNotPt :
1432 return Hexagon::LDriub_indexed_cNotPt;
1434 case Hexagon::POST_LDriub_cdnPt_V4 :
1435 return Hexagon::POST_LDriub_cPt;
1437 case Hexagon::POST_LDriub_cdnNotPt_V4 :
1438 return Hexagon::POST_LDriub_cNotPt;
1440 // V4 indexed+scaled Load
1442 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1443 return Hexagon::LDrid_indexed_shl_cPt_V4;
1445 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
1446 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1448 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1449 return Hexagon::LDrib_indexed_shl_cPt_V4;
1451 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
1452 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1454 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1455 return Hexagon::LDriub_indexed_shl_cPt_V4;
1457 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
1458 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1460 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1461 return Hexagon::LDrih_indexed_shl_cPt_V4;
1463 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
1464 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1466 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1467 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1469 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
1470 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1472 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1473 return Hexagon::LDriw_indexed_shl_cPt_V4;
1475 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
1476 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1478 // V4 global address load
1480 case Hexagon::LDd_GP_cdnPt_V4:
1481 return Hexagon::LDd_GP_cPt_V4;
1483 case Hexagon::LDd_GP_cdnNotPt_V4:
1484 return Hexagon::LDd_GP_cNotPt_V4;
1486 case Hexagon::LDb_GP_cdnPt_V4:
1487 return Hexagon::LDb_GP_cPt_V4;
1489 case Hexagon::LDb_GP_cdnNotPt_V4:
1490 return Hexagon::LDb_GP_cNotPt_V4;
1492 case Hexagon::LDub_GP_cdnPt_V4:
1493 return Hexagon::LDub_GP_cPt_V4;
1495 case Hexagon::LDub_GP_cdnNotPt_V4:
1496 return Hexagon::LDub_GP_cNotPt_V4;
1498 case Hexagon::LDh_GP_cdnPt_V4:
1499 return Hexagon::LDh_GP_cPt_V4;
1501 case Hexagon::LDh_GP_cdnNotPt_V4:
1502 return Hexagon::LDh_GP_cNotPt_V4;
1504 case Hexagon::LDuh_GP_cdnPt_V4:
1505 return Hexagon::LDuh_GP_cPt_V4;
1507 case Hexagon::LDuh_GP_cdnNotPt_V4:
1508 return Hexagon::LDuh_GP_cNotPt_V4;
1510 case Hexagon::LDw_GP_cdnPt_V4:
1511 return Hexagon::LDw_GP_cPt_V4;
1513 case Hexagon::LDw_GP_cdnNotPt_V4:
1514 return Hexagon::LDw_GP_cNotPt_V4;
1518 case Hexagon::ADD_ri_cdnPt :
1519 return Hexagon::ADD_ri_cPt;
1520 case Hexagon::ADD_ri_cdnNotPt :
1521 return Hexagon::ADD_ri_cNotPt;
1523 case Hexagon::ADD_rr_cdnPt :
1524 return Hexagon::ADD_rr_cPt;
1525 case Hexagon::ADD_rr_cdnNotPt:
1526 return Hexagon::ADD_rr_cNotPt;
1528 // Conditional logical Operations
1530 case Hexagon::XOR_rr_cdnPt :
1531 return Hexagon::XOR_rr_cPt;
1532 case Hexagon::XOR_rr_cdnNotPt :
1533 return Hexagon::XOR_rr_cNotPt;
1535 case Hexagon::AND_rr_cdnPt :
1536 return Hexagon::AND_rr_cPt;
1537 case Hexagon::AND_rr_cdnNotPt :
1538 return Hexagon::AND_rr_cNotPt;
1540 case Hexagon::OR_rr_cdnPt :
1541 return Hexagon::OR_rr_cPt;
1542 case Hexagon::OR_rr_cdnNotPt :
1543 return Hexagon::OR_rr_cNotPt;
1545 // Conditional Subtract
1547 case Hexagon::SUB_rr_cdnPt :
1548 return Hexagon::SUB_rr_cPt;
1549 case Hexagon::SUB_rr_cdnNotPt :
1550 return Hexagon::SUB_rr_cNotPt;
1552 // Conditional combine
1554 case Hexagon::COMBINE_rr_cdnPt :
1555 return Hexagon::COMBINE_rr_cPt;
1556 case Hexagon::COMBINE_rr_cdnNotPt :
1557 return Hexagon::COMBINE_rr_cNotPt;
1559 // Conditional shift operations
1561 case Hexagon::ASLH_cdnPt_V4 :
1562 return Hexagon::ASLH_cPt_V4;
1563 case Hexagon::ASLH_cdnNotPt_V4 :
1564 return Hexagon::ASLH_cNotPt_V4;
1566 case Hexagon::ASRH_cdnPt_V4 :
1567 return Hexagon::ASRH_cPt_V4;
1568 case Hexagon::ASRH_cdnNotPt_V4 :
1569 return Hexagon::ASRH_cNotPt_V4;
1571 case Hexagon::SXTB_cdnPt_V4 :
1572 return Hexagon::SXTB_cPt_V4;
1573 case Hexagon::SXTB_cdnNotPt_V4 :
1574 return Hexagon::SXTB_cNotPt_V4;
1576 case Hexagon::SXTH_cdnPt_V4 :
1577 return Hexagon::SXTH_cPt_V4;
1578 case Hexagon::SXTH_cdnNotPt_V4 :
1579 return Hexagon::SXTH_cNotPt_V4;
1581 case Hexagon::ZXTB_cdnPt_V4 :
1582 return Hexagon::ZXTB_cPt_V4;
1583 case Hexagon::ZXTB_cdnNotPt_V4 :
1584 return Hexagon::ZXTB_cNotPt_V4;
1586 case Hexagon::ZXTH_cdnPt_V4 :
1587 return Hexagon::ZXTH_cPt_V4;
1588 case Hexagon::ZXTH_cdnNotPt_V4 :
1589 return Hexagon::ZXTH_cNotPt_V4;
1593 case Hexagon::STrib_imm_cdnPt_V4 :
1594 return Hexagon::STrib_imm_cPt_V4;
1596 case Hexagon::STrib_imm_cdnNotPt_V4 :
1597 return Hexagon::STrib_imm_cNotPt_V4;
1599 case Hexagon::STrib_cdnPt_nv_V4 :
1600 case Hexagon::STrib_cPt_nv_V4 :
1601 case Hexagon::STrib_cdnPt_V4 :
1602 return Hexagon::STrib_cPt;
1604 case Hexagon::STrib_cdnNotPt_nv_V4 :
1605 case Hexagon::STrib_cNotPt_nv_V4 :
1606 case Hexagon::STrib_cdnNotPt_V4 :
1607 return Hexagon::STrib_cNotPt;
1609 case Hexagon::STrib_indexed_cdnPt_V4 :
1610 case Hexagon::STrib_indexed_cPt_nv_V4 :
1611 case Hexagon::STrib_indexed_cdnPt_nv_V4 :
1612 return Hexagon::STrib_indexed_cPt;
1614 case Hexagon::STrib_indexed_cdnNotPt_V4 :
1615 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1616 case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
1617 return Hexagon::STrib_indexed_cNotPt;
1619 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1620 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1621 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1622 return Hexagon::STrib_indexed_shl_cPt_V4;
1624 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1625 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1626 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
1627 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1629 case Hexagon::POST_STbri_cdnPt_nv_V4 :
1630 case Hexagon::POST_STbri_cPt_nv_V4 :
1631 case Hexagon::POST_STbri_cdnPt_V4 :
1632 return Hexagon::POST_STbri_cPt;
1634 case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
1635 case Hexagon::POST_STbri_cNotPt_nv_V4:
1636 case Hexagon::POST_STbri_cdnNotPt_V4 :
1637 return Hexagon::POST_STbri_cNotPt;
1639 case Hexagon::STb_GP_cdnPt_nv_V4:
1640 case Hexagon::STb_GP_cdnPt_V4:
1641 case Hexagon::STb_GP_cPt_nv_V4:
1642 return Hexagon::STb_GP_cPt_V4;
1644 case Hexagon::STb_GP_cdnNotPt_nv_V4:
1645 case Hexagon::STb_GP_cdnNotPt_V4:
1646 case Hexagon::STb_GP_cNotPt_nv_V4:
1647 return Hexagon::STb_GP_cNotPt_V4;
1649 // Store new-value byte - unconditional
1650 case Hexagon::STrib_nv_V4:
1651 return Hexagon::STrib;
1653 case Hexagon::STrib_indexed_nv_V4:
1654 return Hexagon::STrib_indexed;
1656 case Hexagon::STrib_indexed_shl_nv_V4:
1657 return Hexagon::STrib_indexed_shl_V4;
1659 case Hexagon::STrib_shl_nv_V4:
1660 return Hexagon::STrib_shl_V4;
1662 case Hexagon::STb_GP_nv_V4:
1663 return Hexagon::STb_GP_V4;
1665 case Hexagon::POST_STbri_nv_V4:
1666 return Hexagon::POST_STbri;
1669 case Hexagon::STrih_imm_cdnPt_V4 :
1670 return Hexagon::STrih_imm_cPt_V4;
1672 case Hexagon::STrih_imm_cdnNotPt_V4 :
1673 return Hexagon::STrih_imm_cNotPt_V4;
1675 case Hexagon::STrih_cdnPt_nv_V4 :
1676 case Hexagon::STrih_cPt_nv_V4 :
1677 case Hexagon::STrih_cdnPt_V4 :
1678 return Hexagon::STrih_cPt;
1680 case Hexagon::STrih_cdnNotPt_nv_V4 :
1681 case Hexagon::STrih_cNotPt_nv_V4 :
1682 case Hexagon::STrih_cdnNotPt_V4 :
1683 return Hexagon::STrih_cNotPt;
1685 case Hexagon::STrih_indexed_cdnPt_nv_V4:
1686 case Hexagon::STrih_indexed_cPt_nv_V4 :
1687 case Hexagon::STrih_indexed_cdnPt_V4 :
1688 return Hexagon::STrih_indexed_cPt;
1690 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1691 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1692 case Hexagon::STrih_indexed_cdnNotPt_V4 :
1693 return Hexagon::STrih_indexed_cNotPt;
1695 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
1696 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1697 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1698 return Hexagon::STrih_indexed_shl_cPt_V4;
1700 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
1701 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1702 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
1703 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1705 case Hexagon::POST_SThri_cdnPt_nv_V4 :
1706 case Hexagon::POST_SThri_cPt_nv_V4 :
1707 case Hexagon::POST_SThri_cdnPt_V4 :
1708 return Hexagon::POST_SThri_cPt;
1710 case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
1711 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1712 case Hexagon::POST_SThri_cdnNotPt_V4 :
1713 return Hexagon::POST_SThri_cNotPt;
1715 case Hexagon::STh_GP_cdnPt_nv_V4:
1716 case Hexagon::STh_GP_cdnPt_V4:
1717 case Hexagon::STh_GP_cPt_nv_V4:
1718 return Hexagon::STh_GP_cPt_V4;
1720 case Hexagon::STh_GP_cdnNotPt_nv_V4:
1721 case Hexagon::STh_GP_cdnNotPt_V4:
1722 case Hexagon::STh_GP_cNotPt_nv_V4:
1723 return Hexagon::STh_GP_cNotPt_V4;
1725 // Store new-value halfword - unconditional
1727 case Hexagon::STrih_nv_V4:
1728 return Hexagon::STrih;
1730 case Hexagon::STrih_indexed_nv_V4:
1731 return Hexagon::STrih_indexed;
1733 case Hexagon::STrih_indexed_shl_nv_V4:
1734 return Hexagon::STrih_indexed_shl_V4;
1736 case Hexagon::STrih_shl_nv_V4:
1737 return Hexagon::STrih_shl_V4;
1739 case Hexagon::STh_GP_nv_V4:
1740 return Hexagon::STh_GP_V4;
1742 case Hexagon::POST_SThri_nv_V4:
1743 return Hexagon::POST_SThri;
1747 case Hexagon::STriw_imm_cdnPt_V4 :
1748 return Hexagon::STriw_imm_cPt_V4;
1750 case Hexagon::STriw_imm_cdnNotPt_V4 :
1751 return Hexagon::STriw_imm_cNotPt_V4;
1753 case Hexagon::STriw_cdnPt_nv_V4 :
1754 case Hexagon::STriw_cPt_nv_V4 :
1755 case Hexagon::STriw_cdnPt_V4 :
1756 return Hexagon::STriw_cPt;
1758 case Hexagon::STriw_cdnNotPt_nv_V4 :
1759 case Hexagon::STriw_cNotPt_nv_V4 :
1760 case Hexagon::STriw_cdnNotPt_V4 :
1761 return Hexagon::STriw_cNotPt;
1763 case Hexagon::STriw_indexed_cdnPt_nv_V4 :
1764 case Hexagon::STriw_indexed_cPt_nv_V4 :
1765 case Hexagon::STriw_indexed_cdnPt_V4 :
1766 return Hexagon::STriw_indexed_cPt;
1768 case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
1769 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1770 case Hexagon::STriw_indexed_cdnNotPt_V4 :
1771 return Hexagon::STriw_indexed_cNotPt;
1773 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
1774 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1775 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1776 return Hexagon::STriw_indexed_shl_cPt_V4;
1778 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
1779 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1780 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
1781 return Hexagon::STriw_indexed_shl_cNotPt_V4;
1783 case Hexagon::POST_STwri_cdnPt_nv_V4 :
1784 case Hexagon::POST_STwri_cPt_nv_V4 :
1785 case Hexagon::POST_STwri_cdnPt_V4 :
1786 return Hexagon::POST_STwri_cPt;
1788 case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
1789 case Hexagon::POST_STwri_cNotPt_nv_V4 :
1790 case Hexagon::POST_STwri_cdnNotPt_V4 :
1791 return Hexagon::POST_STwri_cNotPt;
1793 case Hexagon::STw_GP_cdnPt_nv_V4:
1794 case Hexagon::STw_GP_cdnPt_V4:
1795 case Hexagon::STw_GP_cPt_nv_V4:
1796 return Hexagon::STw_GP_cPt_V4;
1798 case Hexagon::STw_GP_cdnNotPt_nv_V4:
1799 case Hexagon::STw_GP_cdnNotPt_V4:
1800 case Hexagon::STw_GP_cNotPt_nv_V4:
1801 return Hexagon::STw_GP_cNotPt_V4;
1803 // Store new-value word - unconditional
1805 case Hexagon::STriw_nv_V4:
1806 return Hexagon::STriw;
1808 case Hexagon::STriw_indexed_nv_V4:
1809 return Hexagon::STriw_indexed;
1811 case Hexagon::STriw_indexed_shl_nv_V4:
1812 return Hexagon::STriw_indexed_shl_V4;
1814 case Hexagon::STriw_shl_nv_V4:
1815 return Hexagon::STriw_shl_V4;
1817 case Hexagon::STw_GP_nv_V4:
1818 return Hexagon::STw_GP_V4;
1820 case Hexagon::POST_STwri_nv_V4:
1821 return Hexagon::POST_STwri;
1825 case Hexagon::STrid_cdnPt_V4 :
1826 return Hexagon::STrid_cPt;
1828 case Hexagon::STrid_cdnNotPt_V4 :
1829 return Hexagon::STrid_cNotPt;
1831 case Hexagon::STrid_indexed_cdnPt_V4 :
1832 return Hexagon::STrid_indexed_cPt;
1834 case Hexagon::STrid_indexed_cdnNotPt_V4 :
1835 return Hexagon::STrid_indexed_cNotPt;
1837 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1838 return Hexagon::STrid_indexed_shl_cPt_V4;
1840 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
1841 return Hexagon::STrid_indexed_shl_cNotPt_V4;
1843 case Hexagon::POST_STdri_cdnPt_V4 :
1844 return Hexagon::POST_STdri_cPt;
1846 case Hexagon::POST_STdri_cdnNotPt_V4 :
1847 return Hexagon::POST_STdri_cNotPt;
1849 case Hexagon::STd_GP_cdnPt_V4 :
1850 return Hexagon::STd_GP_cPt_V4;
1852 case Hexagon::STd_GP_cdnNotPt_V4 :
1853 return Hexagon::STd_GP_cNotPt_V4;
1858 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
1859 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1860 int NewOpcode = GetDotOldOp(MI->getOpcode());
1861 MI->setDesc(QII->get(NewOpcode));
1865 // Returns true if an instruction is predicated on p0 and false if it's
1866 // predicated on !p0.
1868 static bool GetPredicateSense(MachineInstr* MI,
1869 const HexagonInstrInfo *QII) {
1871 switch (MI->getOpcode()) {
1872 default: llvm_unreachable("Unknown predicate sense of the instruction");
1873 case Hexagon::TFR_cPt:
1874 case Hexagon::TFR_cdnPt:
1875 case Hexagon::TFRI_cPt:
1876 case Hexagon::TFRI_cdnPt:
1877 case Hexagon::STrib_cPt :
1878 case Hexagon::STrib_cdnPt_V4 :
1879 case Hexagon::STrib_indexed_cPt :
1880 case Hexagon::STrib_indexed_cdnPt_V4 :
1881 case Hexagon::STrib_indexed_shl_cPt_V4 :
1882 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1883 case Hexagon::POST_STbri_cPt :
1884 case Hexagon::POST_STbri_cdnPt_V4 :
1885 case Hexagon::STrih_cPt :
1886 case Hexagon::STrih_cdnPt_V4 :
1887 case Hexagon::STrih_indexed_cPt :
1888 case Hexagon::STrih_indexed_cdnPt_V4 :
1889 case Hexagon::STrih_indexed_shl_cPt_V4 :
1890 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1891 case Hexagon::POST_SThri_cPt :
1892 case Hexagon::POST_SThri_cdnPt_V4 :
1893 case Hexagon::STriw_cPt :
1894 case Hexagon::STriw_cdnPt_V4 :
1895 case Hexagon::STriw_indexed_cPt :
1896 case Hexagon::STriw_indexed_cdnPt_V4 :
1897 case Hexagon::STriw_indexed_shl_cPt_V4 :
1898 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1899 case Hexagon::POST_STwri_cPt :
1900 case Hexagon::POST_STwri_cdnPt_V4 :
1901 case Hexagon::STrib_imm_cPt_V4 :
1902 case Hexagon::STrib_imm_cdnPt_V4 :
1903 case Hexagon::STrid_cPt :
1904 case Hexagon::STrid_cdnPt_V4 :
1905 case Hexagon::STrid_indexed_cPt :
1906 case Hexagon::STrid_indexed_cdnPt_V4 :
1907 case Hexagon::STrid_indexed_shl_cPt_V4 :
1908 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1909 case Hexagon::POST_STdri_cPt :
1910 case Hexagon::POST_STdri_cdnPt_V4 :
1911 case Hexagon::STrih_imm_cPt_V4 :
1912 case Hexagon::STrih_imm_cdnPt_V4 :
1913 case Hexagon::STriw_imm_cPt_V4 :
1914 case Hexagon::STriw_imm_cdnPt_V4 :
1915 case Hexagon::JMP_cdnPt :
1916 case Hexagon::LDrid_cPt :
1917 case Hexagon::LDrid_cdnPt :
1918 case Hexagon::LDrid_indexed_cPt :
1919 case Hexagon::LDrid_indexed_cdnPt :
1920 case Hexagon::POST_LDrid_cPt :
1921 case Hexagon::POST_LDrid_cdnPt_V4 :
1922 case Hexagon::LDriw_cPt :
1923 case Hexagon::LDriw_cdnPt :
1924 case Hexagon::LDriw_indexed_cPt :
1925 case Hexagon::LDriw_indexed_cdnPt :
1926 case Hexagon::POST_LDriw_cPt :
1927 case Hexagon::POST_LDriw_cdnPt_V4 :
1928 case Hexagon::LDrih_cPt :
1929 case Hexagon::LDrih_cdnPt :
1930 case Hexagon::LDrih_indexed_cPt :
1931 case Hexagon::LDrih_indexed_cdnPt :
1932 case Hexagon::POST_LDrih_cPt :
1933 case Hexagon::POST_LDrih_cdnPt_V4 :
1934 case Hexagon::LDrib_cPt :
1935 case Hexagon::LDrib_cdnPt :
1936 case Hexagon::LDrib_indexed_cPt :
1937 case Hexagon::LDrib_indexed_cdnPt :
1938 case Hexagon::POST_LDrib_cPt :
1939 case Hexagon::POST_LDrib_cdnPt_V4 :
1940 case Hexagon::LDriuh_cPt :
1941 case Hexagon::LDriuh_cdnPt :
1942 case Hexagon::LDriuh_indexed_cPt :
1943 case Hexagon::LDriuh_indexed_cdnPt :
1944 case Hexagon::POST_LDriuh_cPt :
1945 case Hexagon::POST_LDriuh_cdnPt_V4 :
1946 case Hexagon::LDriub_cPt :
1947 case Hexagon::LDriub_cdnPt :
1948 case Hexagon::LDriub_indexed_cPt :
1949 case Hexagon::LDriub_indexed_cdnPt :
1950 case Hexagon::POST_LDriub_cPt :
1951 case Hexagon::POST_LDriub_cdnPt_V4 :
1952 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1953 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1954 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1955 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1956 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1957 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1958 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1959 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1960 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1961 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1962 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1963 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1964 case Hexagon::ADD_ri_cPt :
1965 case Hexagon::ADD_ri_cdnPt :
1966 case Hexagon::ADD_rr_cPt :
1967 case Hexagon::ADD_rr_cdnPt :
1968 case Hexagon::XOR_rr_cPt :
1969 case Hexagon::XOR_rr_cdnPt :
1970 case Hexagon::AND_rr_cPt :
1971 case Hexagon::AND_rr_cdnPt :
1972 case Hexagon::OR_rr_cPt :
1973 case Hexagon::OR_rr_cdnPt :
1974 case Hexagon::SUB_rr_cPt :
1975 case Hexagon::SUB_rr_cdnPt :
1976 case Hexagon::COMBINE_rr_cPt :
1977 case Hexagon::COMBINE_rr_cdnPt :
1978 case Hexagon::ASLH_cPt_V4 :
1979 case Hexagon::ASLH_cdnPt_V4 :
1980 case Hexagon::ASRH_cPt_V4 :
1981 case Hexagon::ASRH_cdnPt_V4 :
1982 case Hexagon::SXTB_cPt_V4 :
1983 case Hexagon::SXTB_cdnPt_V4 :
1984 case Hexagon::SXTH_cPt_V4 :
1985 case Hexagon::SXTH_cdnPt_V4 :
1986 case Hexagon::ZXTB_cPt_V4 :
1987 case Hexagon::ZXTB_cdnPt_V4 :
1988 case Hexagon::ZXTH_cPt_V4 :
1989 case Hexagon::ZXTH_cdnPt_V4 :
1990 case Hexagon::LDd_GP_cPt_V4 :
1991 case Hexagon::LDb_GP_cPt_V4 :
1992 case Hexagon::LDub_GP_cPt_V4 :
1993 case Hexagon::LDh_GP_cPt_V4 :
1994 case Hexagon::LDuh_GP_cPt_V4 :
1995 case Hexagon::LDw_GP_cPt_V4 :
1996 case Hexagon::STd_GP_cPt_V4 :
1997 case Hexagon::STb_GP_cPt_V4 :
1998 case Hexagon::STh_GP_cPt_V4 :
1999 case Hexagon::STw_GP_cPt_V4 :
2000 case Hexagon::LDd_GP_cdnPt_V4 :
2001 case Hexagon::LDb_GP_cdnPt_V4 :
2002 case Hexagon::LDub_GP_cdnPt_V4 :
2003 case Hexagon::LDh_GP_cdnPt_V4 :
2004 case Hexagon::LDuh_GP_cdnPt_V4 :
2005 case Hexagon::LDw_GP_cdnPt_V4 :
2006 case Hexagon::STd_GP_cdnPt_V4 :
2007 case Hexagon::STb_GP_cdnPt_V4 :
2008 case Hexagon::STh_GP_cdnPt_V4 :
2009 case Hexagon::STw_GP_cdnPt_V4 :
2012 case Hexagon::TFR_cNotPt:
2013 case Hexagon::TFR_cdnNotPt:
2014 case Hexagon::TFRI_cNotPt:
2015 case Hexagon::TFRI_cdnNotPt:
2016 case Hexagon::STrib_cNotPt :
2017 case Hexagon::STrib_cdnNotPt_V4 :
2018 case Hexagon::STrib_indexed_cNotPt :
2019 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2020 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2021 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2022 case Hexagon::POST_STbri_cNotPt :
2023 case Hexagon::POST_STbri_cdnNotPt_V4 :
2024 case Hexagon::STrih_cNotPt :
2025 case Hexagon::STrih_cdnNotPt_V4 :
2026 case Hexagon::STrih_indexed_cNotPt :
2027 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2028 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2029 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2030 case Hexagon::POST_SThri_cNotPt :
2031 case Hexagon::POST_SThri_cdnNotPt_V4 :
2032 case Hexagon::STriw_cNotPt :
2033 case Hexagon::STriw_cdnNotPt_V4 :
2034 case Hexagon::STriw_indexed_cNotPt :
2035 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2036 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2037 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2038 case Hexagon::POST_STwri_cNotPt :
2039 case Hexagon::POST_STwri_cdnNotPt_V4 :
2040 case Hexagon::STrib_imm_cNotPt_V4 :
2041 case Hexagon::STrib_imm_cdnNotPt_V4 :
2042 case Hexagon::STrid_cNotPt :
2043 case Hexagon::STrid_cdnNotPt_V4 :
2044 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2045 case Hexagon::STrid_indexed_cNotPt :
2046 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
2047 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2048 case Hexagon::POST_STdri_cNotPt :
2049 case Hexagon::POST_STdri_cdnNotPt_V4 :
2050 case Hexagon::STrih_imm_cNotPt_V4 :
2051 case Hexagon::STrih_imm_cdnNotPt_V4 :
2052 case Hexagon::STriw_imm_cNotPt_V4 :
2053 case Hexagon::STriw_imm_cdnNotPt_V4 :
2054 case Hexagon::JMP_cdnNotPt :
2055 case Hexagon::LDrid_cNotPt :
2056 case Hexagon::LDrid_cdnNotPt :
2057 case Hexagon::LDrid_indexed_cNotPt :
2058 case Hexagon::LDrid_indexed_cdnNotPt :
2059 case Hexagon::POST_LDrid_cNotPt :
2060 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2061 case Hexagon::LDriw_cNotPt :
2062 case Hexagon::LDriw_cdnNotPt :
2063 case Hexagon::LDriw_indexed_cNotPt :
2064 case Hexagon::LDriw_indexed_cdnNotPt :
2065 case Hexagon::POST_LDriw_cNotPt :
2066 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2067 case Hexagon::LDrih_cNotPt :
2068 case Hexagon::LDrih_cdnNotPt :
2069 case Hexagon::LDrih_indexed_cNotPt :
2070 case Hexagon::LDrih_indexed_cdnNotPt :
2071 case Hexagon::POST_LDrih_cNotPt :
2072 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2073 case Hexagon::LDrib_cNotPt :
2074 case Hexagon::LDrib_cdnNotPt :
2075 case Hexagon::LDrib_indexed_cNotPt :
2076 case Hexagon::LDrib_indexed_cdnNotPt :
2077 case Hexagon::POST_LDrib_cNotPt :
2078 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2079 case Hexagon::LDriuh_cNotPt :
2080 case Hexagon::LDriuh_cdnNotPt :
2081 case Hexagon::LDriuh_indexed_cNotPt :
2082 case Hexagon::LDriuh_indexed_cdnNotPt :
2083 case Hexagon::POST_LDriuh_cNotPt :
2084 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2085 case Hexagon::LDriub_cNotPt :
2086 case Hexagon::LDriub_cdnNotPt :
2087 case Hexagon::LDriub_indexed_cNotPt :
2088 case Hexagon::LDriub_indexed_cdnNotPt :
2089 case Hexagon::POST_LDriub_cNotPt :
2090 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2091 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2092 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2093 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2094 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2095 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2096 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2097 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2098 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2099 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2100 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2101 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2102 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2103 case Hexagon::ADD_ri_cNotPt :
2104 case Hexagon::ADD_ri_cdnNotPt :
2105 case Hexagon::ADD_rr_cNotPt :
2106 case Hexagon::ADD_rr_cdnNotPt :
2107 case Hexagon::XOR_rr_cNotPt :
2108 case Hexagon::XOR_rr_cdnNotPt :
2109 case Hexagon::AND_rr_cNotPt :
2110 case Hexagon::AND_rr_cdnNotPt :
2111 case Hexagon::OR_rr_cNotPt :
2112 case Hexagon::OR_rr_cdnNotPt :
2113 case Hexagon::SUB_rr_cNotPt :
2114 case Hexagon::SUB_rr_cdnNotPt :
2115 case Hexagon::COMBINE_rr_cNotPt :
2116 case Hexagon::COMBINE_rr_cdnNotPt :
2117 case Hexagon::ASLH_cNotPt_V4 :
2118 case Hexagon::ASLH_cdnNotPt_V4 :
2119 case Hexagon::ASRH_cNotPt_V4 :
2120 case Hexagon::ASRH_cdnNotPt_V4 :
2121 case Hexagon::SXTB_cNotPt_V4 :
2122 case Hexagon::SXTB_cdnNotPt_V4 :
2123 case Hexagon::SXTH_cNotPt_V4 :
2124 case Hexagon::SXTH_cdnNotPt_V4 :
2125 case Hexagon::ZXTB_cNotPt_V4 :
2126 case Hexagon::ZXTB_cdnNotPt_V4 :
2127 case Hexagon::ZXTH_cNotPt_V4 :
2128 case Hexagon::ZXTH_cdnNotPt_V4 :
2130 case Hexagon::LDd_GP_cNotPt_V4 :
2131 case Hexagon::LDb_GP_cNotPt_V4 :
2132 case Hexagon::LDub_GP_cNotPt_V4 :
2133 case Hexagon::LDh_GP_cNotPt_V4 :
2134 case Hexagon::LDuh_GP_cNotPt_V4 :
2135 case Hexagon::LDw_GP_cNotPt_V4 :
2136 case Hexagon::STd_GP_cNotPt_V4 :
2137 case Hexagon::STb_GP_cNotPt_V4 :
2138 case Hexagon::STh_GP_cNotPt_V4 :
2139 case Hexagon::STw_GP_cNotPt_V4 :
2140 case Hexagon::LDd_GP_cdnNotPt_V4 :
2141 case Hexagon::LDb_GP_cdnNotPt_V4 :
2142 case Hexagon::LDub_GP_cdnNotPt_V4 :
2143 case Hexagon::LDh_GP_cdnNotPt_V4 :
2144 case Hexagon::LDuh_GP_cdnNotPt_V4 :
2145 case Hexagon::LDw_GP_cdnNotPt_V4 :
2146 case Hexagon::STd_GP_cdnNotPt_V4 :
2147 case Hexagon::STb_GP_cdnNotPt_V4 :
2148 case Hexagon::STh_GP_cdnNotPt_V4 :
2149 case Hexagon::STw_GP_cdnNotPt_V4 :
2152 // return *some value* to avoid compiler warning
2156 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
2157 const HexagonInstrInfo *QII) {
2158 assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
2160 // Post Increment means duplicates. Use dense map to find duplicates in the
2161 // list. Caution: Densemap initializes with the minimum of 64 buckets,
2162 // whereas there are at most 5 operands in the post increment.
2163 DenseMap<unsigned, unsigned> DefRegsSet;
2164 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2165 if (MI->getOperand(opNum).isReg() &&
2166 MI->getOperand(opNum).isDef()) {
2167 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
2170 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2171 if (MI->getOperand(opNum).isReg() &&
2172 MI->getOperand(opNum).isUse()) {
2173 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
2174 return MI->getOperand(opNum);
2178 if (MI->getDesc().mayLoad()) {
2179 // The 2nd operand is always the post increment operand in load.
2180 assert(MI->getOperand(1).isReg() &&
2181 "Post increment operand has be to a register.");
2182 return (MI->getOperand(1));
2184 if (MI->getDesc().mayStore()) {
2185 // The 1st operand is always the post increment operand in store.
2186 assert(MI->getOperand(0).isReg() &&
2187 "Post increment operand has be to a register.");
2188 return (MI->getOperand(0));
2191 // we should never come here.
2192 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
2195 // get the value being stored
2196 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
2197 // value being stored is always the last operand.
2198 return (MI->getOperand(MI->getNumOperands()-1));
2201 // can be new value store?
2202 // Following restrictions are to be respected in convert a store into
2203 // a new value store.
2204 // 1. If an instruction uses auto-increment, its address register cannot
2205 // be a new-value register. Arch Spec 5.4.2.1
2206 // 2. If an instruction uses absolute-set addressing mode,
2207 // its address register cannot be a new-value register.
2208 // Arch Spec 5.4.2.1.TODO: This is not enabled as
2209 // as absolute-set address mode patters are not implemented.
2210 // 3. If an instruction produces a 64-bit result, its registers cannot be used
2211 // as new-value registers. Arch Spec 5.4.2.2.
2212 // 4. If the instruction that sets a new-value register is conditional, then
2213 // the instruction that uses the new-value register must also be conditional,
2214 // and both must always have their predicates evaluate identically.
2215 // Arch Spec 5.4.2.3.
2216 // 5. There is an implied restriction of a packet can not have another store,
2217 // if there is a new value store in the packet. Corollary, if there is
2218 // already a store in a packet, there can not be a new value store.
2219 // Arch Spec: 3.4.4.2
2220 bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
2221 MachineInstr *PacketMI, unsigned DepReg,
2222 std::map <MachineInstr*, SUnit*> MIToSUnit)
2224 // Make sure we are looking at the store
2225 if (!IsNewifyStore(MI))
2228 // Make sure there is dependency and can be new value'ed
2229 if (GetStoreValueOperand(MI).isReg() &&
2230 GetStoreValueOperand(MI).getReg() != DepReg)
2233 const HexagonRegisterInfo* QRI =
2234 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2235 const MCInstrDesc& MCID = PacketMI->getDesc();
2236 // first operand is always the result
2238 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2239 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
2241 // if there is already an store in the packet, no can do new value store
2242 // Arch Spec 3.4.4.2.
2243 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
2244 VE = CurrentPacketMIs.end();
2246 SUnit* PacketSU = MIToSUnit[*VI];
2247 if (PacketSU->getInstr()->getDesc().mayStore() ||
2248 // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
2249 // then we don't need this
2250 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2251 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
2255 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
2256 // new value store constraint: double regs can not feed into new value store
2257 // arch spec section: 5.4.2.2
2261 // Make sure it's NOT the post increment register that we are going to
2263 if (QII->isPostIncrement(MI) &&
2264 MI->getDesc().mayStore() &&
2265 GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
2269 if (QII->isPostIncrement(PacketMI) &&
2270 PacketMI->getDesc().mayLoad() &&
2271 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
2272 // if source is post_inc, or absolute-set addressing,
2273 // it can not feed into new value store
2274 // r3 = memw(r2++#4)
2275 // memw(r30 + #-1404) = r2.new -> can not be new value store
2276 // arch spec section: 5.4.2.1
2280 // If the source that feeds the store is predicated, new value store must
2281 // also be also predicated.
2282 if (QII->isPredicated(PacketMI)) {
2283 if (!QII->isPredicated(MI))
2286 // Check to make sure that they both will have their predicates
2287 // evaluate identically
2288 unsigned predRegNumSrc = 0;
2289 unsigned predRegNumDst = 0;
2290 const TargetRegisterClass* predRegClass = NULL;
2292 // Get predicate register used in the source instruction
2293 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2294 if ( PacketMI->getOperand(opNum).isReg())
2295 predRegNumSrc = PacketMI->getOperand(opNum).getReg();
2296 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
2297 if (predRegClass == &Hexagon::PredRegsRegClass) {
2301 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2302 ("predicate register not found in a predicated PacketMI instruction"));
2304 // Get predicate register used in new-value store instruction
2305 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2306 if ( MI->getOperand(opNum).isReg())
2307 predRegNumDst = MI->getOperand(opNum).getReg();
2308 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
2309 if (predRegClass == &Hexagon::PredRegsRegClass) {
2313 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2314 ("predicate register not found in a predicated MI instruction"));
2316 // New-value register producer and user (store) need to satisfy these
2318 // 1) Both instructions should be predicated on the same register.
2319 // 2) If producer of the new-value register is .new predicated then store
2320 // should also be .new predicated and if producer is not .new predicated
2321 // then store should not be .new predicated.
2322 // 3) Both new-value register producer and user should have same predicate
2323 // sense, i.e, either both should be negated or both should be none negated.
2325 if (( predRegNumDst != predRegNumSrc) ||
2326 QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI) ||
2327 GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
2332 // Make sure that other than the new-value register no other store instruction
2333 // register has been modified in the same packet. Predicate registers can be
2334 // modified by they should not be modified between the producer and the store
2335 // instruction as it will make them both conditional on different values.
2336 // We already know this to be true for all the instructions before and
2337 // including PacketMI. Howerver, we need to perform the check for the
2338 // remaining instructions in the packet.
2340 std::vector<MachineInstr*>::iterator VI;
2341 std::vector<MachineInstr*>::iterator VE;
2342 unsigned StartCheck = 0;
2344 for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
2346 SUnit* TempSU = MIToSUnit[*VI];
2347 MachineInstr* TempMI = TempSU->getInstr();
2349 // Following condition is true for all the instructions until PacketMI is
2350 // reached (StartCheck is set to 0 before the for loop).
2351 // StartCheck flag is 1 for all the instructions after PacketMI.
2352 if (TempMI != PacketMI && !StartCheck) // start processing only after
2353 continue; // encountering PacketMI
2356 if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
2359 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2360 if (MI->getOperand(opNum).isReg() &&
2361 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
2367 // Make sure that for non POST_INC stores:
2368 // 1. The only use of reg is DepReg and no other registers.
2369 // This handles V4 base+index registers.
2370 // The following store can not be dot new.
2371 // Eg. r0 = add(r0, #3)a
2372 // memw(r1+r0<<#2) = r0
2373 if (!QII->isPostIncrement(MI) &&
2374 GetStoreValueOperand(MI).isReg() &&
2375 GetStoreValueOperand(MI).getReg() == DepReg) {
2376 for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
2377 if (MI->getOperand(opNum).isReg() &&
2378 MI->getOperand(opNum).getReg() == DepReg) {
2382 // 2. If data definition is because of implicit definition of the register,
2383 // do not newify the store. Eg.
2384 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
2385 // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
2386 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2387 if (PacketMI->getOperand(opNum).isReg() &&
2388 PacketMI->getOperand(opNum).getReg() == DepReg &&
2389 PacketMI->getOperand(opNum).isDef() &&
2390 PacketMI->getOperand(opNum).isImplicit()) {
2396 // Can be dot new store.
2400 // can this MI to promoted to either
2401 // new value store or new value jump
2402 bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
2403 SUnit *PacketSU, unsigned DepReg,
2404 std::map <MachineInstr*, SUnit*> MIToSUnit,
2405 MachineBasicBlock::iterator &MII)
2408 const HexagonRegisterInfo* QRI =
2409 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2410 if (!QRI->Subtarget.hasV4TOps() ||
2414 MachineInstr *PacketMI = PacketSU->getInstr();
2416 // Check to see the store can be new value'ed.
2417 if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
2420 // Check to see the compare/jump can be new value'ed.
2421 // This is done as a pass on its own. Don't need to check it here.
2425 // Check to see if an instruction can be dot new
2426 // There are three kinds.
2427 // 1. dot new on predicate - V2/V3/V4
2428 // 2. dot new on stores NV/ST - V4
2429 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
2430 bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
2431 SUnit *PacketSU, unsigned DepReg,
2432 std::map <MachineInstr*, SUnit*> MIToSUnit,
2433 MachineBasicBlock::iterator &MII,
2434 const TargetRegisterClass* RC )
2436 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2437 // Already a dot new instruction.
2438 if (QII->isDotNewInst(MI) && !IsNewifyStore(MI))
2441 if (!isNewifiable(MI))
2445 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
2447 else if (RC != &Hexagon::PredRegsRegClass &&
2448 !IsNewifyStore(MI)) // MI is not a new-value store
2451 // Create a dot new machine instruction to see if resources can be
2452 // allocated. If not, bail out now.
2453 int NewOpcode = GetDotNewOp(MI->getOpcode());
2454 const MCInstrDesc &desc = QII->get(NewOpcode);
2456 MachineInstr *NewMI =
2457 MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
2458 bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
2459 MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
2461 if (!ResourcesAvailable)
2464 // new value store only
2465 // new new value jump generated as a passes
2466 if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
2473 // Go through the packet instructions and search for anti dependency
2474 // between them and DepReg from MI
2475 // Consider this case:
2477 // a) %R1<def> = TFRI_cdNotPt %P3, 2
2480 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
2481 // c) %P3<def> = TFR_PdRs %R23
2482 // d) %R1<def> = TFRI_cdnPt %P3, 4
2484 // The P3 from a) and d) will be complements after
2485 // a)'s P3 is converted to .new form
2486 // Anti Dep between c) and b) is irrelevant for this case
2487 bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
2489 std::map <MachineInstr*, SUnit*> MIToSUnit) {
2491 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2492 SUnit* PacketSUDep = MIToSUnit[MI];
2494 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2495 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2497 // We only care for dependencies to predicated instructions
2498 if(!QII->isPredicated(*VIN)) continue;
2500 // Scheduling Unit for current insn in the packet
2501 SUnit* PacketSU = MIToSUnit[*VIN];
2503 // Look at dependencies between current members of the packet
2504 // and predicate defining instruction MI.
2505 // Make sure that dependency is on the exact register
2507 if (PacketSU->isSucc(PacketSUDep)) {
2508 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2509 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
2510 (PacketSU->Succs[i].getKind() == SDep::Anti) &&
2511 (PacketSU->Succs[i].getReg() == DepReg)) {
2522 // Given two predicated instructions, this function detects whether
2523 // the predicates are complements
2524 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
2525 MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
2527 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2528 // Currently can only reason about conditional transfers
2529 if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
2533 // Scheduling unit for candidate
2534 SUnit* SU = MIToSUnit[MI1];
2536 // One corner case deals with the following scenario:
2538 // a) %R24<def> = TFR_cPt %P0, %R25
2542 // b) %R25<def> = TFR_cNotPt %P0, %R24
2543 // c) %P0<def> = CMPEQri %R26, 1
2546 // On general check a) and b) are complements, but
2547 // presence of c) will convert a) to .new form, and
2548 // then it is not a complement
2549 // We attempt to detect it by analyzing existing
2550 // dependencies in the packet
2552 // Analyze relationships between all existing members of the packet.
2553 // Look for Anti dependecy on the same predicate reg
2554 // as used in the candidate
2555 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2556 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2558 // Scheduling Unit for current insn in the packet
2559 SUnit* PacketSU = MIToSUnit[*VIN];
2561 // If this instruction in the packet is succeeded by the candidate...
2562 if (PacketSU->isSucc(SU)) {
2563 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2564 // The corner case exist when there is true data
2565 // dependency between candidate and one of current
2566 // packet members, this dep is on predicate reg, and
2567 // there already exist anti dep on the same pred in
2569 if (PacketSU->Succs[i].getSUnit() == SU &&
2570 Hexagon::PredRegsRegClass.contains(
2571 PacketSU->Succs[i].getReg()) &&
2572 PacketSU->Succs[i].getKind() == SDep::Data &&
2573 // Here I know that *VIN is predicate setting instruction
2574 // with true data dep to candidate on the register
2575 // we care about - c) in the above example.
2576 // Now I need to see if there is an anti dependency
2577 // from c) to any other instruction in the
2578 // same packet on the pred reg of interest
2579 RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
2587 // If the above case does not apply, check regular
2588 // complement condition.
2589 // Check that the predicate register is the same and
2590 // that the predicate sense is different
2591 // We also need to differentiate .old vs. .new:
2592 // !p0 is not complimentary to p0.new
2593 return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
2594 (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
2595 (QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
2598 // initPacketizerState - Initialize packetizer flags
2599 void HexagonPacketizerList::initPacketizerState() {
2602 PromotedToDotNew = false;
2603 GlueToNewValueJump = false;
2604 GlueAllocframeStore = false;
2605 FoundSequentialDependence = false;
2610 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
2611 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
2612 MachineBasicBlock *MBB) {
2613 if (MI->isDebugValue())
2616 // We must print out inline assembly
2617 if (MI->isInlineAsm())
2620 // We check if MI has any functional units mapped to it.
2621 // If it doesn't, we ignore the instruction.
2622 const MCInstrDesc& TID = MI->getDesc();
2623 unsigned SchedClass = TID.getSchedClass();
2624 const InstrStage* IS =
2625 ResourceTracker->getInstrItins()->beginStage(SchedClass);
2626 unsigned FuncUnits = IS->getUnits();
2630 // isSoloInstruction: - Returns true for instructions that must be
2631 // scheduled in their own packet.
2632 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
2634 if (MI->isInlineAsm())
2637 if (MI->isEHLabel())
2640 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
2641 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
2642 // They must not be grouped with other instructions in a packet.
2643 if (IsSchedBarrier(MI))
2649 // isLegalToPacketizeTogether:
2650 // SUI is the current instruction that is out side of the current packet.
2651 // SUJ is the current instruction inside the current packet against which that
2652 // SUI will be packetized.
2653 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
2654 MachineInstr *I = SUI->getInstr();
2655 MachineInstr *J = SUJ->getInstr();
2656 assert(I && J && "Unable to packetize null instruction!");
2658 const MCInstrDesc &MCIDI = I->getDesc();
2659 const MCInstrDesc &MCIDJ = J->getDesc();
2661 MachineBasicBlock::iterator II = I;
2663 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
2664 const HexagonRegisterInfo* QRI =
2665 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2666 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2668 // Inline asm cannot go in the packet.
2669 if (I->getOpcode() == Hexagon::INLINEASM)
2670 llvm_unreachable("Should not meet inline asm here!");
2672 if (isSoloInstruction(I))
2673 llvm_unreachable("Should not meet solo instr here!");
2675 // A save callee-save register function call can only be in a packet
2676 // with instructions that don't write to the callee-save registers.
2677 if ((QII->isSaveCalleeSavedRegsCall(I) &&
2678 DoesModifyCalleeSavedReg(J, QRI)) ||
2679 (QII->isSaveCalleeSavedRegsCall(J) &&
2680 DoesModifyCalleeSavedReg(I, QRI))) {
2685 // Two control flow instructions cannot go in the same packet.
2686 if (IsControlFlow(I) && IsControlFlow(J)) {
2691 // A LoopN instruction cannot appear in the same packet as a jump or call.
2692 if (IsLoopN(I) && ( IsDirectJump(J)
2694 || QII->isDeallocRet(J))) {
2698 if (IsLoopN(J) && ( IsDirectJump(I)
2700 || QII->isDeallocRet(I))) {
2705 // dealloc_return cannot appear in the same packet as a conditional or
2706 // unconditional jump.
2707 if (QII->isDeallocRet(I) && ( MCIDJ.isBranch()
2709 || MCIDJ.isBarrier())) {
2715 // V4 allows dual store. But does not allow second store, if the
2716 // first store is not in SLOT0. New value store, new value jump,
2717 // dealloc_return and memop always take SLOT0.
2718 // Arch spec 3.4.4.2
2719 if (QRI->Subtarget.hasV4TOps()) {
2720 if (MCIDI.mayStore() && MCIDJ.mayStore() &&
2721 (QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
2726 if ((QII->isMemOp(J) && MCIDI.mayStore())
2727 || (MCIDJ.mayStore() && QII->isMemOp(I))
2728 || (QII->isMemOp(J) && QII->isMemOp(I))) {
2734 if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
2739 // If an instruction feeds new value jump, glue it.
2740 MachineBasicBlock::iterator NextMII = I;
2742 MachineInstr *NextMI = NextMII;
2744 if (QII->isNewValueJump(NextMI)) {
2746 bool secondRegMatch = false;
2747 bool maintainNewValueJump = false;
2749 if (NextMI->getOperand(1).isReg() &&
2750 I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
2751 secondRegMatch = true;
2752 maintainNewValueJump = true;
2755 if (!secondRegMatch &&
2756 I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
2757 maintainNewValueJump = true;
2760 for (std::vector<MachineInstr*>::iterator
2761 VI = CurrentPacketMIs.begin(),
2762 VE = CurrentPacketMIs.end();
2763 (VI != VE && maintainNewValueJump); ++VI) {
2764 SUnit* PacketSU = MIToSUnit[*VI];
2766 // NVJ can not be part of the dual jump - Arch Spec: section 7.8
2767 if (PacketSU->getInstr()->getDesc().isCall()) {
2772 // 1. Packet does not have a store in it.
2773 // 2. If the first operand of the nvj is newified, and the second
2774 // operand is also a reg, it (second reg) is not defined in
2776 // 3. If the second operand of the nvj is newified, (which means
2777 // first operand is also a reg), first reg is not defined in
2779 if (PacketSU->getInstr()->getDesc().mayStore() ||
2780 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2782 (!secondRegMatch && NextMI->getOperand(1).isReg() &&
2783 PacketSU->getInstr()->modifiesRegister(
2784 NextMI->getOperand(1).getReg(), QRI)) ||
2787 PacketSU->getInstr()->modifiesRegister(
2788 NextMI->getOperand(0).getReg(), QRI))) {
2794 GlueToNewValueJump = true;
2800 if (SUJ->isSucc(SUI)) {
2801 for (unsigned i = 0;
2802 (i < SUJ->Succs.size()) && !FoundSequentialDependence;
2805 if (SUJ->Succs[i].getSUnit() != SUI) {
2809 SDep::Kind DepType = SUJ->Succs[i].getKind();
2811 // For direct calls:
2812 // Ignore register dependences for call instructions for
2813 // packetization purposes except for those due to r31 and
2814 // predicate registers.
2816 // For indirect calls:
2817 // Same as direct calls + check for true dependences to the register
2818 // used in the indirect call.
2820 // We completely ignore Order dependences for call instructions
2823 // Ignore register dependences for return instructions like jumpr,
2824 // dealloc return unless we have dependencies on the explicit uses
2825 // of the registers used by jumpr (like r31) or dealloc return
2826 // (like r29 or r30).
2828 // TODO: Currently, jumpr is handling only return of r31. So, the
2829 // following logic (specificaly IsCallDependent) is working fine.
2830 // We need to enable jumpr for register other than r31 and then,
2831 // we need to rework the last part, where it handles indirect call
2832 // of that (IsCallDependent) function. Bug 6216 is opened for this.
2834 unsigned DepReg = 0;
2835 const TargetRegisterClass* RC = NULL;
2836 if (DepType == SDep::Data) {
2837 DepReg = SUJ->Succs[i].getReg();
2838 RC = QRI->getMinimalPhysRegClass(DepReg);
2840 if ((MCIDI.isCall() || MCIDI.isReturn()) &&
2841 (!IsRegDependence(DepType) ||
2842 !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
2846 // For instructions that can be promoted to dot-new, try to promote.
2847 else if ((DepType == SDep::Data) &&
2848 CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
2849 PromoteToDotNew(I, DepType, II, RC)) {
2850 PromotedToDotNew = true;
2854 else if ((DepType == SDep::Data) &&
2855 (QII->isNewValueJump(I))) {
2859 // For predicated instructions, if the predicates are complements
2860 // then there can be no dependence.
2861 else if (QII->isPredicated(I) &&
2862 QII->isPredicated(J) &&
2863 ArePredicatesComplements(I, J, MIToSUnit)) {
2867 else if (IsDirectJump(I) &&
2868 !MCIDJ.isBranch() &&
2870 (DepType == SDep::Order)) {
2871 // Ignore Order dependences between unconditional direct branches
2872 // and non-control-flow instructions
2875 else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
2876 (DepType != SDep::Output)) {
2877 // Ignore all dependences for jumps except for true and output
2882 // Ignore output dependences due to superregs. We can
2883 // write to two different subregisters of R1:0 for instance
2884 // in the same cycle
2889 // If neither I nor J defines DepReg, then this is a
2890 // superfluous output dependence. The dependence must be of the
2894 // and there is an output dependence between the two instructions
2897 // We want to ignore these dependences.
2898 // Ideally, the dependence constructor should annotate such
2899 // dependences. We can then avoid this relatively expensive check.
2901 else if (DepType == SDep::Output) {
2902 // DepReg is the register that's responsible for the dependence.
2903 unsigned DepReg = SUJ->Succs[i].getReg();
2905 // Check if I and J really defines DepReg.
2906 if (I->definesRegister(DepReg) ||
2907 J->definesRegister(DepReg)) {
2908 FoundSequentialDependence = true;
2913 // We ignore Order dependences for
2914 // 1. Two loads unless they are volatile.
2915 // 2. Two stores in V4 unless they are volatile.
2916 else if ((DepType == SDep::Order) &&
2917 !I->hasOrderedMemoryRef() &&
2918 !J->hasOrderedMemoryRef()) {
2919 if (QRI->Subtarget.hasV4TOps() &&
2920 // hexagonv4 allows dual store.
2921 MCIDI.mayStore() && MCIDJ.mayStore()) {
2924 // store followed by store-- not OK on V2
2925 // store followed by load -- not OK on all (OK if addresses
2927 // load followed by store -- OK on all
2928 // load followed by load -- OK on all
2929 else if ( !MCIDJ.mayStore()) {
2933 FoundSequentialDependence = true;
2938 // For V4, special case ALLOCFRAME. Even though there is dependency
2939 // between ALLOCAFRAME and subsequent store, allow it to be
2940 // packetized in a same packet. This implies that the store is using
2941 // caller's SP. Hense, offset needs to be updated accordingly.
2942 else if (DepType == SDep::Data
2943 && QRI->Subtarget.hasV4TOps()
2944 && J->getOpcode() == Hexagon::ALLOCFRAME
2945 && (I->getOpcode() == Hexagon::STrid
2946 || I->getOpcode() == Hexagon::STriw
2947 || I->getOpcode() == Hexagon::STrib)
2948 && I->getOperand(0).getReg() == QRI->getStackRegister()
2949 && QII->isValidOffset(I->getOpcode(),
2950 I->getOperand(1).getImm() -
2951 (FrameSize + HEXAGON_LRFP_SIZE)))
2953 GlueAllocframeStore = true;
2954 // Since this store is to be glued with allocframe in the same
2955 // packet, it will use SP of the previous stack frame, i.e
2956 // caller's SP. Therefore, we need to recalculate offset according
2958 I->getOperand(1).setImm(I->getOperand(1).getImm() -
2959 (FrameSize + HEXAGON_LRFP_SIZE));
2963 // Skip over anti-dependences. Two instructions that are
2964 // anti-dependent can share a packet
2966 else if (DepType != SDep::Anti) {
2967 FoundSequentialDependence = true;
2972 if (FoundSequentialDependence) {
2981 // isLegalToPruneDependencies
2982 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
2983 MachineInstr *I = SUI->getInstr();
2984 assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
2986 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
2990 // Check if the instruction was promoted to a dot-new. If so, demote it
2991 // back into a dot-old.
2992 if (PromotedToDotNew) {
2996 // Check if the instruction (must be a store) was glued with an Allocframe
2997 // instruction. If so, restore its offset to its original value, i.e. use
2998 // curent SP instead of caller's SP.
2999 if (GlueAllocframeStore) {
3000 I->getOperand(1).setImm(I->getOperand(1).getImm() +
3001 FrameSize + HEXAGON_LRFP_SIZE);
3009 MachineBasicBlock::iterator
3010 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
3012 MachineBasicBlock::iterator MII = MI;
3013 MachineBasicBlock *MBB = MI->getParent();
3015 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3017 if (GlueToNewValueJump) {
3020 MachineInstr *nvjMI = MII;
3021 assert(ResourceTracker->canReserveResources(MI));
3022 ResourceTracker->reserveResources(MI);
3023 if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
3024 !tryAllocateResourcesForConstExt(MI)) {
3026 ResourceTracker->reserveResources(MI);
3027 assert(canReserveResourcesForConstExt(MI) &&
3028 "Ensure that there is a slot");
3029 reserveResourcesForConstExt(MI);
3030 // Reserve resources for new value jump constant extender.
3031 assert(canReserveResourcesForConstExt(MI) &&
3032 "Ensure that there is a slot");
3033 reserveResourcesForConstExt(nvjMI);
3034 assert(ResourceTracker->canReserveResources(nvjMI) &&
3035 "Ensure that there is a slot");
3037 } else if ( // Extended instruction takes two slots in the packet.
3038 // Try reserve and allocate 4-byte in the current packet first.
3039 (QII->isExtended(nvjMI)
3040 && (!tryAllocateResourcesForConstExt(nvjMI)
3041 || !ResourceTracker->canReserveResources(nvjMI)))
3042 || // For non-extended instruction, no need to allocate extra 4 bytes.
3043 (!QII->isExtended(nvjMI) &&
3044 !ResourceTracker->canReserveResources(nvjMI)))
3047 // A new and empty packet starts.
3048 // We are sure that the resources requirements can be satisfied.
3049 // Therefore, do not need to call "canReserveResources" anymore.
3050 ResourceTracker->reserveResources(MI);
3051 if (QII->isExtended(nvjMI))
3052 reserveResourcesForConstExt(nvjMI);
3054 // Here, we are sure that "reserveResources" would succeed.
3055 ResourceTracker->reserveResources(nvjMI);
3056 CurrentPacketMIs.push_back(MI);
3057 CurrentPacketMIs.push_back(nvjMI);
3059 if ( (QII->isExtended(MI) || QII->isConstExtended(MI))
3060 && ( !tryAllocateResourcesForConstExt(MI)
3061 || !ResourceTracker->canReserveResources(MI)))
3064 // Check if the instruction was promoted to a dot-new. If so, demote it
3065 // back into a dot-old
3066 if (PromotedToDotNew) {
3069 reserveResourcesForConstExt(MI);
3071 // In case that "MI" is not an extended insn,
3072 // the resource availability has already been checked.
3073 ResourceTracker->reserveResources(MI);
3074 CurrentPacketMIs.push_back(MI);
3079 //===----------------------------------------------------------------------===//
3080 // Public Constructor Functions
3081 //===----------------------------------------------------------------------===//
3083 FunctionPass *llvm::createHexagonPacketizer() {
3084 return new HexagonPacketizer();