1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "llvm/Module.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
21 #include "llvm/Transforms/Scalar.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
28 opt<bool> DisableHardwareLoops(
29 "disable-hexagon-hwloops", cl::Hidden,
30 cl::desc("Disable Hardware Loops for Hexagon target"));
32 /// HexagonTargetMachineModule - Note that this is used on hosts that
33 /// cannot link in a library unless there are references into the
34 /// library. In particular, it seems that it is not possible to get
35 /// things to work on Win32 without this. Though it is unused, do not
37 extern "C" int HexagonTargetMachineModule;
38 int HexagonTargetMachineModule = 0;
40 extern "C" void LLVMInitializeHexagonTarget() {
41 // Register the target.
42 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
46 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
49 /// Hexagon_TODO: Do I need an aggregate alignment?
51 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
52 StringRef CPU, StringRef FS,
53 const TargetOptions &Options,
57 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
58 DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") ,
59 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
61 FrameLowering(Subtarget),
62 InstrItins(&Subtarget.getInstrItineraryData()) {
66 // addPassesForOptimizations - Allow the backend (target) to add Target
67 // Independent Optimization passes to the Pass Manager.
68 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
70 PM.add(createConstantPropagationPass());
71 PM.add(createLoopSimplifyPass());
72 PM.add(createDeadCodeEliminationPass());
73 PM.add(createConstantPropagationPass());
74 PM.add(createLoopUnrollPass());
75 PM.add(createLoopStrengthReducePass(getTargetLowering()));
80 /// Hexagon Code Generator Pass Configuration Options.
81 class HexagonPassConfig : public TargetPassConfig {
83 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
84 : TargetPassConfig(TM, PM) {}
86 HexagonTargetMachine &getHexagonTargetMachine() const {
87 return getTM<HexagonTargetMachine>();
90 virtual bool addInstSelector();
91 virtual bool addPreRegAlloc();
92 virtual bool addPostRegAlloc();
93 virtual bool addPreSched2();
94 virtual bool addPreEmitPass();
98 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
99 return new HexagonPassConfig(this, PM);
102 bool HexagonPassConfig::addInstSelector() {
103 PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
104 PM.add(createHexagonISelDag(getHexagonTargetMachine()));
105 PM.add(createHexagonPeephole());
110 bool HexagonPassConfig::addPreRegAlloc() {
111 if (!DisableHardwareLoops) {
112 PM.add(createHexagonHardwareLoops());
118 bool HexagonPassConfig::addPostRegAlloc() {
119 PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
124 bool HexagonPassConfig::addPreSched2() {
125 addPass(IfConverterID);
129 bool HexagonPassConfig::addPreEmitPass() {
131 if (!DisableHardwareLoops) {
132 PM.add(createHexagonFixupHwLoops());
135 // Expand Spill code for predicate registers.
136 PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
138 // Split up TFRcondsets into conditional transfers.
139 PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));