1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/IR/Module.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
25 #include "llvm/Transforms/Scalar.h"
29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
32 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
33 cl::Hidden, cl::ZeroOrMore, cl::init(false),
34 cl::desc("Disable Hexagon CFG Optimization"));
36 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
37 cl::init(true), cl::Hidden, cl::ZeroOrMore,
38 cl::desc("Early expansion of MUX"));
40 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
41 cl::Hidden, cl::desc("Generate \"insert\" instructions"));
43 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
44 cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
46 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
47 cl::Hidden, cl::desc("Generate \"extract\" instructions"));
49 /// HexagonTargetMachineModule - Note that this is used on hosts that
50 /// cannot link in a library unless there are references into the
51 /// library. In particular, it seems that it is not possible to get
52 /// things to work on Win32 without this. Though it is unused, do not
54 extern "C" int HexagonTargetMachineModule;
55 int HexagonTargetMachineModule = 0;
57 extern "C" void LLVMInitializeHexagonTarget() {
58 // Register the target.
59 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
62 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
63 return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
66 static MachineSchedRegistry
67 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
68 createVLIWMachineSched);
71 FunctionPass *createHexagonCFGOptimizer();
72 FunctionPass *createHexagonCommonGEP();
73 FunctionPass *createHexagonCopyToCombine();
74 FunctionPass *createHexagonExpandCondsets();
75 FunctionPass *createHexagonExpandPredSpillCode();
76 FunctionPass *createHexagonFixupHwLoops();
77 FunctionPass *createHexagonGenExtract();
78 FunctionPass *createHexagonGenInsert();
79 FunctionPass *createHexagonHardwareLoops();
80 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
81 CodeGenOpt::Level OptLevel);
82 FunctionPass *createHexagonNewValueJump();
83 FunctionPass *createHexagonPacketizer();
84 FunctionPass *createHexagonPeephole();
85 FunctionPass *createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM);
86 FunctionPass *createHexagonSplitConst32AndConst64();
87 } // end namespace llvm;
89 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
92 /// Hexagon_TODO: Do I need an aggregate alignment?
94 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
95 StringRef CPU, StringRef FS,
96 const TargetOptions &Options,
97 Reloc::Model RM, CodeModel::Model CM,
99 : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
100 Options, RM, CM, OL),
101 TLOF(make_unique<HexagonTargetObjectFile>()),
102 Subtarget(TT, CPU, FS, *this) {
106 HexagonTargetMachine::~HexagonTargetMachine() {}
109 /// Hexagon Code Generator Pass Configuration Options.
110 class HexagonPassConfig : public TargetPassConfig {
112 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
113 : TargetPassConfig(TM, PM) {
114 bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
116 if (EnableExpandCondsets) {
117 Pass *Exp = createHexagonExpandCondsets();
118 insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
123 HexagonTargetMachine &getHexagonTargetMachine() const {
124 return getTM<HexagonTargetMachine>();
128 createMachineScheduler(MachineSchedContext *C) const override {
129 return createVLIWMachineSched(C);
132 void addIRPasses() override;
133 bool addInstSelector() override;
134 void addPreRegAlloc() override;
135 void addPostRegAlloc() override;
136 void addPreSched2() override;
137 void addPreEmitPass() override;
141 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
142 return new HexagonPassConfig(this, PM);
145 void HexagonPassConfig::addIRPasses() {
146 TargetPassConfig::addIRPasses();
147 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
149 addPass(createAtomicExpandPass(TM));
152 addPass(createHexagonCommonGEP());
153 // Replace certain combinations of shifts and ands with extracts.
154 if (EnableGenExtract)
155 addPass(createHexagonGenExtract());
159 bool HexagonPassConfig::addInstSelector() {
160 HexagonTargetMachine &TM = getHexagonTargetMachine();
161 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
164 addPass(createHexagonRemoveExtendArgs(TM));
166 addPass(createHexagonISelDag(TM, getOptLevel()));
169 addPass(createHexagonPeephole());
170 printAndVerify("After hexagon peephole pass");
172 addPass(createHexagonGenInsert(), false);
178 void HexagonPassConfig::addPreRegAlloc() {
179 if (getOptLevel() != CodeGenOpt::None)
180 if (!DisableHardwareLoops)
181 addPass(createHexagonHardwareLoops(), false);
184 void HexagonPassConfig::addPostRegAlloc() {
185 if (getOptLevel() != CodeGenOpt::None)
186 if (!DisableHexagonCFGOpt)
187 addPass(createHexagonCFGOptimizer(), false);
190 void HexagonPassConfig::addPreSched2() {
191 addPass(createHexagonCopyToCombine(), false);
192 if (getOptLevel() != CodeGenOpt::None)
193 addPass(&IfConverterID, false);
194 addPass(createHexagonSplitConst32AndConst64());
197 void HexagonPassConfig::addPreEmitPass() {
198 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
201 addPass(createHexagonNewValueJump(), false);
203 // Expand Spill code for predicate registers.
204 addPass(createHexagonExpandPredSpillCode(), false);
208 if (!DisableHardwareLoops)
209 addPass(createHexagonFixupHwLoops(), false);
210 addPass(createHexagonPacketizer(), false);