1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "llvm/Module.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/PassManager.h"
21 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
22 #include "llvm/Transforms/Scalar.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
29 opt<bool> DisableHardwareLoops(
30 "disable-hexagon-hwloops", cl::Hidden,
31 cl::desc("Disable Hardware Loops for Hexagon target"));
34 opt<bool> DisableHexagonMISched("disable-hexagon-misched",
35 cl::Hidden, cl::ZeroOrMore, cl::init(false),
36 cl::desc("Disable Hexagon MI Scheduling"));
38 /// HexagonTargetMachineModule - Note that this is used on hosts that
39 /// cannot link in a library unless there are references into the
40 /// library. In particular, it seems that it is not possible to get
41 /// things to work on Win32 without this. Though it is unused, do not
43 extern "C" int HexagonTargetMachineModule;
44 int HexagonTargetMachineModule = 0;
46 extern "C" void LLVMInitializeHexagonTarget() {
47 // Register the target.
48 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
51 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
52 return new VLIWMachineScheduler(C, new ConvergingVLIWScheduler());
55 static MachineSchedRegistry
56 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
57 createVLIWMachineSched);
59 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
62 /// Hexagon_TODO: Do I need an aggregate alignment?
64 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
65 StringRef CPU, StringRef FS,
66 const TargetOptions &Options,
70 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
72 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
73 "f64:64:64-f32:32:32-a0:0-n32") ,
74 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
76 FrameLowering(Subtarget),
77 InstrItins(&Subtarget.getInstrItineraryData()),
78 STTI(&TLInfo), VTTI(&TLInfo) {
82 // addPassesForOptimizations - Allow the backend (target) to add Target
83 // Independent Optimization passes to the Pass Manager.
84 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
86 PM.add(createConstantPropagationPass());
87 PM.add(createLoopSimplifyPass());
88 PM.add(createDeadCodeEliminationPass());
89 PM.add(createConstantPropagationPass());
90 PM.add(createLoopUnrollPass());
91 PM.add(createLoopStrengthReducePass());
96 /// Hexagon Code Generator Pass Configuration Options.
97 class HexagonPassConfig : public TargetPassConfig {
99 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
100 : TargetPassConfig(TM, PM) {
101 // Enable MI scheduler.
102 if (!DisableHexagonMISched) {
103 enablePass(&MachineSchedulerID);
104 MachineSchedRegistry::setDefault(createVLIWMachineSched);
108 HexagonTargetMachine &getHexagonTargetMachine() const {
109 return getTM<HexagonTargetMachine>();
112 virtual bool addInstSelector();
113 virtual bool addPreRegAlloc();
114 virtual bool addPostRegAlloc();
115 virtual bool addPreSched2();
116 virtual bool addPreEmitPass();
120 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
121 return new HexagonPassConfig(this, PM);
124 bool HexagonPassConfig::addInstSelector() {
125 addPass(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
126 addPass(createHexagonISelDag(getHexagonTargetMachine()));
127 addPass(createHexagonPeephole());
132 bool HexagonPassConfig::addPreRegAlloc() {
133 if (!DisableHardwareLoops) {
134 addPass(createHexagonHardwareLoops());
139 bool HexagonPassConfig::addPostRegAlloc() {
140 addPass(createHexagonCFGOptimizer(getHexagonTargetMachine()));
145 bool HexagonPassConfig::addPreSched2() {
146 addPass(&IfConverterID);
150 bool HexagonPassConfig::addPreEmitPass() {
152 if (!DisableHardwareLoops) {
153 addPass(createHexagonFixupHwLoops());
156 addPass(createHexagonNewValueJump());
158 // Expand Spill code for predicate registers.
159 addPass(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
161 // Split up TFRcondsets into conditional transfers.
162 addPass(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
165 addPass(createHexagonPacketizer());