1 //===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Hexagon specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonSubtarget.h"
16 #include "HexagonRegisterInfo.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/ErrorHandling.h"
21 #define GET_SUBTARGETINFO_CTOR
22 #define GET_SUBTARGETINFO_TARGET_DESC
23 #include "HexagonGenSubtargetInfo.inc"
26 EnableV3("enable-hexagon-v3", cl::Hidden,
27 cl::desc("Enable Hexagon V3 instructions."));
31 "enable-hexagon-memops",
32 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed,
33 cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
37 "enable-hexagon-ieee-rnd-near",
38 cl::Hidden, cl::ZeroOrMore, cl::init(false),
39 cl::desc("Generate non-chopped conversion from fp to int for Hexagon target."));
41 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
42 HexagonGenSubtargetInfo(TT, CPU, FS),
43 HexagonArchVersion(V2),
44 CPUString(CPU.str()) {
45 ParseSubtargetFeatures(CPU, FS);
47 switch(HexagonArchVersion) {
48 case HexagonSubtarget::V2:
50 case HexagonSubtarget::V3:
53 case HexagonSubtarget::V4:
55 case HexagonSubtarget::V5:
58 llvm_unreachable("Unknown Architecture Version.");
61 // Initialize scheduling itinerary for the specified CPU.
62 InstrItins = getInstrItineraryForCPU(CPUString);
64 // Max issue per cycle == bundle width.
65 InstrItins.IssueWidth = 4;
72 if (EnableIEEERndNear)
73 ModeIEEERndNear = true;
75 ModeIEEERndNear = false;