1 //===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Hexagon specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonSubtarget.h"
16 #include "HexagonRegisterInfo.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/ErrorHandling.h"
23 #define DEBUG_TYPE "hexagon-subtarget"
25 #define GET_SUBTARGETINFO_CTOR
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #include "HexagonGenSubtargetInfo.inc"
29 static cl::opt<bool> EnableMemOps("enable-hexagon-memops",
30 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
31 cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
33 static cl::opt<bool> DisableMemOps("disable-hexagon-memops",
34 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
35 cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"));
37 static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
38 cl::Hidden, cl::ZeroOrMore, cl::init(false),
39 cl::desc("Generate non-chopped conversion from fp to int."));
41 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
42 cl::Hidden, cl::ZeroOrMore, cl::init(true));
44 static cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double",
45 cl::Hidden, cl::ZeroOrMore, cl::init(false),
46 cl::desc("Enable Hexagon Double Vector eXtensions"));
48 static cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx",
49 cl::Hidden, cl::ZeroOrMore, cl::init(false),
50 cl::desc("Enable Hexagon Vector eXtensions"));
52 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
53 cl::Hidden, cl::ZeroOrMore, cl::init(false),
54 cl::desc("Disable Hexagon MI Scheduling"));
56 void HexagonSubtarget::initializeEnvironment() {
58 ModeIEEERndNear = false;
59 UseBSBScheduling = false;
63 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
64 CPUString = HEXAGON_MC::selectHexagonCPU(getTargetTriple(), CPU);
66 static std::map<StringRef, HexagonArchEnum> CpuTable {
69 { "hexagonv55", V55 },
70 { "hexagonv60", V60 },
73 auto foundIt = CpuTable.find(CPUString);
74 if (foundIt != CpuTable.end())
75 HexagonArchVersion = foundIt->second;
77 llvm_unreachable("Unrecognized Hexagon processor version");
81 ParseSubtargetFeatures(CPUString, FS);
83 if (EnableHexagonHVX.getPosition())
84 UseHVXOps = EnableHexagonHVX;
85 if (EnableHexagonHVXDouble.getPosition())
86 UseHVXDblOps = EnableHexagonHVXDouble;
91 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
92 StringRef FS, const TargetMachine &TM)
93 : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
94 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
97 initializeEnvironment();
99 // Initialize scheduling itinerary for the specified CPU.
100 InstrItins = getInstrItineraryForCPU(CPUString);
102 // UseMemOps on by default unless disabled explicitly
105 else if (EnableMemOps)
110 if (EnableIEEERndNear)
111 ModeIEEERndNear = true;
113 ModeIEEERndNear = false;
115 UseBSBScheduling = hasV60TOps() && EnableBSBSched;
118 // Pin the vtable to this file.
119 void HexagonSubtarget::anchor() {}
121 bool HexagonSubtarget::enableMachineScheduler() const {
122 if (DisableHexagonMISched.getNumOccurrences())
123 return !DisableHexagonMISched;